ds1307.c revision 1.13.4.1
1 /* $NetBSD: ds1307.c,v 1.13.4.1 2012/04/17 00:07:30 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.13.4.1 2012/04/17 00:07:30 yamt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_model { 56 uint16_t dm_model; 57 uint8_t dm_ch_reg; 58 uint8_t dm_ch_value; 59 uint8_t dm_rtc_start; 60 uint8_t dm_rtc_size; 61 uint8_t dm_nvram_start; 62 uint8_t dm_nvram_size; 63 uint8_t dm_flags; 64 #define DSRTC_FLAG_CLOCK_HOLD 1 65 #define DSRTC_FLAG_BCD 2 66 }; 67 68 static const struct dsrtc_model dsrtc_models[] = { 69 { 70 .dm_model = 1307, 71 .dm_ch_reg = DSXXXX_SECONDS, 72 .dm_ch_value = DS1307_SECONDS_CH, 73 .dm_rtc_start = DS1307_RTC_START, 74 .dm_rtc_size = DS1307_RTC_SIZE, 75 .dm_nvram_start = DS1307_NVRAM_START, 76 .dm_nvram_size = DS1307_NVRAM_SIZE, 77 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 78 }, { 79 .dm_model = 1339, 80 .dm_rtc_start = DS1339_RTC_START, 81 .dm_rtc_size = DS1339_RTC_SIZE, 82 .dm_flags = DSRTC_FLAG_BCD, 83 }, { 84 .dm_model = 1672, 85 .dm_rtc_start = DS1672_RTC_START, 86 .dm_rtc_size = DS1672_RTC_SIZE, 87 .dm_flags = 0, 88 }, { 89 .dm_model = 3232, 90 .dm_rtc_start = DS3232_RTC_START, 91 .dm_rtc_size = DS3232_RTC_SIZE, 92 .dm_nvram_start = DS3232_NVRAM_START, 93 .dm_nvram_size = DS3232_NVRAM_SIZE, 94 .dm_flags = DSRTC_FLAG_BCD, 95 }, 96 }; 97 98 struct dsrtc_softc { 99 device_t sc_dev; 100 i2c_tag_t sc_tag; 101 uint8_t sc_address; 102 bool sc_open; 103 struct dsrtc_model sc_model; 104 struct todr_chip_handle sc_todr; 105 }; 106 107 static void dsrtc_attach(device_t, device_t, void *); 108 static int dsrtc_match(device_t, cfdata_t, void *); 109 110 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 111 dsrtc_match, dsrtc_attach, NULL, NULL); 112 extern struct cfdriver dsrtc_cd; 113 114 dev_type_open(dsrtc_open); 115 dev_type_close(dsrtc_close); 116 dev_type_read(dsrtc_read); 117 dev_type_write(dsrtc_write); 118 119 const struct cdevsw dsrtc_cdevsw = { 120 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 121 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 122 }; 123 124 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 125 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 126 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 127 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 128 129 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 130 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 131 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 132 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 133 134 static const struct dsrtc_model * 135 dsrtc_model(u_int model) 136 { 137 /* no model given, assume it's a DS1307 (the first one) */ 138 if (model == 0) 139 return &dsrtc_models[0]; 140 141 for (const struct dsrtc_model *dm = dsrtc_models; 142 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 143 if (dm->dm_model == model) 144 return dm; 145 } 146 return NULL; 147 } 148 149 static int 150 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 151 { 152 struct i2c_attach_args *ia = arg; 153 154 if (ia->ia_name) { 155 /* direct config - check name */ 156 if (strcmp(ia->ia_name, "dsrtc") == 0) 157 return 1; 158 } else { 159 /* indirect config - check typical address */ 160 if (ia->ia_addr == DS1307_ADDR) 161 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 162 } 163 return 0; 164 } 165 166 static void 167 dsrtc_attach(device_t parent, device_t self, void *arg) 168 { 169 struct dsrtc_softc *sc = device_private(self); 170 struct i2c_attach_args *ia = arg; 171 const struct dsrtc_model * const dm = 172 dsrtc_model(device_cfdata(self)->cf_flags); 173 174 aprint_naive(": Real-time Clock%s\n", 175 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 176 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 177 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 178 179 sc->sc_tag = ia->ia_tag; 180 sc->sc_address = ia->ia_addr; 181 sc->sc_model = *dm; 182 sc->sc_dev = self; 183 sc->sc_open = 0; 184 sc->sc_todr.cookie = sc; 185 if (dm->dm_flags & DSRTC_FLAG_BCD) { 186 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 187 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 188 } else { 189 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 190 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 191 } 192 sc->sc_todr.todr_setwen = NULL; 193 194 todr_attach(&sc->sc_todr); 195 } 196 197 /*ARGSUSED*/ 198 int 199 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 200 { 201 struct dsrtc_softc *sc; 202 203 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 204 return ENXIO; 205 206 /* XXX: Locking */ 207 if (sc->sc_open) 208 return EBUSY; 209 210 sc->sc_open = true; 211 return 0; 212 } 213 214 /*ARGSUSED*/ 215 int 216 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 217 { 218 struct dsrtc_softc *sc; 219 220 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 221 return ENXIO; 222 223 sc->sc_open = false; 224 return 0; 225 } 226 227 /*ARGSUSED*/ 228 int 229 dsrtc_read(dev_t dev, struct uio *uio, int flags) 230 { 231 struct dsrtc_softc *sc; 232 int error; 233 234 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 235 return ENXIO; 236 237 const struct dsrtc_model * const dm = &sc->sc_model; 238 if (uio->uio_offset >= dm->dm_nvram_size) 239 return EINVAL; 240 241 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 242 return error; 243 244 KASSERT(uio->uio_offset >= 0); 245 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 246 uint8_t ch, cmd; 247 const u_int a = uio->uio_offset; 248 cmd = a + dm->dm_nvram_start; 249 if ((error = iic_exec(sc->sc_tag, 250 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 251 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 252 iic_release_bus(sc->sc_tag, 0); 253 aprint_error_dev(sc->sc_dev, 254 "dsrtc_read: read failed at 0x%x\n", a); 255 return error; 256 } 257 if ((error = uiomove(&ch, 1, uio)) != 0) { 258 iic_release_bus(sc->sc_tag, 0); 259 return error; 260 } 261 } 262 263 iic_release_bus(sc->sc_tag, 0); 264 265 return 0; 266 } 267 268 /*ARGSUSED*/ 269 int 270 dsrtc_write(dev_t dev, struct uio *uio, int flags) 271 { 272 struct dsrtc_softc *sc; 273 int error; 274 275 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 276 return ENXIO; 277 278 const struct dsrtc_model * const dm = &sc->sc_model; 279 if (uio->uio_offset >= dm->dm_nvram_size) 280 return EINVAL; 281 282 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 283 return error; 284 285 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 286 uint8_t cmdbuf[2]; 287 const u_int a = (int)uio->uio_offset; 288 cmdbuf[0] = a + dm->dm_nvram_start; 289 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 290 break; 291 292 if ((error = iic_exec(sc->sc_tag, 293 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 294 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 295 aprint_error_dev(sc->sc_dev, 296 "dsrtc_write: write failed at 0x%x\n", a); 297 break; 298 } 299 } 300 301 iic_release_bus(sc->sc_tag, 0); 302 303 return error; 304 } 305 306 static int 307 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 308 { 309 struct dsrtc_softc *sc = ch->cookie; 310 struct clock_ymdhms check; 311 int retries; 312 313 memset(dt, 0, sizeof(*dt)); 314 memset(&check, 0, sizeof(check)); 315 316 /* 317 * Since we don't support Burst Read, we have to read the clock twice 318 * until we get two consecutive identical results. 319 */ 320 retries = 5; 321 do { 322 dsrtc_clock_read_ymdhms(sc, dt); 323 dsrtc_clock_read_ymdhms(sc, &check); 324 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 325 326 return 0; 327 } 328 329 static int 330 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 331 { 332 struct dsrtc_softc *sc = ch->cookie; 333 334 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 335 return -1; 336 337 return 0; 338 } 339 340 static int 341 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 342 { 343 struct dsrtc_model * const dm = &sc->sc_model; 344 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 345 346 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 347 348 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 349 aprint_error_dev(sc->sc_dev, 350 "dsrtc_clock_read: failed to acquire I2C bus\n"); 351 return 0; 352 } 353 354 /* Read each RTC register in order. */ 355 for (u_int i = 0; i < dm->dm_rtc_size; i++) { 356 cmdbuf[0] = dm->dm_rtc_start + i; 357 358 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 359 sc->sc_address, cmdbuf, 1, 360 &bcd[i], 1, I2C_F_POLL)) { 361 iic_release_bus(sc->sc_tag, I2C_F_POLL); 362 aprint_error_dev(sc->sc_dev, 363 "dsrtc_clock_read: failed to read rtc " 364 "at 0x%x\n", i); 365 return 0; 366 } 367 } 368 369 /* Done with I2C */ 370 iic_release_bus(sc->sc_tag, I2C_F_POLL); 371 372 /* 373 * Convert the RTC's register values into something useable 374 */ 375 dt->dt_sec = FROMBCD(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 376 dt->dt_min = FROMBCD(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 377 378 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 379 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 380 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 381 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 382 dt->dt_hour += 12; 383 } else 384 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 385 DSXXXX_HOURS_24MASK); 386 387 dt->dt_day = FROMBCD(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 388 dt->dt_mon = FROMBCD(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 389 390 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 391 dt->dt_year = FROMBCD(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 392 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 393 dt->dt_year += 100; 394 395 return 1; 396 } 397 398 static int 399 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 400 { 401 struct dsrtc_model * const dm = &sc->sc_model; 402 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 403 404 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 405 406 /* 407 * Convert our time representation into something the DSXXXX 408 * can understand. 409 */ 410 bcd[DSXXXX_SECONDS] = TOBCD(dt->dt_sec); 411 bcd[DSXXXX_MINUTES] = TOBCD(dt->dt_min); 412 bcd[DSXXXX_HOURS] = TOBCD(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 413 bcd[DSXXXX_DATE] = TOBCD(dt->dt_day); 414 bcd[DSXXXX_DAY] = TOBCD(dt->dt_wday); 415 bcd[DSXXXX_MONTH] = TOBCD(dt->dt_mon); 416 bcd[DSXXXX_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 417 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 418 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 419 420 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 421 aprint_error_dev(sc->sc_dev, 422 "dsrtc_clock_write: failed to acquire I2C bus\n"); 423 return 0; 424 } 425 426 /* Stop the clock */ 427 cmdbuf[0] = dm->dm_ch_reg; 428 429 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 430 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 431 iic_release_bus(sc->sc_tag, I2C_F_POLL); 432 aprint_error_dev(sc->sc_dev, 433 "dsrtc_clock_write: failed to read Hold Clock\n"); 434 return 0; 435 } 436 437 cmdbuf[1] |= dm->dm_ch_value; 438 439 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 440 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 441 iic_release_bus(sc->sc_tag, I2C_F_POLL); 442 aprint_error_dev(sc->sc_dev, 443 "dsrtc_clock_write: failed to write Hold Clock\n"); 444 return 0; 445 } 446 447 /* 448 * Write registers in reverse order. The last write (to the Seconds 449 * register) will undo the Clock Hold, above. 450 */ 451 uint8_t op = I2C_OP_WRITE; 452 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 453 cmdbuf[0] = dm->dm_rtc_start + i; 454 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 455 op = I2C_OP_WRITE_WITH_STOP; 456 } 457 if (iic_exec(sc->sc_tag, op, sc->sc_address, 458 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 459 iic_release_bus(sc->sc_tag, I2C_F_POLL); 460 aprint_error_dev(sc->sc_dev, 461 "dsrtc_clock_write: failed to write rtc " 462 " at 0x%x\n", i); 463 /* XXX: Clock Hold is likely still asserted! */ 464 return 0; 465 } 466 } 467 /* 468 * If the clock hold register isn't the same register as seconds, 469 * we need to reeanble the clock. 470 */ 471 if (op != I2C_OP_WRITE_WITH_STOP) { 472 cmdbuf[0] = dm->dm_ch_reg; 473 cmdbuf[1] &= ~dm->dm_ch_value; 474 475 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 476 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 477 iic_release_bus(sc->sc_tag, I2C_F_POLL); 478 aprint_error_dev(sc->sc_dev, 479 "dsrtc_clock_write: failed to Hold Clock\n"); 480 return 0; 481 } 482 } 483 484 iic_release_bus(sc->sc_tag, I2C_F_POLL); 485 486 return 1; 487 } 488 489 static int 490 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 491 { 492 struct dsrtc_softc *sc = ch->cookie; 493 struct timeval check; 494 int retries; 495 496 memset(tv, 0, sizeof(*tv)); 497 memset(&check, 0, sizeof(check)); 498 499 /* 500 * Since we don't support Burst Read, we have to read the clock twice 501 * until we get two consecutive identical results. 502 */ 503 retries = 5; 504 do { 505 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 506 dsrtc_clock_read_timeval(sc, &check.tv_sec); 507 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 508 509 return 0; 510 } 511 512 static int 513 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 514 { 515 struct dsrtc_softc *sc = ch->cookie; 516 517 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 518 return -1; 519 520 return 0; 521 } 522 523 /* 524 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 525 * it, since some I2C controllers don't support anything other than single-byte 526 * transfers. 527 */ 528 static int 529 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 530 { 531 const struct dsrtc_model * const dm = &sc->sc_model; 532 uint8_t buf[4]; 533 534 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 535 aprint_error_dev(sc->sc_dev, "%s: failed to acquire I2C bus\n", 536 __func__); 537 return (0); 538 } 539 540 /* read all registers: */ 541 uint8_t reg = dm->dm_rtc_start; 542 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, ®, 1, 543 buf, 4, I2C_F_POLL)) { 544 iic_release_bus(sc->sc_tag, I2C_F_POLL); 545 aprint_error_dev(sc->sc_dev, "%s: failed to read rtc\n", 546 __func__); 547 return (0); 548 } 549 550 /* Done with I2C */ 551 iic_release_bus(sc->sc_tag, I2C_F_POLL); 552 553 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 554 *tp = v; 555 556 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 557 __func__, v); 558 559 return (1); 560 } 561 562 static int 563 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 564 { 565 const struct dsrtc_model * const dm = &sc->sc_model; 566 size_t buflen = dm->dm_rtc_size + 2; 567 uint8_t buf[buflen]; 568 569 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 570 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 571 572 buf[0] = dm->dm_rtc_start; 573 buf[1] = (t >> 0) & 0xff; 574 buf[2] = (t >> 8) & 0xff; 575 buf[3] = (t >> 16) & 0xff; 576 buf[4] = (t >> 24) & 0xff; 577 buf[5] = 0; 578 579 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 580 aprint_error_dev(sc->sc_dev, "%s: failed to acquire I2C bus\n", 581 __func__); 582 return (0); 583 } 584 585 /* send data */ 586 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 587 &buf, buflen, NULL, 0, I2C_F_POLL)) { 588 iic_release_bus(sc->sc_tag, I2C_F_POLL); 589 aprint_error_dev(sc->sc_dev, "%s: failed to set time\n", 590 __func__); 591 return (0); 592 } 593 594 iic_release_bus(sc->sc_tag, I2C_F_POLL); 595 596 return (1); 597 } 598
Indexes created Thu Oct 02 14:10:14 GMT 2025