ds1307.c revision 1.13.8.1
1 /* $NetBSD: ds1307.c,v 1.13.8.1 2012/02/18 07:34:12 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.13.8.1 2012/02/18 07:34:12 mrg Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void dsrtc_attach(device_t, device_t, void *); 64 static int dsrtc_match(device_t, cfdata_t, void *); 65 66 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 67 dsrtc_match, dsrtc_attach, NULL, NULL); 68 extern struct cfdriver dsrtc_cd; 69 70 dev_type_open(dsrtc_open); 71 dev_type_close(dsrtc_close); 72 dev_type_read(dsrtc_read); 73 dev_type_write(dsrtc_write); 74 75 const struct cdevsw dsrtc_cdevsw = { 76 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *); 81 static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *); 82 static int dsrtc_gettime(struct todr_chip_handle *, struct clock_ymdhms *); 83 static int dsrtc_settime(struct todr_chip_handle *, struct clock_ymdhms *); 84 85 static int 86 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 87 { 88 struct i2c_attach_args *ia = arg; 89 90 if (ia->ia_name) { 91 /* direct config - check name */ 92 if (strcmp(ia->ia_name, "dsrtc") == 0) 93 return 1; 94 } else { 95 /* indirect config - check typical address */ 96 if (ia->ia_addr == DS1307_ADDR) 97 return 1; 98 } 99 return 0; 100 } 101 102 static void 103 dsrtc_attach(device_t parent, device_t self, void *arg) 104 { 105 struct dsrtc_softc *sc = device_private(self); 106 struct i2c_attach_args *ia = arg; 107 108 aprint_naive(": Real-time Clock/NVRAM\n"); 109 aprint_normal(": DS1307 Real-time Clock/NVRAM\n"); 110 111 sc->sc_tag = ia->ia_tag; 112 sc->sc_address = ia->ia_addr; 113 sc->sc_dev = self; 114 sc->sc_open = 0; 115 sc->sc_todr.cookie = sc; 116 sc->sc_todr.todr_gettime = NULL; 117 sc->sc_todr.todr_settime = NULL; 118 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime; 119 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime; 120 sc->sc_todr.todr_setwen = NULL; 121 122 todr_attach(&sc->sc_todr); 123 } 124 125 /*ARGSUSED*/ 126 int 127 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 128 { 129 struct dsrtc_softc *sc; 130 131 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 132 return ENXIO; 133 134 /* XXX: Locking */ 135 136 if (sc->sc_open) 137 return EBUSY; 138 139 sc->sc_open = 1; 140 return 0; 141 } 142 143 /*ARGSUSED*/ 144 int 145 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 146 { 147 struct dsrtc_softc *sc; 148 149 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 150 return ENXIO; 151 152 sc->sc_open = 0; 153 return 0; 154 } 155 156 /*ARGSUSED*/ 157 int 158 dsrtc_read(dev_t dev, struct uio *uio, int flags) 159 { 160 struct dsrtc_softc *sc; 161 u_int8_t ch, cmdbuf[1]; 162 int a, error; 163 164 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 165 return ENXIO; 166 167 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 168 return EINVAL; 169 170 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 171 return error; 172 173 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 174 a = (int)uio->uio_offset; 175 cmdbuf[0] = a + DS1307_NVRAM_START; 176 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 177 sc->sc_address, cmdbuf, 1, 178 &ch, 1, 0)) != 0) { 179 iic_release_bus(sc->sc_tag, 0); 180 aprint_error_dev(sc->sc_dev, 181 "dsrtc_read: read failed at 0x%x\n", a); 182 return error; 183 } 184 if ((error = uiomove(&ch, 1, uio)) != 0) { 185 iic_release_bus(sc->sc_tag, 0); 186 return error; 187 } 188 } 189 190 iic_release_bus(sc->sc_tag, 0); 191 192 return 0; 193 } 194 195 /*ARGSUSED*/ 196 int 197 dsrtc_write(dev_t dev, struct uio *uio, int flags) 198 { 199 struct dsrtc_softc *sc; 200 u_int8_t cmdbuf[2]; 201 int a, error; 202 203 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 204 return ENXIO; 205 206 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 207 return EINVAL; 208 209 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 210 return error; 211 212 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 213 a = (int)uio->uio_offset; 214 cmdbuf[0] = a + DS1307_NVRAM_START; 215 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 216 break; 217 218 if ((error = iic_exec(sc->sc_tag, 219 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 220 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 221 aprint_error_dev(sc->sc_dev, 222 "dsrtc_write: write failed at 0x%x\n", a); 223 break; 224 } 225 } 226 227 iic_release_bus(sc->sc_tag, 0); 228 229 return error; 230 } 231 232 static int 233 dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 234 { 235 struct dsrtc_softc *sc = ch->cookie; 236 struct clock_ymdhms check; 237 int retries; 238 239 memset(dt, 0, sizeof(*dt)); 240 memset(&check, 0, sizeof(check)); 241 242 /* 243 * Since we don't support Burst Read, we have to read the clock twice 244 * until we get two consecutive identical results. 245 */ 246 retries = 5; 247 do { 248 dsrtc_clock_read(sc, dt); 249 dsrtc_clock_read(sc, &check); 250 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 251 252 return 0; 253 } 254 255 static int 256 dsrtc_settime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 257 { 258 struct dsrtc_softc *sc = ch->cookie; 259 260 if (dsrtc_clock_write(sc, dt) == 0) 261 return -1; 262 263 return 0; 264 } 265 266 static int 267 dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 268 { 269 u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1]; 270 int i; 271 272 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 273 aprint_error_dev(sc->sc_dev, 274 "dsrtc_clock_read: failed to acquire I2C bus\n"); 275 return 0; 276 } 277 278 /* Read each RTC register in order. */ 279 for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) { 280 cmdbuf[0] = i; 281 282 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 283 sc->sc_address, cmdbuf, 1, 284 &bcd[i], 1, I2C_F_POLL)) { 285 iic_release_bus(sc->sc_tag, I2C_F_POLL); 286 aprint_error_dev(sc->sc_dev, 287 "dsrtc_clock_read: failed to read rtc " 288 "at 0x%x\n", i); 289 return 0; 290 } 291 } 292 293 /* Done with I2C */ 294 iic_release_bus(sc->sc_tag, I2C_F_POLL); 295 296 /* 297 * Convert the DS1307's register values into something useable 298 */ 299 dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK); 300 dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK); 301 302 if ((bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_MODE) != 0) { 303 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 304 DS1307_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 305 if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM) 306 dt->dt_hour += 12; 307 } else 308 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 309 DS1307_HOURS_24MASK); 310 311 dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK); 312 dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK); 313 314 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 315 dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR; 316 317 return 1; 318 } 319 320 static int 321 dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 322 { 323 uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2]; 324 int i; 325 326 /* 327 * Convert our time representation into something the DS1307 328 * can understand. 329 */ 330 bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec); 331 bcd[DS1307_MINUTES] = TOBCD(dt->dt_min); 332 bcd[DS1307_HOURS] = TOBCD(dt->dt_hour); /* DS1307_HOURS_12HRS_MODE=0 */ 333 bcd[DS1307_DATE] = TOBCD(dt->dt_day); 334 bcd[DS1307_DAY] = TOBCD(dt->dt_wday); 335 bcd[DS1307_MONTH] = TOBCD(dt->dt_mon); 336 bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 337 338 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 339 aprint_error_dev(sc->sc_dev, 340 "dsrtc_clock_write: failed to acquire I2C bus\n"); 341 return 0; 342 } 343 344 /* Stop the clock */ 345 cmdbuf[0] = DS1307_SECONDS; 346 cmdbuf[1] = DS1307_SECONDS_CH; 347 348 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 349 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 350 iic_release_bus(sc->sc_tag, I2C_F_POLL); 351 aprint_error_dev(sc->sc_dev, 352 "dsrtc_clock_write: failed to Hold Clock\n"); 353 return 0; 354 } 355 356 /* 357 * Write registers in reverse order. The last write (to the Seconds 358 * register) will undo the Clock Hold, above. 359 */ 360 for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) { 361 cmdbuf[0] = i; 362 if (iic_exec(sc->sc_tag, 363 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 364 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 365 I2C_F_POLL)) { 366 iic_release_bus(sc->sc_tag, I2C_F_POLL); 367 aprint_error_dev(sc->sc_dev, 368 "dsrtc_clock_write: failed to write rtc " 369 " at 0x%x\n", i); 370 /* XXX: Clock Hold is likely still asserted! */ 371 return 0; 372 } 373 } 374 375 iic_release_bus(sc->sc_tag, I2C_F_POLL); 376 377 return 1; 378 } 379
Indexes created Thu Oct 02 14:10:14 GMT 2025