ds1307.c revision 1.16
1 /* $NetBSD: ds1307.c,v 1.16 2012/07/25 03:07:37 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.16 2012/07/25 03:07:37 matt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_model { 56 uint16_t dm_model; 57 uint8_t dm_ch_reg; 58 uint8_t dm_ch_value; 59 uint8_t dm_rtc_start; 60 uint8_t dm_rtc_size; 61 uint8_t dm_nvram_start; 62 uint8_t dm_nvram_size; 63 uint8_t dm_flags; 64 #define DSRTC_FLAG_CLOCK_HOLD 1 65 #define DSRTC_FLAG_BCD 2 66 }; 67 68 static const struct dsrtc_model dsrtc_models[] = { 69 { 70 .dm_model = 1307, 71 .dm_ch_reg = DSXXXX_SECONDS, 72 .dm_ch_value = DS1307_SECONDS_CH, 73 .dm_rtc_start = DS1307_RTC_START, 74 .dm_rtc_size = DS1307_RTC_SIZE, 75 .dm_nvram_start = DS1307_NVRAM_START, 76 .dm_nvram_size = DS1307_NVRAM_SIZE, 77 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 78 }, { 79 .dm_model = 1339, 80 .dm_rtc_start = DS1339_RTC_START, 81 .dm_rtc_size = DS1339_RTC_SIZE, 82 .dm_flags = DSRTC_FLAG_BCD, 83 }, { 84 .dm_model = 1672, 85 .dm_rtc_start = DS1672_RTC_START, 86 .dm_rtc_size = DS1672_RTC_SIZE, 87 .dm_flags = 0, 88 }, { 89 .dm_model = 3232, 90 .dm_rtc_start = DS3232_RTC_START, 91 .dm_rtc_size = DS3232_RTC_SIZE, 92 .dm_nvram_start = DS3232_NVRAM_START, 93 .dm_nvram_size = DS3232_NVRAM_SIZE, 94 .dm_flags = DSRTC_FLAG_BCD, 95 }, 96 }; 97 98 struct dsrtc_softc { 99 device_t sc_dev; 100 i2c_tag_t sc_tag; 101 uint8_t sc_address; 102 bool sc_open; 103 struct dsrtc_model sc_model; 104 struct todr_chip_handle sc_todr; 105 }; 106 107 static void dsrtc_attach(device_t, device_t, void *); 108 static int dsrtc_match(device_t, cfdata_t, void *); 109 110 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 111 dsrtc_match, dsrtc_attach, NULL, NULL); 112 extern struct cfdriver dsrtc_cd; 113 114 dev_type_open(dsrtc_open); 115 dev_type_close(dsrtc_close); 116 dev_type_read(dsrtc_read); 117 dev_type_write(dsrtc_write); 118 119 const struct cdevsw dsrtc_cdevsw = { 120 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 121 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 122 }; 123 124 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 125 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 126 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 127 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 128 129 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 130 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 131 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 132 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 133 134 static const struct dsrtc_model * 135 dsrtc_model(u_int model) 136 { 137 /* no model given, assume it's a DS1307 (the first one) */ 138 if (model == 0) 139 return &dsrtc_models[0]; 140 141 for (const struct dsrtc_model *dm = dsrtc_models; 142 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 143 if (dm->dm_model == model) 144 return dm; 145 } 146 return NULL; 147 } 148 149 static int 150 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 151 { 152 struct i2c_attach_args *ia = arg; 153 154 if (ia->ia_name) { 155 /* direct config - check name */ 156 if (strcmp(ia->ia_name, "dsrtc") == 0) 157 return 1; 158 } else { 159 /* indirect config - check typical address */ 160 if (ia->ia_addr == DS1307_ADDR) 161 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 162 } 163 return 0; 164 } 165 166 static void 167 dsrtc_attach(device_t parent, device_t self, void *arg) 168 { 169 struct dsrtc_softc *sc = device_private(self); 170 struct i2c_attach_args *ia = arg; 171 const struct dsrtc_model * const dm = 172 dsrtc_model(device_cfdata(self)->cf_flags); 173 174 aprint_naive(": Real-time Clock%s\n", 175 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 176 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 177 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 178 179 sc->sc_tag = ia->ia_tag; 180 sc->sc_address = ia->ia_addr; 181 sc->sc_model = *dm; 182 sc->sc_dev = self; 183 sc->sc_open = 0; 184 sc->sc_todr.cookie = sc; 185 if (dm->dm_flags & DSRTC_FLAG_BCD) { 186 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 187 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 188 } else { 189 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 190 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 191 } 192 sc->sc_todr.todr_setwen = NULL; 193 194 todr_attach(&sc->sc_todr); 195 } 196 197 /*ARGSUSED*/ 198 int 199 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 200 { 201 struct dsrtc_softc *sc; 202 203 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 204 return ENXIO; 205 206 /* XXX: Locking */ 207 if (sc->sc_open) 208 return EBUSY; 209 210 sc->sc_open = true; 211 return 0; 212 } 213 214 /*ARGSUSED*/ 215 int 216 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 217 { 218 struct dsrtc_softc *sc; 219 220 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 221 return ENXIO; 222 223 sc->sc_open = false; 224 return 0; 225 } 226 227 /*ARGSUSED*/ 228 int 229 dsrtc_read(dev_t dev, struct uio *uio, int flags) 230 { 231 struct dsrtc_softc *sc; 232 int error; 233 234 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 235 return ENXIO; 236 237 const struct dsrtc_model * const dm = &sc->sc_model; 238 if (uio->uio_offset >= dm->dm_nvram_size) 239 return EINVAL; 240 241 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 242 return error; 243 244 KASSERT(uio->uio_offset >= 0); 245 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 246 uint8_t ch, cmd; 247 const u_int a = uio->uio_offset; 248 cmd = a + dm->dm_nvram_start; 249 if ((error = iic_exec(sc->sc_tag, 250 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 251 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 252 iic_release_bus(sc->sc_tag, 0); 253 aprint_error_dev(sc->sc_dev, 254 "%s: read failed at 0x%x: %d\n", 255 __func__, a, error); 256 return error; 257 } 258 if ((error = uiomove(&ch, 1, uio)) != 0) { 259 iic_release_bus(sc->sc_tag, 0); 260 return error; 261 } 262 } 263 264 iic_release_bus(sc->sc_tag, 0); 265 266 return 0; 267 } 268 269 /*ARGSUSED*/ 270 int 271 dsrtc_write(dev_t dev, struct uio *uio, int flags) 272 { 273 struct dsrtc_softc *sc; 274 int error; 275 276 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 277 return ENXIO; 278 279 const struct dsrtc_model * const dm = &sc->sc_model; 280 if (uio->uio_offset >= dm->dm_nvram_size) 281 return EINVAL; 282 283 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 284 return error; 285 286 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 287 uint8_t cmdbuf[2]; 288 const u_int a = (int)uio->uio_offset; 289 cmdbuf[0] = a + dm->dm_nvram_start; 290 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 291 break; 292 293 if ((error = iic_exec(sc->sc_tag, 294 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 295 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 296 aprint_error_dev(sc->sc_dev, 297 "%s: write failed at 0x%x: %d\n", 298 __func__, a, error); 299 break; 300 } 301 } 302 303 iic_release_bus(sc->sc_tag, 0); 304 305 return error; 306 } 307 308 static int 309 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 310 { 311 struct dsrtc_softc *sc = ch->cookie; 312 struct clock_ymdhms check; 313 int retries; 314 315 memset(dt, 0, sizeof(*dt)); 316 memset(&check, 0, sizeof(check)); 317 318 /* 319 * Since we don't support Burst Read, we have to read the clock twice 320 * until we get two consecutive identical results. 321 */ 322 retries = 5; 323 do { 324 dsrtc_clock_read_ymdhms(sc, dt); 325 dsrtc_clock_read_ymdhms(sc, &check); 326 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 327 328 return 0; 329 } 330 331 static int 332 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 333 { 334 struct dsrtc_softc *sc = ch->cookie; 335 336 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 337 return -1; 338 339 return 0; 340 } 341 342 static int 343 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 344 { 345 struct dsrtc_model * const dm = &sc->sc_model; 346 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 347 int error; 348 349 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 350 351 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 352 aprint_error_dev(sc->sc_dev, 353 "%s: failed to acquire I2C bus: %d\n", 354 __func__, error); 355 return 0; 356 } 357 358 /* Read each RTC register in order. */ 359 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 360 cmdbuf[0] = dm->dm_rtc_start + i; 361 362 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 363 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 364 } 365 366 /* Done with I2C */ 367 iic_release_bus(sc->sc_tag, I2C_F_POLL); 368 369 if (error != 0) { 370 aprint_error_dev(sc->sc_dev, 371 "%s: failed to read rtc at 0x%x: %d\n", 372 __func__, cmdbuf[0], error); 373 return 0; 374 } 375 376 /* 377 * Convert the RTC's register values into something useable 378 */ 379 dt->dt_sec = FROMBCD(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 380 dt->dt_min = FROMBCD(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 381 382 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 383 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 384 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 385 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 386 dt->dt_hour += 12; 387 } else 388 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 389 DSXXXX_HOURS_24MASK); 390 391 dt->dt_day = FROMBCD(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 392 dt->dt_mon = FROMBCD(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 393 394 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 395 dt->dt_year = FROMBCD(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 396 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 397 dt->dt_year += 100; 398 399 return 1; 400 } 401 402 static int 403 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 404 { 405 struct dsrtc_model * const dm = &sc->sc_model; 406 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 407 int error; 408 409 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 410 411 /* 412 * Convert our time representation into something the DSXXXX 413 * can understand. 414 */ 415 bcd[DSXXXX_SECONDS] = TOBCD(dt->dt_sec); 416 bcd[DSXXXX_MINUTES] = TOBCD(dt->dt_min); 417 bcd[DSXXXX_HOURS] = TOBCD(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 418 bcd[DSXXXX_DATE] = TOBCD(dt->dt_day); 419 bcd[DSXXXX_DAY] = TOBCD(dt->dt_wday); 420 bcd[DSXXXX_MONTH] = TOBCD(dt->dt_mon); 421 bcd[DSXXXX_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 422 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 423 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 424 425 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 426 aprint_error_dev(sc->sc_dev, 427 "%s: failed to acquire I2C bus: %d\n", 428 __func__, error); 429 return 0; 430 } 431 432 /* Stop the clock */ 433 cmdbuf[0] = dm->dm_ch_reg; 434 435 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 436 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 437 iic_release_bus(sc->sc_tag, I2C_F_POLL); 438 aprint_error_dev(sc->sc_dev, 439 "%s: failed to read Hold Clock: %d\n", 440 __func__, error); 441 return 0; 442 } 443 444 cmdbuf[1] |= dm->dm_ch_value; 445 446 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 447 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 448 iic_release_bus(sc->sc_tag, I2C_F_POLL); 449 aprint_error_dev(sc->sc_dev, 450 "%s: failed to write Hold Clock: %d\n", 451 __func__, error); 452 return 0; 453 } 454 455 /* 456 * Write registers in reverse order. The last write (to the Seconds 457 * register) will undo the Clock Hold, above. 458 */ 459 uint8_t op = I2C_OP_WRITE; 460 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 461 cmdbuf[0] = dm->dm_rtc_start + i; 462 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 463 op = I2C_OP_WRITE_WITH_STOP; 464 } 465 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 466 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 467 iic_release_bus(sc->sc_tag, I2C_F_POLL); 468 aprint_error_dev(sc->sc_dev, 469 "%s: failed to write rtc at 0x%x: %d\n", 470 __func__, i, error); 471 /* XXX: Clock Hold is likely still asserted! */ 472 return 0; 473 } 474 } 475 /* 476 * If the clock hold register isn't the same register as seconds, 477 * we need to reeanble the clock. 478 */ 479 if (op != I2C_OP_WRITE_WITH_STOP) { 480 cmdbuf[0] = dm->dm_ch_reg; 481 cmdbuf[1] &= ~dm->dm_ch_value; 482 483 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 484 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 485 I2C_F_POLL)) != 0) { 486 iic_release_bus(sc->sc_tag, I2C_F_POLL); 487 aprint_error_dev(sc->sc_dev, 488 "%s: failed to Hold Clock: %d\n", 489 __func__, error); 490 return 0; 491 } 492 } 493 494 iic_release_bus(sc->sc_tag, I2C_F_POLL); 495 496 return 1; 497 } 498 499 static int 500 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 501 { 502 struct dsrtc_softc *sc = ch->cookie; 503 struct timeval check; 504 int retries; 505 506 memset(tv, 0, sizeof(*tv)); 507 memset(&check, 0, sizeof(check)); 508 509 /* 510 * Since we don't support Burst Read, we have to read the clock twice 511 * until we get two consecutive identical results. 512 */ 513 retries = 5; 514 do { 515 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 516 dsrtc_clock_read_timeval(sc, &check.tv_sec); 517 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 518 519 return 0; 520 } 521 522 static int 523 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 524 { 525 struct dsrtc_softc *sc = ch->cookie; 526 527 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 528 return -1; 529 530 return 0; 531 } 532 533 /* 534 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 535 * it, since some I2C controllers don't support anything other than single-byte 536 * transfers. 537 */ 538 static int 539 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 540 { 541 const struct dsrtc_model * const dm = &sc->sc_model; 542 uint8_t buf[4]; 543 int error; 544 545 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 546 aprint_error_dev(sc->sc_dev, 547 "%s: failed to acquire I2C bus: %d\n", 548 __func__, error); 549 return 0; 550 } 551 552 /* read all registers: */ 553 uint8_t reg = dm->dm_rtc_start; 554 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 555 ®, 1, buf, 4, I2C_F_POLL); 556 557 /* Done with I2C */ 558 iic_release_bus(sc->sc_tag, I2C_F_POLL); 559 560 if (error != 0) { 561 aprint_error_dev(sc->sc_dev, 562 "%s: failed to read rtc at 0x%x: %d\n", 563 __func__, reg, error); 564 return 0; 565 } 566 567 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 568 *tp = v; 569 570 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 571 __func__, v); 572 573 return 1; 574 } 575 576 static int 577 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 578 { 579 const struct dsrtc_model * const dm = &sc->sc_model; 580 size_t buflen = dm->dm_rtc_size + 2; 581 uint8_t buf[buflen]; 582 int error; 583 584 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 585 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 586 587 buf[0] = dm->dm_rtc_start; 588 buf[1] = (t >> 0) & 0xff; 589 buf[2] = (t >> 8) & 0xff; 590 buf[3] = (t >> 16) & 0xff; 591 buf[4] = (t >> 24) & 0xff; 592 buf[5] = 0; 593 594 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "%s: failed to acquire I2C bus: %d\n", 597 __func__, error); 598 return 0; 599 } 600 601 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 602 &buf, buflen, NULL, 0, I2C_F_POLL); 603 604 /* Done with I2C */ 605 iic_release_bus(sc->sc_tag, I2C_F_POLL); 606 607 /* send data */ 608 if (error != 0) { 609 aprint_error_dev(sc->sc_dev, 610 "%s: failed to set time: %d\n", 611 __func__, error); 612 return 0; 613 } 614 615 return 1; 616 } 617
Indexes created Thu Oct 02 14:10:14 GMT 2025