ds1307.c revision 1.16.2.2
1 /* $NetBSD: ds1307.c,v 1.16.2.2 2017/12/03 11:37:02 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.16.2.2 2017/12/03 11:37:02 jdolecek Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 58 struct dsrtc_model { 59 uint16_t dm_model; 60 uint8_t dm_ch_reg; 61 uint8_t dm_ch_value; 62 uint8_t dm_vbaten_reg; 63 uint8_t dm_vbaten_value; 64 uint8_t dm_rtc_start; 65 uint8_t dm_rtc_size; 66 uint8_t dm_nvram_start; 67 uint8_t dm_nvram_size; 68 uint8_t dm_flags; 69 #define DSRTC_FLAG_CLOCK_HOLD 0x01 70 #define DSRTC_FLAG_BCD 0x02 71 #define DSRTC_FLAG_TEMP 0x04 72 #define DSRTC_FLAG_VBATEN 0x08 73 #define DSRTC_FLAG_YEAR_START_2K 0x10 74 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 75 }; 76 77 static const struct dsrtc_model dsrtc_models[] = { 78 { 79 .dm_model = 1307, 80 .dm_ch_reg = DSXXXX_SECONDS, 81 .dm_ch_value = DS1307_SECONDS_CH, 82 .dm_rtc_start = DS1307_RTC_START, 83 .dm_rtc_size = DS1307_RTC_SIZE, 84 .dm_nvram_start = DS1307_NVRAM_START, 85 .dm_nvram_size = DS1307_NVRAM_SIZE, 86 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 87 }, { 88 .dm_model = 1339, 89 .dm_rtc_start = DS1339_RTC_START, 90 .dm_rtc_size = DS1339_RTC_SIZE, 91 .dm_flags = DSRTC_FLAG_BCD, 92 }, { 93 .dm_model = 1340, 94 .dm_ch_reg = DSXXXX_SECONDS, 95 .dm_ch_value = DS1340_SECONDS_EOSC, 96 .dm_rtc_start = DS1340_RTC_START, 97 .dm_rtc_size = DS1340_RTC_SIZE, 98 .dm_flags = DSRTC_FLAG_BCD, 99 }, { 100 .dm_model = 1672, 101 .dm_rtc_start = DS1672_RTC_START, 102 .dm_rtc_size = DS1672_RTC_SIZE, 103 .dm_ch_reg = DS1672_CONTROL, 104 .dm_ch_value = DS1672_CONTROL_CH, 105 .dm_flags = 0, 106 }, { 107 .dm_model = 3231, 108 .dm_rtc_start = DS3232_RTC_START, 109 .dm_rtc_size = DS3232_RTC_SIZE, 110 /* 111 * XXX 112 * the DS3232 likely has the temperature sensor too but I can't 113 * easily verify or test that right now 114 */ 115 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 116 }, { 117 .dm_model = 3232, 118 .dm_rtc_start = DS3232_RTC_START, 119 .dm_rtc_size = DS3232_RTC_SIZE, 120 .dm_nvram_start = DS3232_NVRAM_START, 121 .dm_nvram_size = DS3232_NVRAM_SIZE, 122 .dm_flags = DSRTC_FLAG_BCD, 123 }, { 124 /* MCP7940 */ 125 .dm_model = 7940, 126 .dm_rtc_start = DS1307_RTC_START, 127 .dm_rtc_size = DS1307_RTC_SIZE, 128 .dm_ch_reg = DSXXXX_SECONDS, 129 .dm_ch_value = DS1307_SECONDS_CH, 130 .dm_vbaten_reg = DSXXXX_DAY, 131 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 132 .dm_nvram_start = MCP7940_NVRAM_START, 133 .dm_nvram_size = MCP7940_NVRAM_SIZE, 134 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 135 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 136 }, 137 }; 138 139 struct dsrtc_softc { 140 device_t sc_dev; 141 i2c_tag_t sc_tag; 142 uint8_t sc_address; 143 bool sc_open; 144 struct dsrtc_model sc_model; 145 struct todr_chip_handle sc_todr; 146 struct sysmon_envsys *sc_sme; 147 envsys_data_t sc_sensor; 148 }; 149 150 static void dsrtc_attach(device_t, device_t, void *); 151 static int dsrtc_match(device_t, cfdata_t, void *); 152 153 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 154 dsrtc_match, dsrtc_attach, NULL, NULL); 155 156 dev_type_open(dsrtc_open); 157 dev_type_close(dsrtc_close); 158 dev_type_read(dsrtc_read); 159 dev_type_write(dsrtc_write); 160 161 const struct cdevsw dsrtc_cdevsw = { 162 .d_open = dsrtc_open, 163 .d_close = dsrtc_close, 164 .d_read = dsrtc_read, 165 .d_write = dsrtc_write, 166 .d_ioctl = noioctl, 167 .d_stop = nostop, 168 .d_tty = notty, 169 .d_poll = nopoll, 170 .d_mmap = nommap, 171 .d_kqfilter = nokqfilter, 172 .d_discard = nodiscard, 173 .d_flag = D_OTHER 174 }; 175 176 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 177 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 178 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 179 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 180 181 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 182 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 183 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 184 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 185 186 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 187 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 188 189 static const struct dsrtc_model * 190 dsrtc_model(u_int model) 191 { 192 /* no model given, assume it's a DS1307 (the first one) */ 193 if (model == 0) 194 return &dsrtc_models[0]; 195 196 for (const struct dsrtc_model *dm = dsrtc_models; 197 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 198 if (dm->dm_model == model) 199 return dm; 200 } 201 return NULL; 202 } 203 204 static int 205 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 206 { 207 struct i2c_attach_args *ia = arg; 208 209 if (ia->ia_name) { 210 /* direct config - check name */ 211 if (strcmp(ia->ia_name, "dsrtc") == 0) 212 return 1; 213 } else { 214 /* indirect config - check typical address */ 215 if (ia->ia_addr == DS1307_ADDR || ia->ia_addr == MCP7940_ADDR) 216 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 217 } 218 return 0; 219 } 220 221 static void 222 dsrtc_attach(device_t parent, device_t self, void *arg) 223 { 224 struct dsrtc_softc *sc = device_private(self); 225 struct i2c_attach_args *ia = arg; 226 const struct dsrtc_model * const dm = 227 dsrtc_model(device_cfdata(self)->cf_flags); 228 229 aprint_naive(": Real-time Clock%s\n", 230 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 231 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 232 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 233 234 sc->sc_tag = ia->ia_tag; 235 sc->sc_address = ia->ia_addr; 236 sc->sc_model = *dm; 237 sc->sc_dev = self; 238 sc->sc_open = 0; 239 sc->sc_todr.cookie = sc; 240 if (dm->dm_flags & DSRTC_FLAG_BCD) { 241 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 242 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 243 } else { 244 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 245 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 246 } 247 sc->sc_todr.todr_setwen = NULL; 248 249 todr_attach(&sc->sc_todr); 250 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 251 int error; 252 253 sc->sc_sme = sysmon_envsys_create(); 254 sc->sc_sme->sme_name = device_xname(self); 255 sc->sc_sme->sme_cookie = sc; 256 sc->sc_sme->sme_refresh = dsrtc_refresh; 257 258 sc->sc_sensor.units = ENVSYS_STEMP; 259 sc->sc_sensor.state = ENVSYS_SINVALID; 260 sc->sc_sensor.flags = 0; 261 (void)strlcpy(sc->sc_sensor.desc, "temperature", 262 sizeof(sc->sc_sensor.desc)); 263 264 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 265 aprint_error_dev(self, "unable to attach sensor\n"); 266 goto bad; 267 } 268 269 error = sysmon_envsys_register(sc->sc_sme); 270 if (error) { 271 aprint_error_dev(self, 272 "error %d registering with sysmon\n", error); 273 goto bad; 274 } 275 } 276 return; 277 bad: 278 sysmon_envsys_destroy(sc->sc_sme); 279 } 280 281 /*ARGSUSED*/ 282 int 283 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 284 { 285 struct dsrtc_softc *sc; 286 287 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 288 return ENXIO; 289 290 /* XXX: Locking */ 291 if (sc->sc_open) 292 return EBUSY; 293 294 sc->sc_open = true; 295 return 0; 296 } 297 298 /*ARGSUSED*/ 299 int 300 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 301 { 302 struct dsrtc_softc *sc; 303 304 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 305 return ENXIO; 306 307 sc->sc_open = false; 308 return 0; 309 } 310 311 /*ARGSUSED*/ 312 int 313 dsrtc_read(dev_t dev, struct uio *uio, int flags) 314 { 315 struct dsrtc_softc *sc; 316 int error; 317 318 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 319 return ENXIO; 320 321 const struct dsrtc_model * const dm = &sc->sc_model; 322 if (uio->uio_offset >= dm->dm_nvram_size) 323 return EINVAL; 324 325 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 326 return error; 327 328 KASSERT(uio->uio_offset >= 0); 329 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 330 uint8_t ch, cmd; 331 const u_int a = uio->uio_offset; 332 cmd = a + dm->dm_nvram_start; 333 if ((error = iic_exec(sc->sc_tag, 334 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 335 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 336 iic_release_bus(sc->sc_tag, 0); 337 aprint_error_dev(sc->sc_dev, 338 "%s: read failed at 0x%x: %d\n", 339 __func__, a, error); 340 return error; 341 } 342 if ((error = uiomove(&ch, 1, uio)) != 0) { 343 iic_release_bus(sc->sc_tag, 0); 344 return error; 345 } 346 } 347 348 iic_release_bus(sc->sc_tag, 0); 349 350 return 0; 351 } 352 353 /*ARGSUSED*/ 354 int 355 dsrtc_write(dev_t dev, struct uio *uio, int flags) 356 { 357 struct dsrtc_softc *sc; 358 int error; 359 360 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 361 return ENXIO; 362 363 const struct dsrtc_model * const dm = &sc->sc_model; 364 if (uio->uio_offset >= dm->dm_nvram_size) 365 return EINVAL; 366 367 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 368 return error; 369 370 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 371 uint8_t cmdbuf[2]; 372 const u_int a = (int)uio->uio_offset; 373 cmdbuf[0] = a + dm->dm_nvram_start; 374 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 375 break; 376 377 if ((error = iic_exec(sc->sc_tag, 378 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 379 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 380 aprint_error_dev(sc->sc_dev, 381 "%s: write failed at 0x%x: %d\n", 382 __func__, a, error); 383 break; 384 } 385 } 386 387 iic_release_bus(sc->sc_tag, 0); 388 389 return error; 390 } 391 392 static int 393 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 394 { 395 struct dsrtc_softc *sc = ch->cookie; 396 struct clock_ymdhms check; 397 int retries; 398 399 memset(dt, 0, sizeof(*dt)); 400 memset(&check, 0, sizeof(check)); 401 402 /* 403 * Since we don't support Burst Read, we have to read the clock twice 404 * until we get two consecutive identical results. 405 */ 406 retries = 5; 407 do { 408 dsrtc_clock_read_ymdhms(sc, dt); 409 dsrtc_clock_read_ymdhms(sc, &check); 410 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 411 412 return 0; 413 } 414 415 static int 416 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 417 { 418 struct dsrtc_softc *sc = ch->cookie; 419 420 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 421 return -1; 422 423 return 0; 424 } 425 426 static int 427 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 428 { 429 struct dsrtc_model * const dm = &sc->sc_model; 430 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 431 int error; 432 433 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 434 435 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 436 aprint_error_dev(sc->sc_dev, 437 "%s: failed to acquire I2C bus: %d\n", 438 __func__, error); 439 return 0; 440 } 441 442 /* Read each RTC register in order. */ 443 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 444 cmdbuf[0] = dm->dm_rtc_start + i; 445 446 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 447 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 448 } 449 450 /* Done with I2C */ 451 iic_release_bus(sc->sc_tag, I2C_F_POLL); 452 453 if (error != 0) { 454 aprint_error_dev(sc->sc_dev, 455 "%s: failed to read rtc at 0x%x: %d\n", 456 __func__, cmdbuf[0], error); 457 return 0; 458 } 459 460 /* 461 * Convert the RTC's register values into something useable 462 */ 463 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 464 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 465 466 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 467 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 468 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 469 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 470 dt->dt_hour += 12; 471 } else 472 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 473 DSXXXX_HOURS_24MASK); 474 475 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 476 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 477 478 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 479 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 480 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 481 else { 482 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 483 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 484 dt->dt_year += 100; 485 } 486 487 return 1; 488 } 489 490 static int 491 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 492 { 493 struct dsrtc_model * const dm = &sc->sc_model; 494 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 495 int error; 496 497 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 498 499 /* 500 * Convert our time representation into something the DSXXXX 501 * can understand. 502 */ 503 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 504 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 505 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 506 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 507 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 508 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 509 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 510 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 511 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 512 513 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 514 aprint_error_dev(sc->sc_dev, 515 "%s: failed to acquire I2C bus: %d\n", 516 __func__, error); 517 return 0; 518 } 519 520 /* Stop the clock */ 521 cmdbuf[0] = dm->dm_ch_reg; 522 523 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 524 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 525 iic_release_bus(sc->sc_tag, I2C_F_POLL); 526 aprint_error_dev(sc->sc_dev, 527 "%s: failed to read Hold Clock: %d\n", 528 __func__, error); 529 return 0; 530 } 531 532 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 533 cmdbuf[1] &= ~dm->dm_ch_value; 534 else 535 cmdbuf[1] |= dm->dm_ch_value; 536 537 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 538 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 539 iic_release_bus(sc->sc_tag, I2C_F_POLL); 540 aprint_error_dev(sc->sc_dev, 541 "%s: failed to write Hold Clock: %d\n", 542 __func__, error); 543 return 0; 544 } 545 546 /* 547 * Write registers in reverse order. The last write (to the Seconds 548 * register) will undo the Clock Hold, above. 549 */ 550 uint8_t op = I2C_OP_WRITE; 551 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 552 cmdbuf[0] = dm->dm_rtc_start + i; 553 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 554 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 555 bcd[i] |= dm->dm_vbaten_value; 556 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 557 op = I2C_OP_WRITE_WITH_STOP; 558 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 559 bcd[i] |= dm->dm_ch_value; 560 } 561 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 562 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 563 iic_release_bus(sc->sc_tag, I2C_F_POLL); 564 aprint_error_dev(sc->sc_dev, 565 "%s: failed to write rtc at 0x%x: %d\n", 566 __func__, i, error); 567 /* XXX: Clock Hold is likely still asserted! */ 568 return 0; 569 } 570 } 571 /* 572 * If the clock hold register isn't the same register as seconds, 573 * we need to reeanble the clock. 574 */ 575 if (op != I2C_OP_WRITE_WITH_STOP) { 576 cmdbuf[0] = dm->dm_ch_reg; 577 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 578 cmdbuf[1] |= dm->dm_ch_value; 579 else 580 cmdbuf[1] &= ~dm->dm_ch_value; 581 582 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 583 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 584 I2C_F_POLL)) != 0) { 585 iic_release_bus(sc->sc_tag, I2C_F_POLL); 586 aprint_error_dev(sc->sc_dev, 587 "%s: failed to Hold Clock: %d\n", 588 __func__, error); 589 return 0; 590 } 591 } 592 593 iic_release_bus(sc->sc_tag, I2C_F_POLL); 594 595 return 1; 596 } 597 598 static int 599 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 600 { 601 struct dsrtc_softc *sc = ch->cookie; 602 struct timeval check; 603 int retries; 604 605 memset(tv, 0, sizeof(*tv)); 606 memset(&check, 0, sizeof(check)); 607 608 /* 609 * Since we don't support Burst Read, we have to read the clock twice 610 * until we get two consecutive identical results. 611 */ 612 retries = 5; 613 do { 614 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 615 dsrtc_clock_read_timeval(sc, &check.tv_sec); 616 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 617 618 return 0; 619 } 620 621 static int 622 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 623 { 624 struct dsrtc_softc *sc = ch->cookie; 625 626 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 627 return -1; 628 629 return 0; 630 } 631 632 /* 633 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 634 * it, since some I2C controllers don't support anything other than single-byte 635 * transfers. 636 */ 637 static int 638 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 639 { 640 const struct dsrtc_model * const dm = &sc->sc_model; 641 uint8_t buf[4]; 642 int error; 643 644 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 645 aprint_error_dev(sc->sc_dev, 646 "%s: failed to acquire I2C bus: %d\n", 647 __func__, error); 648 return 0; 649 } 650 651 /* read all registers: */ 652 uint8_t reg = dm->dm_rtc_start; 653 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 654 ®, 1, buf, 4, I2C_F_POLL); 655 656 /* Done with I2C */ 657 iic_release_bus(sc->sc_tag, I2C_F_POLL); 658 659 if (error != 0) { 660 aprint_error_dev(sc->sc_dev, 661 "%s: failed to read rtc at 0x%x: %d\n", 662 __func__, reg, error); 663 return 0; 664 } 665 666 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 667 *tp = v; 668 669 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 670 __func__, v); 671 672 return 1; 673 } 674 675 static int 676 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 677 { 678 const struct dsrtc_model * const dm = &sc->sc_model; 679 size_t buflen = dm->dm_rtc_size + 2; 680 uint8_t buf[buflen]; 681 int error; 682 683 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 684 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 685 686 buf[0] = dm->dm_rtc_start; 687 buf[1] = (t >> 0) & 0xff; 688 buf[2] = (t >> 8) & 0xff; 689 buf[3] = (t >> 16) & 0xff; 690 buf[4] = (t >> 24) & 0xff; 691 buf[5] = 0; 692 693 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 694 aprint_error_dev(sc->sc_dev, 695 "%s: failed to acquire I2C bus: %d\n", 696 __func__, error); 697 return 0; 698 } 699 700 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 701 &buf, buflen, NULL, 0, I2C_F_POLL); 702 703 /* Done with I2C */ 704 iic_release_bus(sc->sc_tag, I2C_F_POLL); 705 706 /* send data */ 707 if (error != 0) { 708 aprint_error_dev(sc->sc_dev, 709 "%s: failed to set time: %d\n", 710 __func__, error); 711 return 0; 712 } 713 714 return 1; 715 } 716 717 static int 718 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 719 { 720 int error, tc; 721 uint8_t reg = DS3232_TEMP_MSB; 722 uint8_t buf[2]; 723 724 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 725 return ENOTSUP; 726 727 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 728 aprint_error_dev(sc->sc_dev, 729 "%s: failed to acquire I2C bus: %d\n", 730 __func__, error); 731 return 0; 732 } 733 734 /* read temperature registers: */ 735 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 736 ®, 1, buf, 2, I2C_F_POLL); 737 738 /* Done with I2C */ 739 iic_release_bus(sc->sc_tag, I2C_F_POLL); 740 741 if (error != 0) { 742 aprint_error_dev(sc->sc_dev, 743 "%s: failed to read temperature: %d\n", 744 __func__, error); 745 return 0; 746 } 747 748 /* convert to microkelvin */ 749 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 750 *temp = tc + 273150000; 751 return 1; 752 } 753 754 static void 755 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 756 { 757 struct dsrtc_softc *sc = sme->sme_cookie; 758 uint32_t temp = 0; /* XXX gcc */ 759 760 if (dsrtc_read_temp(sc, &temp) == 0) { 761 edata->state = ENVSYS_SINVALID; 762 return; 763 } 764 765 edata->value_cur = temp; 766 767 edata->state = ENVSYS_SVALID; 768 } 769
Indexes created Thu Oct 02 14:10:14 GMT 2025