ds1307.c revision 1.16.4.1
1 /* $NetBSD: ds1307.c,v 1.16.4.1 2014/05/18 17:45:37 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.16.4.1 2014/05/18 17:45:37 rmind Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_model { 56 uint16_t dm_model; 57 uint8_t dm_ch_reg; 58 uint8_t dm_ch_value; 59 uint8_t dm_rtc_start; 60 uint8_t dm_rtc_size; 61 uint8_t dm_nvram_start; 62 uint8_t dm_nvram_size; 63 uint8_t dm_flags; 64 #define DSRTC_FLAG_CLOCK_HOLD 1 65 #define DSRTC_FLAG_BCD 2 66 }; 67 68 static const struct dsrtc_model dsrtc_models[] = { 69 { 70 .dm_model = 1307, 71 .dm_ch_reg = DSXXXX_SECONDS, 72 .dm_ch_value = DS1307_SECONDS_CH, 73 .dm_rtc_start = DS1307_RTC_START, 74 .dm_rtc_size = DS1307_RTC_SIZE, 75 .dm_nvram_start = DS1307_NVRAM_START, 76 .dm_nvram_size = DS1307_NVRAM_SIZE, 77 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 78 }, { 79 .dm_model = 1339, 80 .dm_rtc_start = DS1339_RTC_START, 81 .dm_rtc_size = DS1339_RTC_SIZE, 82 .dm_flags = DSRTC_FLAG_BCD, 83 }, { 84 .dm_model = 1672, 85 .dm_rtc_start = DS1672_RTC_START, 86 .dm_rtc_size = DS1672_RTC_SIZE, 87 .dm_flags = 0, 88 }, { 89 .dm_model = 3232, 90 .dm_rtc_start = DS3232_RTC_START, 91 .dm_rtc_size = DS3232_RTC_SIZE, 92 .dm_nvram_start = DS3232_NVRAM_START, 93 .dm_nvram_size = DS3232_NVRAM_SIZE, 94 .dm_flags = DSRTC_FLAG_BCD, 95 }, 96 }; 97 98 struct dsrtc_softc { 99 device_t sc_dev; 100 i2c_tag_t sc_tag; 101 uint8_t sc_address; 102 bool sc_open; 103 struct dsrtc_model sc_model; 104 struct todr_chip_handle sc_todr; 105 }; 106 107 static void dsrtc_attach(device_t, device_t, void *); 108 static int dsrtc_match(device_t, cfdata_t, void *); 109 110 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 111 dsrtc_match, dsrtc_attach, NULL, NULL); 112 extern struct cfdriver dsrtc_cd; 113 114 dev_type_open(dsrtc_open); 115 dev_type_close(dsrtc_close); 116 dev_type_read(dsrtc_read); 117 dev_type_write(dsrtc_write); 118 119 const struct cdevsw dsrtc_cdevsw = { 120 .d_open = dsrtc_open, 121 .d_close = dsrtc_close, 122 .d_read = dsrtc_read, 123 .d_write = dsrtc_write, 124 .d_ioctl = noioctl, 125 .d_stop = nostop, 126 .d_tty = notty, 127 .d_poll = nopoll, 128 .d_mmap = nommap, 129 .d_kqfilter = nokqfilter, 130 .d_flag = D_OTHER 131 }; 132 133 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 134 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 135 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 136 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 137 138 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 139 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 140 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 141 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 142 143 static const struct dsrtc_model * 144 dsrtc_model(u_int model) 145 { 146 /* no model given, assume it's a DS1307 (the first one) */ 147 if (model == 0) 148 return &dsrtc_models[0]; 149 150 for (const struct dsrtc_model *dm = dsrtc_models; 151 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 152 if (dm->dm_model == model) 153 return dm; 154 } 155 return NULL; 156 } 157 158 static int 159 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 160 { 161 struct i2c_attach_args *ia = arg; 162 163 if (ia->ia_name) { 164 /* direct config - check name */ 165 if (strcmp(ia->ia_name, "dsrtc") == 0) 166 return 1; 167 } else { 168 /* indirect config - check typical address */ 169 if (ia->ia_addr == DS1307_ADDR) 170 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 171 } 172 return 0; 173 } 174 175 static void 176 dsrtc_attach(device_t parent, device_t self, void *arg) 177 { 178 struct dsrtc_softc *sc = device_private(self); 179 struct i2c_attach_args *ia = arg; 180 const struct dsrtc_model * const dm = 181 dsrtc_model(device_cfdata(self)->cf_flags); 182 183 aprint_naive(": Real-time Clock%s\n", 184 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 185 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 186 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 187 188 sc->sc_tag = ia->ia_tag; 189 sc->sc_address = ia->ia_addr; 190 sc->sc_model = *dm; 191 sc->sc_dev = self; 192 sc->sc_open = 0; 193 sc->sc_todr.cookie = sc; 194 if (dm->dm_flags & DSRTC_FLAG_BCD) { 195 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 196 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 197 } else { 198 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 199 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 200 } 201 sc->sc_todr.todr_setwen = NULL; 202 203 todr_attach(&sc->sc_todr); 204 } 205 206 /*ARGSUSED*/ 207 int 208 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 209 { 210 struct dsrtc_softc *sc; 211 212 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 213 return ENXIO; 214 215 /* XXX: Locking */ 216 if (sc->sc_open) 217 return EBUSY; 218 219 sc->sc_open = true; 220 return 0; 221 } 222 223 /*ARGSUSED*/ 224 int 225 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 226 { 227 struct dsrtc_softc *sc; 228 229 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 230 return ENXIO; 231 232 sc->sc_open = false; 233 return 0; 234 } 235 236 /*ARGSUSED*/ 237 int 238 dsrtc_read(dev_t dev, struct uio *uio, int flags) 239 { 240 struct dsrtc_softc *sc; 241 int error; 242 243 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 244 return ENXIO; 245 246 const struct dsrtc_model * const dm = &sc->sc_model; 247 if (uio->uio_offset >= dm->dm_nvram_size) 248 return EINVAL; 249 250 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 251 return error; 252 253 KASSERT(uio->uio_offset >= 0); 254 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 255 uint8_t ch, cmd; 256 const u_int a = uio->uio_offset; 257 cmd = a + dm->dm_nvram_start; 258 if ((error = iic_exec(sc->sc_tag, 259 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 260 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 261 iic_release_bus(sc->sc_tag, 0); 262 aprint_error_dev(sc->sc_dev, 263 "%s: read failed at 0x%x: %d\n", 264 __func__, a, error); 265 return error; 266 } 267 if ((error = uiomove(&ch, 1, uio)) != 0) { 268 iic_release_bus(sc->sc_tag, 0); 269 return error; 270 } 271 } 272 273 iic_release_bus(sc->sc_tag, 0); 274 275 return 0; 276 } 277 278 /*ARGSUSED*/ 279 int 280 dsrtc_write(dev_t dev, struct uio *uio, int flags) 281 { 282 struct dsrtc_softc *sc; 283 int error; 284 285 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 286 return ENXIO; 287 288 const struct dsrtc_model * const dm = &sc->sc_model; 289 if (uio->uio_offset >= dm->dm_nvram_size) 290 return EINVAL; 291 292 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 293 return error; 294 295 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 296 uint8_t cmdbuf[2]; 297 const u_int a = (int)uio->uio_offset; 298 cmdbuf[0] = a + dm->dm_nvram_start; 299 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 300 break; 301 302 if ((error = iic_exec(sc->sc_tag, 303 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 304 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 305 aprint_error_dev(sc->sc_dev, 306 "%s: write failed at 0x%x: %d\n", 307 __func__, a, error); 308 break; 309 } 310 } 311 312 iic_release_bus(sc->sc_tag, 0); 313 314 return error; 315 } 316 317 static int 318 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 319 { 320 struct dsrtc_softc *sc = ch->cookie; 321 struct clock_ymdhms check; 322 int retries; 323 324 memset(dt, 0, sizeof(*dt)); 325 memset(&check, 0, sizeof(check)); 326 327 /* 328 * Since we don't support Burst Read, we have to read the clock twice 329 * until we get two consecutive identical results. 330 */ 331 retries = 5; 332 do { 333 dsrtc_clock_read_ymdhms(sc, dt); 334 dsrtc_clock_read_ymdhms(sc, &check); 335 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 336 337 return 0; 338 } 339 340 static int 341 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 342 { 343 struct dsrtc_softc *sc = ch->cookie; 344 345 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 346 return -1; 347 348 return 0; 349 } 350 351 static int 352 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 353 { 354 struct dsrtc_model * const dm = &sc->sc_model; 355 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 356 int error; 357 358 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 359 360 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "%s: failed to acquire I2C bus: %d\n", 363 __func__, error); 364 return 0; 365 } 366 367 /* Read each RTC register in order. */ 368 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 369 cmdbuf[0] = dm->dm_rtc_start + i; 370 371 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 372 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 373 } 374 375 /* Done with I2C */ 376 iic_release_bus(sc->sc_tag, I2C_F_POLL); 377 378 if (error != 0) { 379 aprint_error_dev(sc->sc_dev, 380 "%s: failed to read rtc at 0x%x: %d\n", 381 __func__, cmdbuf[0], error); 382 return 0; 383 } 384 385 /* 386 * Convert the RTC's register values into something useable 387 */ 388 dt->dt_sec = FROMBCD(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 389 dt->dt_min = FROMBCD(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 390 391 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 392 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 393 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 394 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 395 dt->dt_hour += 12; 396 } else 397 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 398 DSXXXX_HOURS_24MASK); 399 400 dt->dt_day = FROMBCD(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 401 dt->dt_mon = FROMBCD(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 402 403 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 404 dt->dt_year = FROMBCD(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 405 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 406 dt->dt_year += 100; 407 408 return 1; 409 } 410 411 static int 412 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 413 { 414 struct dsrtc_model * const dm = &sc->sc_model; 415 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 416 int error; 417 418 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 419 420 /* 421 * Convert our time representation into something the DSXXXX 422 * can understand. 423 */ 424 bcd[DSXXXX_SECONDS] = TOBCD(dt->dt_sec); 425 bcd[DSXXXX_MINUTES] = TOBCD(dt->dt_min); 426 bcd[DSXXXX_HOURS] = TOBCD(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 427 bcd[DSXXXX_DATE] = TOBCD(dt->dt_day); 428 bcd[DSXXXX_DAY] = TOBCD(dt->dt_wday); 429 bcd[DSXXXX_MONTH] = TOBCD(dt->dt_mon); 430 bcd[DSXXXX_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 431 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 432 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 433 434 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 435 aprint_error_dev(sc->sc_dev, 436 "%s: failed to acquire I2C bus: %d\n", 437 __func__, error); 438 return 0; 439 } 440 441 /* Stop the clock */ 442 cmdbuf[0] = dm->dm_ch_reg; 443 444 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 445 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 446 iic_release_bus(sc->sc_tag, I2C_F_POLL); 447 aprint_error_dev(sc->sc_dev, 448 "%s: failed to read Hold Clock: %d\n", 449 __func__, error); 450 return 0; 451 } 452 453 cmdbuf[1] |= dm->dm_ch_value; 454 455 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 456 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 457 iic_release_bus(sc->sc_tag, I2C_F_POLL); 458 aprint_error_dev(sc->sc_dev, 459 "%s: failed to write Hold Clock: %d\n", 460 __func__, error); 461 return 0; 462 } 463 464 /* 465 * Write registers in reverse order. The last write (to the Seconds 466 * register) will undo the Clock Hold, above. 467 */ 468 uint8_t op = I2C_OP_WRITE; 469 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 470 cmdbuf[0] = dm->dm_rtc_start + i; 471 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 472 op = I2C_OP_WRITE_WITH_STOP; 473 } 474 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 475 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 476 iic_release_bus(sc->sc_tag, I2C_F_POLL); 477 aprint_error_dev(sc->sc_dev, 478 "%s: failed to write rtc at 0x%x: %d\n", 479 __func__, i, error); 480 /* XXX: Clock Hold is likely still asserted! */ 481 return 0; 482 } 483 } 484 /* 485 * If the clock hold register isn't the same register as seconds, 486 * we need to reeanble the clock. 487 */ 488 if (op != I2C_OP_WRITE_WITH_STOP) { 489 cmdbuf[0] = dm->dm_ch_reg; 490 cmdbuf[1] &= ~dm->dm_ch_value; 491 492 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 493 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 494 I2C_F_POLL)) != 0) { 495 iic_release_bus(sc->sc_tag, I2C_F_POLL); 496 aprint_error_dev(sc->sc_dev, 497 "%s: failed to Hold Clock: %d\n", 498 __func__, error); 499 return 0; 500 } 501 } 502 503 iic_release_bus(sc->sc_tag, I2C_F_POLL); 504 505 return 1; 506 } 507 508 static int 509 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 510 { 511 struct dsrtc_softc *sc = ch->cookie; 512 struct timeval check; 513 int retries; 514 515 memset(tv, 0, sizeof(*tv)); 516 memset(&check, 0, sizeof(check)); 517 518 /* 519 * Since we don't support Burst Read, we have to read the clock twice 520 * until we get two consecutive identical results. 521 */ 522 retries = 5; 523 do { 524 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 525 dsrtc_clock_read_timeval(sc, &check.tv_sec); 526 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 527 528 return 0; 529 } 530 531 static int 532 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 533 { 534 struct dsrtc_softc *sc = ch->cookie; 535 536 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 537 return -1; 538 539 return 0; 540 } 541 542 /* 543 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 544 * it, since some I2C controllers don't support anything other than single-byte 545 * transfers. 546 */ 547 static int 548 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 549 { 550 const struct dsrtc_model * const dm = &sc->sc_model; 551 uint8_t buf[4]; 552 int error; 553 554 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 555 aprint_error_dev(sc->sc_dev, 556 "%s: failed to acquire I2C bus: %d\n", 557 __func__, error); 558 return 0; 559 } 560 561 /* read all registers: */ 562 uint8_t reg = dm->dm_rtc_start; 563 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 564 ®, 1, buf, 4, I2C_F_POLL); 565 566 /* Done with I2C */ 567 iic_release_bus(sc->sc_tag, I2C_F_POLL); 568 569 if (error != 0) { 570 aprint_error_dev(sc->sc_dev, 571 "%s: failed to read rtc at 0x%x: %d\n", 572 __func__, reg, error); 573 return 0; 574 } 575 576 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 577 *tp = v; 578 579 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 580 __func__, v); 581 582 return 1; 583 } 584 585 static int 586 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 587 { 588 const struct dsrtc_model * const dm = &sc->sc_model; 589 size_t buflen = dm->dm_rtc_size + 2; 590 uint8_t buf[buflen]; 591 int error; 592 593 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 594 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 595 596 buf[0] = dm->dm_rtc_start; 597 buf[1] = (t >> 0) & 0xff; 598 buf[2] = (t >> 8) & 0xff; 599 buf[3] = (t >> 16) & 0xff; 600 buf[4] = (t >> 24) & 0xff; 601 buf[5] = 0; 602 603 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 604 aprint_error_dev(sc->sc_dev, 605 "%s: failed to acquire I2C bus: %d\n", 606 __func__, error); 607 return 0; 608 } 609 610 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 611 &buf, buflen, NULL, 0, I2C_F_POLL); 612 613 /* Done with I2C */ 614 iic_release_bus(sc->sc_tag, I2C_F_POLL); 615 616 /* send data */ 617 if (error != 0) { 618 aprint_error_dev(sc->sc_dev, 619 "%s: failed to set time: %d\n", 620 __func__, error); 621 return 0; 622 } 623 624 return 1; 625 } 626
Indexes created Thu Oct 02 10:09:58 GMT 2025