ds1307.c revision 1.17.2.1
1 /* $NetBSD: ds1307.c,v 1.17.2.1 2014/08/10 06:54:51 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.17.2.1 2014/08/10 06:54:51 tls Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_model { 56 uint16_t dm_model; 57 uint8_t dm_ch_reg; 58 uint8_t dm_ch_value; 59 uint8_t dm_rtc_start; 60 uint8_t dm_rtc_size; 61 uint8_t dm_nvram_start; 62 uint8_t dm_nvram_size; 63 uint8_t dm_flags; 64 #define DSRTC_FLAG_CLOCK_HOLD 1 65 #define DSRTC_FLAG_BCD 2 66 }; 67 68 static const struct dsrtc_model dsrtc_models[] = { 69 { 70 .dm_model = 1307, 71 .dm_ch_reg = DSXXXX_SECONDS, 72 .dm_ch_value = DS1307_SECONDS_CH, 73 .dm_rtc_start = DS1307_RTC_START, 74 .dm_rtc_size = DS1307_RTC_SIZE, 75 .dm_nvram_start = DS1307_NVRAM_START, 76 .dm_nvram_size = DS1307_NVRAM_SIZE, 77 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 78 }, { 79 .dm_model = 1339, 80 .dm_rtc_start = DS1339_RTC_START, 81 .dm_rtc_size = DS1339_RTC_SIZE, 82 .dm_flags = DSRTC_FLAG_BCD, 83 }, { 84 .dm_model = 1672, 85 .dm_rtc_start = DS1672_RTC_START, 86 .dm_rtc_size = DS1672_RTC_SIZE, 87 .dm_flags = 0, 88 }, { 89 .dm_model = 3232, 90 .dm_rtc_start = DS3232_RTC_START, 91 .dm_rtc_size = DS3232_RTC_SIZE, 92 .dm_nvram_start = DS3232_NVRAM_START, 93 .dm_nvram_size = DS3232_NVRAM_SIZE, 94 .dm_flags = DSRTC_FLAG_BCD, 95 }, 96 }; 97 98 struct dsrtc_softc { 99 device_t sc_dev; 100 i2c_tag_t sc_tag; 101 uint8_t sc_address; 102 bool sc_open; 103 struct dsrtc_model sc_model; 104 struct todr_chip_handle sc_todr; 105 }; 106 107 static void dsrtc_attach(device_t, device_t, void *); 108 static int dsrtc_match(device_t, cfdata_t, void *); 109 110 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 111 dsrtc_match, dsrtc_attach, NULL, NULL); 112 extern struct cfdriver dsrtc_cd; 113 114 dev_type_open(dsrtc_open); 115 dev_type_close(dsrtc_close); 116 dev_type_read(dsrtc_read); 117 dev_type_write(dsrtc_write); 118 119 const struct cdevsw dsrtc_cdevsw = { 120 .d_open = dsrtc_open, 121 .d_close = dsrtc_close, 122 .d_read = dsrtc_read, 123 .d_write = dsrtc_write, 124 .d_ioctl = noioctl, 125 .d_stop = nostop, 126 .d_tty = notty, 127 .d_poll = nopoll, 128 .d_mmap = nommap, 129 .d_kqfilter = nokqfilter, 130 .d_discard = nodiscard, 131 .d_flag = D_OTHER 132 }; 133 134 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 135 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 136 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 137 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 138 139 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 140 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 141 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 142 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 143 144 static const struct dsrtc_model * 145 dsrtc_model(u_int model) 146 { 147 /* no model given, assume it's a DS1307 (the first one) */ 148 if (model == 0) 149 return &dsrtc_models[0]; 150 151 for (const struct dsrtc_model *dm = dsrtc_models; 152 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 153 if (dm->dm_model == model) 154 return dm; 155 } 156 return NULL; 157 } 158 159 static int 160 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 161 { 162 struct i2c_attach_args *ia = arg; 163 164 if (ia->ia_name) { 165 /* direct config - check name */ 166 if (strcmp(ia->ia_name, "dsrtc") == 0) 167 return 1; 168 } else { 169 /* indirect config - check typical address */ 170 if (ia->ia_addr == DS1307_ADDR) 171 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 172 } 173 return 0; 174 } 175 176 static void 177 dsrtc_attach(device_t parent, device_t self, void *arg) 178 { 179 struct dsrtc_softc *sc = device_private(self); 180 struct i2c_attach_args *ia = arg; 181 const struct dsrtc_model * const dm = 182 dsrtc_model(device_cfdata(self)->cf_flags); 183 184 aprint_naive(": Real-time Clock%s\n", 185 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 186 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 187 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 188 189 sc->sc_tag = ia->ia_tag; 190 sc->sc_address = ia->ia_addr; 191 sc->sc_model = *dm; 192 sc->sc_dev = self; 193 sc->sc_open = 0; 194 sc->sc_todr.cookie = sc; 195 if (dm->dm_flags & DSRTC_FLAG_BCD) { 196 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 197 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 198 } else { 199 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 200 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 201 } 202 sc->sc_todr.todr_setwen = NULL; 203 204 todr_attach(&sc->sc_todr); 205 } 206 207 /*ARGSUSED*/ 208 int 209 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 210 { 211 struct dsrtc_softc *sc; 212 213 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 214 return ENXIO; 215 216 /* XXX: Locking */ 217 if (sc->sc_open) 218 return EBUSY; 219 220 sc->sc_open = true; 221 return 0; 222 } 223 224 /*ARGSUSED*/ 225 int 226 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 227 { 228 struct dsrtc_softc *sc; 229 230 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 231 return ENXIO; 232 233 sc->sc_open = false; 234 return 0; 235 } 236 237 /*ARGSUSED*/ 238 int 239 dsrtc_read(dev_t dev, struct uio *uio, int flags) 240 { 241 struct dsrtc_softc *sc; 242 int error; 243 244 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 245 return ENXIO; 246 247 const struct dsrtc_model * const dm = &sc->sc_model; 248 if (uio->uio_offset >= dm->dm_nvram_size) 249 return EINVAL; 250 251 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 252 return error; 253 254 KASSERT(uio->uio_offset >= 0); 255 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 256 uint8_t ch, cmd; 257 const u_int a = uio->uio_offset; 258 cmd = a + dm->dm_nvram_start; 259 if ((error = iic_exec(sc->sc_tag, 260 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 261 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 262 iic_release_bus(sc->sc_tag, 0); 263 aprint_error_dev(sc->sc_dev, 264 "%s: read failed at 0x%x: %d\n", 265 __func__, a, error); 266 return error; 267 } 268 if ((error = uiomove(&ch, 1, uio)) != 0) { 269 iic_release_bus(sc->sc_tag, 0); 270 return error; 271 } 272 } 273 274 iic_release_bus(sc->sc_tag, 0); 275 276 return 0; 277 } 278 279 /*ARGSUSED*/ 280 int 281 dsrtc_write(dev_t dev, struct uio *uio, int flags) 282 { 283 struct dsrtc_softc *sc; 284 int error; 285 286 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 287 return ENXIO; 288 289 const struct dsrtc_model * const dm = &sc->sc_model; 290 if (uio->uio_offset >= dm->dm_nvram_size) 291 return EINVAL; 292 293 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 294 return error; 295 296 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 297 uint8_t cmdbuf[2]; 298 const u_int a = (int)uio->uio_offset; 299 cmdbuf[0] = a + dm->dm_nvram_start; 300 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 301 break; 302 303 if ((error = iic_exec(sc->sc_tag, 304 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 305 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 306 aprint_error_dev(sc->sc_dev, 307 "%s: write failed at 0x%x: %d\n", 308 __func__, a, error); 309 break; 310 } 311 } 312 313 iic_release_bus(sc->sc_tag, 0); 314 315 return error; 316 } 317 318 static int 319 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 320 { 321 struct dsrtc_softc *sc = ch->cookie; 322 struct clock_ymdhms check; 323 int retries; 324 325 memset(dt, 0, sizeof(*dt)); 326 memset(&check, 0, sizeof(check)); 327 328 /* 329 * Since we don't support Burst Read, we have to read the clock twice 330 * until we get two consecutive identical results. 331 */ 332 retries = 5; 333 do { 334 dsrtc_clock_read_ymdhms(sc, dt); 335 dsrtc_clock_read_ymdhms(sc, &check); 336 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 337 338 return 0; 339 } 340 341 static int 342 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 343 { 344 struct dsrtc_softc *sc = ch->cookie; 345 346 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 347 return -1; 348 349 return 0; 350 } 351 352 static int 353 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 354 { 355 struct dsrtc_model * const dm = &sc->sc_model; 356 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 357 int error; 358 359 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 360 361 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 362 aprint_error_dev(sc->sc_dev, 363 "%s: failed to acquire I2C bus: %d\n", 364 __func__, error); 365 return 0; 366 } 367 368 /* Read each RTC register in order. */ 369 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 370 cmdbuf[0] = dm->dm_rtc_start + i; 371 372 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 373 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 374 } 375 376 /* Done with I2C */ 377 iic_release_bus(sc->sc_tag, I2C_F_POLL); 378 379 if (error != 0) { 380 aprint_error_dev(sc->sc_dev, 381 "%s: failed to read rtc at 0x%x: %d\n", 382 __func__, cmdbuf[0], error); 383 return 0; 384 } 385 386 /* 387 * Convert the RTC's register values into something useable 388 */ 389 dt->dt_sec = FROMBCD(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 390 dt->dt_min = FROMBCD(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 391 392 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 393 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 394 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 395 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 396 dt->dt_hour += 12; 397 } else 398 dt->dt_hour = FROMBCD(bcd[DSXXXX_HOURS] & 399 DSXXXX_HOURS_24MASK); 400 401 dt->dt_day = FROMBCD(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 402 dt->dt_mon = FROMBCD(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 403 404 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 405 dt->dt_year = FROMBCD(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 406 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 407 dt->dt_year += 100; 408 409 return 1; 410 } 411 412 static int 413 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 414 { 415 struct dsrtc_model * const dm = &sc->sc_model; 416 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 417 int error; 418 419 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 420 421 /* 422 * Convert our time representation into something the DSXXXX 423 * can understand. 424 */ 425 bcd[DSXXXX_SECONDS] = TOBCD(dt->dt_sec); 426 bcd[DSXXXX_MINUTES] = TOBCD(dt->dt_min); 427 bcd[DSXXXX_HOURS] = TOBCD(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 428 bcd[DSXXXX_DATE] = TOBCD(dt->dt_day); 429 bcd[DSXXXX_DAY] = TOBCD(dt->dt_wday); 430 bcd[DSXXXX_MONTH] = TOBCD(dt->dt_mon); 431 bcd[DSXXXX_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 432 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 433 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 434 435 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 436 aprint_error_dev(sc->sc_dev, 437 "%s: failed to acquire I2C bus: %d\n", 438 __func__, error); 439 return 0; 440 } 441 442 /* Stop the clock */ 443 cmdbuf[0] = dm->dm_ch_reg; 444 445 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 446 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 447 iic_release_bus(sc->sc_tag, I2C_F_POLL); 448 aprint_error_dev(sc->sc_dev, 449 "%s: failed to read Hold Clock: %d\n", 450 __func__, error); 451 return 0; 452 } 453 454 cmdbuf[1] |= dm->dm_ch_value; 455 456 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 457 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 458 iic_release_bus(sc->sc_tag, I2C_F_POLL); 459 aprint_error_dev(sc->sc_dev, 460 "%s: failed to write Hold Clock: %d\n", 461 __func__, error); 462 return 0; 463 } 464 465 /* 466 * Write registers in reverse order. The last write (to the Seconds 467 * register) will undo the Clock Hold, above. 468 */ 469 uint8_t op = I2C_OP_WRITE; 470 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 471 cmdbuf[0] = dm->dm_rtc_start + i; 472 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 473 op = I2C_OP_WRITE_WITH_STOP; 474 } 475 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 476 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 477 iic_release_bus(sc->sc_tag, I2C_F_POLL); 478 aprint_error_dev(sc->sc_dev, 479 "%s: failed to write rtc at 0x%x: %d\n", 480 __func__, i, error); 481 /* XXX: Clock Hold is likely still asserted! */ 482 return 0; 483 } 484 } 485 /* 486 * If the clock hold register isn't the same register as seconds, 487 * we need to reeanble the clock. 488 */ 489 if (op != I2C_OP_WRITE_WITH_STOP) { 490 cmdbuf[0] = dm->dm_ch_reg; 491 cmdbuf[1] &= ~dm->dm_ch_value; 492 493 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 494 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 495 I2C_F_POLL)) != 0) { 496 iic_release_bus(sc->sc_tag, I2C_F_POLL); 497 aprint_error_dev(sc->sc_dev, 498 "%s: failed to Hold Clock: %d\n", 499 __func__, error); 500 return 0; 501 } 502 } 503 504 iic_release_bus(sc->sc_tag, I2C_F_POLL); 505 506 return 1; 507 } 508 509 static int 510 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 511 { 512 struct dsrtc_softc *sc = ch->cookie; 513 struct timeval check; 514 int retries; 515 516 memset(tv, 0, sizeof(*tv)); 517 memset(&check, 0, sizeof(check)); 518 519 /* 520 * Since we don't support Burst Read, we have to read the clock twice 521 * until we get two consecutive identical results. 522 */ 523 retries = 5; 524 do { 525 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 526 dsrtc_clock_read_timeval(sc, &check.tv_sec); 527 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 528 529 return 0; 530 } 531 532 static int 533 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 534 { 535 struct dsrtc_softc *sc = ch->cookie; 536 537 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 538 return -1; 539 540 return 0; 541 } 542 543 /* 544 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 545 * it, since some I2C controllers don't support anything other than single-byte 546 * transfers. 547 */ 548 static int 549 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 550 { 551 const struct dsrtc_model * const dm = &sc->sc_model; 552 uint8_t buf[4]; 553 int error; 554 555 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 556 aprint_error_dev(sc->sc_dev, 557 "%s: failed to acquire I2C bus: %d\n", 558 __func__, error); 559 return 0; 560 } 561 562 /* read all registers: */ 563 uint8_t reg = dm->dm_rtc_start; 564 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 565 ®, 1, buf, 4, I2C_F_POLL); 566 567 /* Done with I2C */ 568 iic_release_bus(sc->sc_tag, I2C_F_POLL); 569 570 if (error != 0) { 571 aprint_error_dev(sc->sc_dev, 572 "%s: failed to read rtc at 0x%x: %d\n", 573 __func__, reg, error); 574 return 0; 575 } 576 577 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 578 *tp = v; 579 580 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 581 __func__, v); 582 583 return 1; 584 } 585 586 static int 587 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 588 { 589 const struct dsrtc_model * const dm = &sc->sc_model; 590 size_t buflen = dm->dm_rtc_size + 2; 591 uint8_t buf[buflen]; 592 int error; 593 594 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 595 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 596 597 buf[0] = dm->dm_rtc_start; 598 buf[1] = (t >> 0) & 0xff; 599 buf[2] = (t >> 8) & 0xff; 600 buf[3] = (t >> 16) & 0xff; 601 buf[4] = (t >> 24) & 0xff; 602 buf[5] = 0; 603 604 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 605 aprint_error_dev(sc->sc_dev, 606 "%s: failed to acquire I2C bus: %d\n", 607 __func__, error); 608 return 0; 609 } 610 611 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 612 &buf, buflen, NULL, 0, I2C_F_POLL); 613 614 /* Done with I2C */ 615 iic_release_bus(sc->sc_tag, I2C_F_POLL); 616 617 /* send data */ 618 if (error != 0) { 619 aprint_error_dev(sc->sc_dev, 620 "%s: failed to set time: %d\n", 621 __func__, error); 622 return 0; 623 } 624 625 return 1; 626 } 627
Indexes created Thu Oct 02 14:10:14 GMT 2025