ds1307.c revision 1.2.2.2
1 /* $NetBSD: ds1307.c,v 1.2.2.2 2006/12/30 20:48:00 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/fcntl.h> 43 #include <sys/uio.h> 44 #include <sys/conf.h> 45 #include <sys/event.h> 46 47 #include <dev/clock_subr.h> 48 49 #include <dev/i2c/i2cvar.h> 50 #include <dev/i2c/ds1307reg.h> 51 52 struct dsrtc_softc { 53 struct device sc_dev; 54 i2c_tag_t sc_tag; 55 int sc_address; 56 int sc_open; 57 struct todr_chip_handle sc_todr; 58 }; 59 60 static void dsrtc_attach(struct device *, struct device *, void *); 61 static int dsrtc_match(struct device *, struct cfdata *, void *); 62 63 CFATTACH_DECL(dsrtc, sizeof(struct dsrtc_softc), 64 dsrtc_match, dsrtc_attach, NULL, NULL); 65 extern struct cfdriver dsrtc_cd; 66 67 dev_type_open(dsrtc_open); 68 dev_type_close(dsrtc_close); 69 dev_type_read(dsrtc_read); 70 dev_type_write(dsrtc_write); 71 72 const struct cdevsw dsrtc_cdevsw = { 73 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 74 nostop, notty, nopoll, nommap, nokqfilter 75 }; 76 77 static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *); 78 static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *); 79 static int dsrtc_gettime(struct todr_chip_handle *, struct clock_ymdhms *); 80 static int dsrtc_settime(struct todr_chip_handle *, struct clock_ymdhms *); 81 82 static int 83 dsrtc_match(struct device *parent, struct cfdata *cf, void *arg) 84 { 85 struct i2c_attach_args *ia = arg; 86 87 if (ia->ia_addr == DS1307_ADDR) 88 return (1); 89 90 return (0); 91 } 92 93 static void 94 dsrtc_attach(struct device *parent, struct device *self, void *arg) 95 { 96 struct dsrtc_softc *sc = device_private(self); 97 struct i2c_attach_args *ia = arg; 98 99 aprint_naive(": Real-time Clock/NVRAM\n"); 100 aprint_normal(": DS1307 Real-time Clock/NVRAM\n"); 101 102 sc->sc_tag = ia->ia_tag; 103 sc->sc_address = ia->ia_addr; 104 sc->sc_open = 0; 105 sc->sc_todr.cookie = sc; 106 sc->sc_todr.todr_gettime = NULL; 107 sc->sc_todr.todr_settime = NULL; 108 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime; 109 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime; 110 sc->sc_todr.todr_setwen = NULL; 111 112 todr_attach(&sc->sc_todr); 113 } 114 115 /*ARGSUSED*/ 116 int 117 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 118 { 119 struct dsrtc_softc *sc; 120 121 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 122 return (ENXIO); 123 124 /* XXX: Locking */ 125 126 if (sc->sc_open) 127 return (EBUSY); 128 129 sc->sc_open = 1; 130 return (0); 131 } 132 133 /*ARGSUSED*/ 134 int 135 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 136 { 137 struct dsrtc_softc *sc; 138 139 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 140 return (ENXIO); 141 142 sc->sc_open = 0; 143 return (0); 144 } 145 146 /*ARGSUSED*/ 147 int 148 dsrtc_read(dev_t dev, struct uio *uio, int flags) 149 { 150 struct dsrtc_softc *sc; 151 u_int8_t ch, cmdbuf[1]; 152 int a, error; 153 154 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 155 return (ENXIO); 156 157 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 158 return (EINVAL); 159 160 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 161 return (error); 162 163 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 164 a = (int)uio->uio_offset; 165 cmdbuf[0] = a + DS1307_NVRAM_START; 166 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 167 sc->sc_address, cmdbuf, 1, 168 &ch, 1, 0)) != 0) { 169 iic_release_bus(sc->sc_tag, 0); 170 printf("%s: dsrtc_read: read failed at 0x%x\n", 171 sc->sc_dev.dv_xname, a); 172 return (error); 173 } 174 if ((error = uiomove(&ch, 1, uio)) != 0) { 175 iic_release_bus(sc->sc_tag, 0); 176 return (error); 177 } 178 } 179 180 iic_release_bus(sc->sc_tag, 0); 181 182 return (0); 183 } 184 185 /*ARGSUSED*/ 186 int 187 dsrtc_write(dev_t dev, struct uio *uio, int flags) 188 { 189 struct dsrtc_softc *sc; 190 u_int8_t cmdbuf[2]; 191 int a, error; 192 193 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 194 return (ENXIO); 195 196 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 197 return (EINVAL); 198 199 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 200 return (error); 201 202 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 203 a = (int)uio->uio_offset; 204 cmdbuf[0] = a + DS1307_NVRAM_START; 205 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 206 break; 207 208 if ((error = iic_exec(sc->sc_tag, 209 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 210 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 211 printf("%s: dsrtc_write: write failed at 0x%x\n", 212 sc->sc_dev.dv_xname, a); 213 break; 214 } 215 } 216 217 iic_release_bus(sc->sc_tag, 0); 218 219 return (error); 220 } 221 222 static int 223 dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 224 { 225 struct dsrtc_softc *sc = ch->cookie; 226 struct clock_ymdhms check; 227 int retries; 228 229 memset(dt, 0, sizeof(*dt)); 230 memset(&check, 0, sizeof(check)); 231 232 /* 233 * Since we don't support Burst Read, we have to read the clock twice 234 * until we get two consecutive identical results. 235 */ 236 retries = 5; 237 do { 238 dsrtc_clock_read(sc, dt); 239 dsrtc_clock_read(sc, &check); 240 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 241 242 return (0); 243 } 244 245 static int 246 dsrtc_settime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 247 { 248 struct dsrtc_softc *sc = ch->cookie; 249 250 if (dsrtc_clock_write(sc, dt) == 0) 251 return (-1); 252 253 return (0); 254 } 255 256 static int 257 dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 258 { 259 u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1]; 260 int i; 261 262 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 263 printf("%s: dsrtc_clock_read: failed to acquire I2C bus\n", 264 sc->sc_dev.dv_xname); 265 return (0); 266 } 267 268 /* Read each RTC register in order. */ 269 for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) { 270 cmdbuf[0] = i; 271 272 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 273 sc->sc_address, cmdbuf, 1, 274 &bcd[i], 1, I2C_F_POLL)) { 275 iic_release_bus(sc->sc_tag, I2C_F_POLL); 276 printf("%s: dsrtc_clock_read: failed to read rtc " 277 "at 0x%x\n", sc->sc_dev.dv_xname, i); 278 return (0); 279 } 280 } 281 282 /* Done with I2C */ 283 iic_release_bus(sc->sc_tag, I2C_F_POLL); 284 285 /* 286 * Convert the DS1307's register values into something useable 287 */ 288 dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK); 289 dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK); 290 291 if ((bcd[DS1307_HOURS] & DS1307_HOURS_24HRS) == 0) { 292 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 293 DS1307_HOURS_12MASK); 294 if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM) 295 dt->dt_hour += 12; 296 } else { 297 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 298 DS1307_HOURS_24MASK); 299 } 300 301 dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK); 302 dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK); 303 304 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 305 dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR; 306 307 return (1); 308 } 309 310 static int 311 dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 312 { 313 uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2]; 314 int i; 315 316 /* 317 * Convert our time representation into something the DS1307 318 * can understand. 319 */ 320 bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec); 321 bcd[DS1307_MINUTES] = TOBCD(dt->dt_min); 322 bcd[DS1307_HOURS] = TOBCD(dt->dt_hour) | DS1307_HOURS_24HRS; 323 bcd[DS1307_DATE] = TOBCD(dt->dt_day); 324 bcd[DS1307_DAY] = TOBCD(dt->dt_wday); 325 bcd[DS1307_MONTH] = TOBCD(dt->dt_mon); 326 bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 327 328 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 329 printf("%s: dsrtc_clock_write: failed to acquire I2C bus\n", 330 sc->sc_dev.dv_xname); 331 return (0); 332 } 333 334 /* Stop the clock */ 335 cmdbuf[0] = DS1307_SECONDS; 336 cmdbuf[1] = DS1307_SECONDS_CH; 337 338 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 339 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 340 iic_release_bus(sc->sc_tag, I2C_F_POLL); 341 printf("%s: dsrtc_clock_write: failed to Hold Clock\n", 342 sc->sc_dev.dv_xname); 343 return (0); 344 } 345 346 /* 347 * Write registers in reverse order. The last write (to the Seconds 348 * register) will undo the Clock Hold, above. 349 */ 350 for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) { 351 cmdbuf[0] = i; 352 if (iic_exec(sc->sc_tag, 353 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 354 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 355 I2C_F_POLL)) { 356 iic_release_bus(sc->sc_tag, I2C_F_POLL); 357 printf("%s: dsrtc_clock_write: failed to write rtc " 358 " at 0x%x\n", sc->sc_dev.dv_xname, i); 359 /* XXX: Clock Hold is likely still asserted! */ 360 return (0); 361 } 362 } 363 364 iic_release_bus(sc->sc_tag, I2C_F_POLL); 365 366 return (1); 367 } 368
Indexes created Thu Oct 02 10:09:58 GMT 2025