ds1307.c revision 1.2.2.4
1 /* $NetBSD: ds1307.c,v 1.2.2.4 2008/01/21 09:42:49 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.2.2.4 2008/01/21 09:42:49 yamt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 55 struct dsrtc_softc { 56 struct device sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void dsrtc_attach(struct device *, struct device *, void *); 64 static int dsrtc_match(struct device *, struct cfdata *, void *); 65 66 CFATTACH_DECL(dsrtc, sizeof(struct dsrtc_softc), 67 dsrtc_match, dsrtc_attach, NULL, NULL); 68 extern struct cfdriver dsrtc_cd; 69 70 dev_type_open(dsrtc_open); 71 dev_type_close(dsrtc_close); 72 dev_type_read(dsrtc_read); 73 dev_type_write(dsrtc_write); 74 75 const struct cdevsw dsrtc_cdevsw = { 76 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *); 81 static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *); 82 static int dsrtc_gettime(struct todr_chip_handle *, struct clock_ymdhms *); 83 static int dsrtc_settime(struct todr_chip_handle *, struct clock_ymdhms *); 84 85 static int 86 dsrtc_match(struct device *parent, struct cfdata *cf, void *arg) 87 { 88 struct i2c_attach_args *ia = arg; 89 90 if (ia->ia_addr == DS1307_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 static void 97 dsrtc_attach(struct device *parent, struct device *self, void *arg) 98 { 99 struct dsrtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = arg; 101 102 aprint_naive(": Real-time Clock/NVRAM\n"); 103 aprint_normal(": DS1307 Real-time Clock/NVRAM\n"); 104 105 sc->sc_tag = ia->ia_tag; 106 sc->sc_address = ia->ia_addr; 107 sc->sc_open = 0; 108 sc->sc_todr.cookie = sc; 109 sc->sc_todr.todr_gettime = NULL; 110 sc->sc_todr.todr_settime = NULL; 111 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime; 112 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime; 113 sc->sc_todr.todr_setwen = NULL; 114 115 todr_attach(&sc->sc_todr); 116 } 117 118 /*ARGSUSED*/ 119 int 120 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 121 { 122 struct dsrtc_softc *sc; 123 124 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 125 return (ENXIO); 126 127 /* XXX: Locking */ 128 129 if (sc->sc_open) 130 return (EBUSY); 131 132 sc->sc_open = 1; 133 return (0); 134 } 135 136 /*ARGSUSED*/ 137 int 138 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 139 { 140 struct dsrtc_softc *sc; 141 142 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 143 return (ENXIO); 144 145 sc->sc_open = 0; 146 return (0); 147 } 148 149 /*ARGSUSED*/ 150 int 151 dsrtc_read(dev_t dev, struct uio *uio, int flags) 152 { 153 struct dsrtc_softc *sc; 154 u_int8_t ch, cmdbuf[1]; 155 int a, error; 156 157 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 158 return (ENXIO); 159 160 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 161 return (EINVAL); 162 163 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 164 return (error); 165 166 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 167 a = (int)uio->uio_offset; 168 cmdbuf[0] = a + DS1307_NVRAM_START; 169 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 170 sc->sc_address, cmdbuf, 1, 171 &ch, 1, 0)) != 0) { 172 iic_release_bus(sc->sc_tag, 0); 173 printf("%s: dsrtc_read: read failed at 0x%x\n", 174 sc->sc_dev.dv_xname, a); 175 return (error); 176 } 177 if ((error = uiomove(&ch, 1, uio)) != 0) { 178 iic_release_bus(sc->sc_tag, 0); 179 return (error); 180 } 181 } 182 183 iic_release_bus(sc->sc_tag, 0); 184 185 return (0); 186 } 187 188 /*ARGSUSED*/ 189 int 190 dsrtc_write(dev_t dev, struct uio *uio, int flags) 191 { 192 struct dsrtc_softc *sc; 193 u_int8_t cmdbuf[2]; 194 int a, error; 195 196 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 197 return (ENXIO); 198 199 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 200 return (EINVAL); 201 202 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 203 return (error); 204 205 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 206 a = (int)uio->uio_offset; 207 cmdbuf[0] = a + DS1307_NVRAM_START; 208 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 209 break; 210 211 if ((error = iic_exec(sc->sc_tag, 212 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 213 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 214 printf("%s: dsrtc_write: write failed at 0x%x\n", 215 sc->sc_dev.dv_xname, a); 216 break; 217 } 218 } 219 220 iic_release_bus(sc->sc_tag, 0); 221 222 return (error); 223 } 224 225 static int 226 dsrtc_gettime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 227 { 228 struct dsrtc_softc *sc = ch->cookie; 229 struct clock_ymdhms check; 230 int retries; 231 232 memset(dt, 0, sizeof(*dt)); 233 memset(&check, 0, sizeof(check)); 234 235 /* 236 * Since we don't support Burst Read, we have to read the clock twice 237 * until we get two consecutive identical results. 238 */ 239 retries = 5; 240 do { 241 dsrtc_clock_read(sc, dt); 242 dsrtc_clock_read(sc, &check); 243 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 244 245 return (0); 246 } 247 248 static int 249 dsrtc_settime(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 250 { 251 struct dsrtc_softc *sc = ch->cookie; 252 253 if (dsrtc_clock_write(sc, dt) == 0) 254 return (-1); 255 256 return (0); 257 } 258 259 static int 260 dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 261 { 262 u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1]; 263 int i; 264 265 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 266 printf("%s: dsrtc_clock_read: failed to acquire I2C bus\n", 267 sc->sc_dev.dv_xname); 268 return (0); 269 } 270 271 /* Read each RTC register in order. */ 272 for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) { 273 cmdbuf[0] = i; 274 275 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 276 sc->sc_address, cmdbuf, 1, 277 &bcd[i], 1, I2C_F_POLL)) { 278 iic_release_bus(sc->sc_tag, I2C_F_POLL); 279 printf("%s: dsrtc_clock_read: failed to read rtc " 280 "at 0x%x\n", sc->sc_dev.dv_xname, i); 281 return (0); 282 } 283 } 284 285 /* Done with I2C */ 286 iic_release_bus(sc->sc_tag, I2C_F_POLL); 287 288 /* 289 * Convert the DS1307's register values into something useable 290 */ 291 dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK); 292 dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK); 293 294 if ((bcd[DS1307_HOURS] & DS1307_HOURS_24HRS) == 0) { 295 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 296 DS1307_HOURS_12MASK); 297 if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM) 298 dt->dt_hour += 12; 299 } else { 300 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 301 DS1307_HOURS_24MASK); 302 } 303 304 dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK); 305 dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK); 306 307 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 308 dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR; 309 310 return (1); 311 } 312 313 static int 314 dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 315 { 316 uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2]; 317 int i; 318 319 /* 320 * Convert our time representation into something the DS1307 321 * can understand. 322 */ 323 bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec); 324 bcd[DS1307_MINUTES] = TOBCD(dt->dt_min); 325 bcd[DS1307_HOURS] = TOBCD(dt->dt_hour) | DS1307_HOURS_24HRS; 326 bcd[DS1307_DATE] = TOBCD(dt->dt_day); 327 bcd[DS1307_DAY] = TOBCD(dt->dt_wday); 328 bcd[DS1307_MONTH] = TOBCD(dt->dt_mon); 329 bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 330 331 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 332 printf("%s: dsrtc_clock_write: failed to acquire I2C bus\n", 333 sc->sc_dev.dv_xname); 334 return (0); 335 } 336 337 /* Stop the clock */ 338 cmdbuf[0] = DS1307_SECONDS; 339 cmdbuf[1] = DS1307_SECONDS_CH; 340 341 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 342 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 343 iic_release_bus(sc->sc_tag, I2C_F_POLL); 344 printf("%s: dsrtc_clock_write: failed to Hold Clock\n", 345 sc->sc_dev.dv_xname); 346 return (0); 347 } 348 349 /* 350 * Write registers in reverse order. The last write (to the Seconds 351 * register) will undo the Clock Hold, above. 352 */ 353 for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) { 354 cmdbuf[0] = i; 355 if (iic_exec(sc->sc_tag, 356 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 357 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 358 I2C_F_POLL)) { 359 iic_release_bus(sc->sc_tag, I2C_F_POLL); 360 printf("%s: dsrtc_clock_write: failed to write rtc " 361 " at 0x%x\n", sc->sc_dev.dv_xname, i); 362 /* XXX: Clock Hold is likely still asserted! */ 363 return (0); 364 } 365 } 366 367 iic_release_bus(sc->sc_tag, I2C_F_POLL); 368 369 return (1); 370 } 371
Indexes created Thu Oct 02 14:10:14 GMT 2025