ds1307.c revision 1.21
1 /* $NetBSD: ds1307.c,v 1.21 2014/11/20 16:34:26 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.21 2014/11/20 16:34:26 christos Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 struct dsrtc_model { 57 uint16_t dm_model; 58 uint8_t dm_ch_reg; 59 uint8_t dm_ch_value; 60 uint8_t dm_rtc_start; 61 uint8_t dm_rtc_size; 62 uint8_t dm_nvram_start; 63 uint8_t dm_nvram_size; 64 uint8_t dm_flags; 65 #define DSRTC_FLAG_CLOCK_HOLD 1 66 #define DSRTC_FLAG_BCD 2 67 #define DSRTC_FLAG_TEMP 4 68 }; 69 70 static const struct dsrtc_model dsrtc_models[] = { 71 { 72 .dm_model = 1307, 73 .dm_ch_reg = DSXXXX_SECONDS, 74 .dm_ch_value = DS1307_SECONDS_CH, 75 .dm_rtc_start = DS1307_RTC_START, 76 .dm_rtc_size = DS1307_RTC_SIZE, 77 .dm_nvram_start = DS1307_NVRAM_START, 78 .dm_nvram_size = DS1307_NVRAM_SIZE, 79 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 80 }, { 81 .dm_model = 1339, 82 .dm_rtc_start = DS1339_RTC_START, 83 .dm_rtc_size = DS1339_RTC_SIZE, 84 .dm_flags = DSRTC_FLAG_BCD, 85 }, { 86 .dm_model = 1672, 87 .dm_rtc_start = DS1672_RTC_START, 88 .dm_rtc_size = DS1672_RTC_SIZE, 89 .dm_flags = 0, 90 }, { 91 .dm_model = 3231, 92 .dm_rtc_start = DS3232_RTC_START, 93 .dm_rtc_size = DS3232_RTC_SIZE, 94 /* 95 * XXX 96 * the DS3232 likely has the temperature sensor too but I can't 97 * easily verify or test that right now 98 */ 99 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 100 }, { 101 .dm_model = 3232, 102 .dm_rtc_start = DS3232_RTC_START, 103 .dm_rtc_size = DS3232_RTC_SIZE, 104 .dm_nvram_start = DS3232_NVRAM_START, 105 .dm_nvram_size = DS3232_NVRAM_SIZE, 106 .dm_flags = DSRTC_FLAG_BCD, 107 }, 108 }; 109 110 struct dsrtc_softc { 111 device_t sc_dev; 112 i2c_tag_t sc_tag; 113 uint8_t sc_address; 114 bool sc_open; 115 struct dsrtc_model sc_model; 116 struct todr_chip_handle sc_todr; 117 struct sysmon_envsys *sc_sme; 118 envsys_data_t sc_sensor; 119 }; 120 121 static void dsrtc_attach(device_t, device_t, void *); 122 static int dsrtc_match(device_t, cfdata_t, void *); 123 124 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 125 dsrtc_match, dsrtc_attach, NULL, NULL); 126 extern struct cfdriver dsrtc_cd; 127 128 dev_type_open(dsrtc_open); 129 dev_type_close(dsrtc_close); 130 dev_type_read(dsrtc_read); 131 dev_type_write(dsrtc_write); 132 133 const struct cdevsw dsrtc_cdevsw = { 134 .d_open = dsrtc_open, 135 .d_close = dsrtc_close, 136 .d_read = dsrtc_read, 137 .d_write = dsrtc_write, 138 .d_ioctl = noioctl, 139 .d_stop = nostop, 140 .d_tty = notty, 141 .d_poll = nopoll, 142 .d_mmap = nommap, 143 .d_kqfilter = nokqfilter, 144 .d_discard = nodiscard, 145 .d_flag = D_OTHER 146 }; 147 148 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 149 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 150 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 151 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 152 153 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 154 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 155 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 156 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 157 158 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 159 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 160 161 static const struct dsrtc_model * 162 dsrtc_model(u_int model) 163 { 164 /* no model given, assume it's a DS1307 (the first one) */ 165 if (model == 0) 166 return &dsrtc_models[0]; 167 168 for (const struct dsrtc_model *dm = dsrtc_models; 169 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 170 if (dm->dm_model == model) 171 return dm; 172 } 173 return NULL; 174 } 175 176 static int 177 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 178 { 179 struct i2c_attach_args *ia = arg; 180 181 if (ia->ia_name) { 182 /* direct config - check name */ 183 if (strcmp(ia->ia_name, "dsrtc") == 0) 184 return 1; 185 } else { 186 /* indirect config - check typical address */ 187 if (ia->ia_addr == DS1307_ADDR) 188 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 189 } 190 return 0; 191 } 192 193 static void 194 dsrtc_attach(device_t parent, device_t self, void *arg) 195 { 196 struct dsrtc_softc *sc = device_private(self); 197 struct i2c_attach_args *ia = arg; 198 const struct dsrtc_model * const dm = 199 dsrtc_model(device_cfdata(self)->cf_flags); 200 201 aprint_naive(": Real-time Clock%s\n", 202 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 203 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 204 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 205 206 sc->sc_tag = ia->ia_tag; 207 sc->sc_address = ia->ia_addr; 208 sc->sc_model = *dm; 209 sc->sc_dev = self; 210 sc->sc_open = 0; 211 sc->sc_todr.cookie = sc; 212 if (dm->dm_flags & DSRTC_FLAG_BCD) { 213 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 214 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 215 } else { 216 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 217 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 218 } 219 sc->sc_todr.todr_setwen = NULL; 220 221 todr_attach(&sc->sc_todr); 222 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 223 int error; 224 225 sc->sc_sme = sysmon_envsys_create(); 226 sc->sc_sme->sme_name = device_xname(self); 227 sc->sc_sme->sme_cookie = sc; 228 sc->sc_sme->sme_refresh = dsrtc_refresh; 229 230 sc->sc_sensor.units = ENVSYS_STEMP; 231 sc->sc_sensor.state = ENVSYS_SINVALID; 232 sc->sc_sensor.flags = 0; 233 (void)strlcpy(sc->sc_sensor.desc, "temperature", 234 sizeof(sc->sc_sensor.desc)); 235 236 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 237 aprint_error_dev(self, "unable to attach sensor\n"); 238 goto bad; 239 } 240 241 error = sysmon_envsys_register(sc->sc_sme); 242 if (error) { 243 aprint_error_dev(self, 244 "error %d registering with sysmon\n", error); 245 goto bad; 246 } 247 } 248 return; 249 bad: 250 sysmon_envsys_destroy(sc->sc_sme); 251 } 252 253 /*ARGSUSED*/ 254 int 255 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 256 { 257 struct dsrtc_softc *sc; 258 259 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 260 return ENXIO; 261 262 /* XXX: Locking */ 263 if (sc->sc_open) 264 return EBUSY; 265 266 sc->sc_open = true; 267 return 0; 268 } 269 270 /*ARGSUSED*/ 271 int 272 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 273 { 274 struct dsrtc_softc *sc; 275 276 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 277 return ENXIO; 278 279 sc->sc_open = false; 280 return 0; 281 } 282 283 /*ARGSUSED*/ 284 int 285 dsrtc_read(dev_t dev, struct uio *uio, int flags) 286 { 287 struct dsrtc_softc *sc; 288 int error; 289 290 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 291 return ENXIO; 292 293 const struct dsrtc_model * const dm = &sc->sc_model; 294 if (uio->uio_offset >= dm->dm_nvram_size) 295 return EINVAL; 296 297 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 298 return error; 299 300 KASSERT(uio->uio_offset >= 0); 301 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 302 uint8_t ch, cmd; 303 const u_int a = uio->uio_offset; 304 cmd = a + dm->dm_nvram_start; 305 if ((error = iic_exec(sc->sc_tag, 306 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 307 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 308 iic_release_bus(sc->sc_tag, 0); 309 aprint_error_dev(sc->sc_dev, 310 "%s: read failed at 0x%x: %d\n", 311 __func__, a, error); 312 return error; 313 } 314 if ((error = uiomove(&ch, 1, uio)) != 0) { 315 iic_release_bus(sc->sc_tag, 0); 316 return error; 317 } 318 } 319 320 iic_release_bus(sc->sc_tag, 0); 321 322 return 0; 323 } 324 325 /*ARGSUSED*/ 326 int 327 dsrtc_write(dev_t dev, struct uio *uio, int flags) 328 { 329 struct dsrtc_softc *sc; 330 int error; 331 332 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 333 return ENXIO; 334 335 const struct dsrtc_model * const dm = &sc->sc_model; 336 if (uio->uio_offset >= dm->dm_nvram_size) 337 return EINVAL; 338 339 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 340 return error; 341 342 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 343 uint8_t cmdbuf[2]; 344 const u_int a = (int)uio->uio_offset; 345 cmdbuf[0] = a + dm->dm_nvram_start; 346 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 347 break; 348 349 if ((error = iic_exec(sc->sc_tag, 350 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 351 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 352 aprint_error_dev(sc->sc_dev, 353 "%s: write failed at 0x%x: %d\n", 354 __func__, a, error); 355 break; 356 } 357 } 358 359 iic_release_bus(sc->sc_tag, 0); 360 361 return error; 362 } 363 364 static int 365 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 366 { 367 struct dsrtc_softc *sc = ch->cookie; 368 struct clock_ymdhms check; 369 int retries; 370 371 memset(dt, 0, sizeof(*dt)); 372 memset(&check, 0, sizeof(check)); 373 374 /* 375 * Since we don't support Burst Read, we have to read the clock twice 376 * until we get two consecutive identical results. 377 */ 378 retries = 5; 379 do { 380 dsrtc_clock_read_ymdhms(sc, dt); 381 dsrtc_clock_read_ymdhms(sc, &check); 382 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 383 384 return 0; 385 } 386 387 static int 388 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 389 { 390 struct dsrtc_softc *sc = ch->cookie; 391 392 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 393 return -1; 394 395 return 0; 396 } 397 398 static int 399 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 400 { 401 struct dsrtc_model * const dm = &sc->sc_model; 402 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 403 int error; 404 405 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 406 407 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 408 aprint_error_dev(sc->sc_dev, 409 "%s: failed to acquire I2C bus: %d\n", 410 __func__, error); 411 return 0; 412 } 413 414 /* Read each RTC register in order. */ 415 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 416 cmdbuf[0] = dm->dm_rtc_start + i; 417 418 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 419 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 420 } 421 422 /* Done with I2C */ 423 iic_release_bus(sc->sc_tag, I2C_F_POLL); 424 425 if (error != 0) { 426 aprint_error_dev(sc->sc_dev, 427 "%s: failed to read rtc at 0x%x: %d\n", 428 __func__, cmdbuf[0], error); 429 return 0; 430 } 431 432 /* 433 * Convert the RTC's register values into something useable 434 */ 435 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 436 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 437 438 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 439 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 440 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 441 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 442 dt->dt_hour += 12; 443 } else 444 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 445 DSXXXX_HOURS_24MASK); 446 447 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 448 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 449 450 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 451 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 452 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 453 dt->dt_year += 100; 454 455 return 1; 456 } 457 458 static int 459 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 460 { 461 struct dsrtc_model * const dm = &sc->sc_model; 462 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 463 int error; 464 465 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 466 467 /* 468 * Convert our time representation into something the DSXXXX 469 * can understand. 470 */ 471 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 472 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 473 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 474 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 475 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 476 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 477 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 478 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 479 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 480 481 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 482 aprint_error_dev(sc->sc_dev, 483 "%s: failed to acquire I2C bus: %d\n", 484 __func__, error); 485 return 0; 486 } 487 488 /* Stop the clock */ 489 cmdbuf[0] = dm->dm_ch_reg; 490 491 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 492 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 493 iic_release_bus(sc->sc_tag, I2C_F_POLL); 494 aprint_error_dev(sc->sc_dev, 495 "%s: failed to read Hold Clock: %d\n", 496 __func__, error); 497 return 0; 498 } 499 500 cmdbuf[1] |= dm->dm_ch_value; 501 502 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 503 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 504 iic_release_bus(sc->sc_tag, I2C_F_POLL); 505 aprint_error_dev(sc->sc_dev, 506 "%s: failed to write Hold Clock: %d\n", 507 __func__, error); 508 return 0; 509 } 510 511 /* 512 * Write registers in reverse order. The last write (to the Seconds 513 * register) will undo the Clock Hold, above. 514 */ 515 uint8_t op = I2C_OP_WRITE; 516 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 517 cmdbuf[0] = dm->dm_rtc_start + i; 518 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 519 op = I2C_OP_WRITE_WITH_STOP; 520 } 521 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 522 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 523 iic_release_bus(sc->sc_tag, I2C_F_POLL); 524 aprint_error_dev(sc->sc_dev, 525 "%s: failed to write rtc at 0x%x: %d\n", 526 __func__, i, error); 527 /* XXX: Clock Hold is likely still asserted! */ 528 return 0; 529 } 530 } 531 /* 532 * If the clock hold register isn't the same register as seconds, 533 * we need to reeanble the clock. 534 */ 535 if (op != I2C_OP_WRITE_WITH_STOP) { 536 cmdbuf[0] = dm->dm_ch_reg; 537 cmdbuf[1] &= ~dm->dm_ch_value; 538 539 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 540 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 541 I2C_F_POLL)) != 0) { 542 iic_release_bus(sc->sc_tag, I2C_F_POLL); 543 aprint_error_dev(sc->sc_dev, 544 "%s: failed to Hold Clock: %d\n", 545 __func__, error); 546 return 0; 547 } 548 } 549 550 iic_release_bus(sc->sc_tag, I2C_F_POLL); 551 552 return 1; 553 } 554 555 static int 556 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 557 { 558 struct dsrtc_softc *sc = ch->cookie; 559 struct timeval check; 560 int retries; 561 562 memset(tv, 0, sizeof(*tv)); 563 memset(&check, 0, sizeof(check)); 564 565 /* 566 * Since we don't support Burst Read, we have to read the clock twice 567 * until we get two consecutive identical results. 568 */ 569 retries = 5; 570 do { 571 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 572 dsrtc_clock_read_timeval(sc, &check.tv_sec); 573 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 574 575 return 0; 576 } 577 578 static int 579 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 580 { 581 struct dsrtc_softc *sc = ch->cookie; 582 583 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 584 return -1; 585 586 return 0; 587 } 588 589 /* 590 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 591 * it, since some I2C controllers don't support anything other than single-byte 592 * transfers. 593 */ 594 static int 595 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 596 { 597 const struct dsrtc_model * const dm = &sc->sc_model; 598 uint8_t buf[4]; 599 int error; 600 601 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 602 aprint_error_dev(sc->sc_dev, 603 "%s: failed to acquire I2C bus: %d\n", 604 __func__, error); 605 return 0; 606 } 607 608 /* read all registers: */ 609 uint8_t reg = dm->dm_rtc_start; 610 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 611 ®, 1, buf, 4, I2C_F_POLL); 612 613 /* Done with I2C */ 614 iic_release_bus(sc->sc_tag, I2C_F_POLL); 615 616 if (error != 0) { 617 aprint_error_dev(sc->sc_dev, 618 "%s: failed to read rtc at 0x%x: %d\n", 619 __func__, reg, error); 620 return 0; 621 } 622 623 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 624 *tp = v; 625 626 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 627 __func__, v); 628 629 return 1; 630 } 631 632 static int 633 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 634 { 635 const struct dsrtc_model * const dm = &sc->sc_model; 636 size_t buflen = dm->dm_rtc_size + 2; 637 uint8_t buf[buflen]; 638 int error; 639 640 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 641 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 642 643 buf[0] = dm->dm_rtc_start; 644 buf[1] = (t >> 0) & 0xff; 645 buf[2] = (t >> 8) & 0xff; 646 buf[3] = (t >> 16) & 0xff; 647 buf[4] = (t >> 24) & 0xff; 648 buf[5] = 0; 649 650 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 651 aprint_error_dev(sc->sc_dev, 652 "%s: failed to acquire I2C bus: %d\n", 653 __func__, error); 654 return 0; 655 } 656 657 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 658 &buf, buflen, NULL, 0, I2C_F_POLL); 659 660 /* Done with I2C */ 661 iic_release_bus(sc->sc_tag, I2C_F_POLL); 662 663 /* send data */ 664 if (error != 0) { 665 aprint_error_dev(sc->sc_dev, 666 "%s: failed to set time: %d\n", 667 __func__, error); 668 return 0; 669 } 670 671 return 1; 672 } 673 674 static int 675 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 676 { 677 int error, tc; 678 uint8_t reg = DS3232_TEMP_MSB; 679 uint8_t buf[2]; 680 681 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 682 return ENOTSUP; 683 684 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 685 aprint_error_dev(sc->sc_dev, 686 "%s: failed to acquire I2C bus: %d\n", 687 __func__, error); 688 return 0; 689 } 690 691 /* read temperature registers: */ 692 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 693 ®, 1, buf, 2, I2C_F_POLL); 694 695 /* Done with I2C */ 696 iic_release_bus(sc->sc_tag, I2C_F_POLL); 697 698 if (error != 0) { 699 aprint_error_dev(sc->sc_dev, 700 "%s: failed to read temperature: %d\n", 701 __func__, error); 702 return 0; 703 } 704 705 /* convert to microkelvin */ 706 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 707 *temp = tc + 273150000; 708 return 1; 709 } 710 711 static void 712 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 713 { 714 struct dsrtc_softc *sc = sme->sme_cookie; 715 uint32_t temp = 0; /* XXX gcc */ 716 717 if (dsrtc_read_temp(sc, &temp) == 0) { 718 edata->state = ENVSYS_SINVALID; 719 return; 720 } 721 722 edata->value_cur = temp; 723 724 edata->state = ENVSYS_SVALID; 725 } 726
Indexes created Thu Oct 02 10:09:58 GMT 2025