ds1307.c revision 1.22
1 /* $NetBSD: ds1307.c,v 1.22 2016/04/05 10:53:16 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.22 2016/04/05 10:53:16 bouyer Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 struct dsrtc_model { 57 uint16_t dm_model; 58 uint8_t dm_ch_reg; 59 uint8_t dm_ch_value; 60 uint8_t dm_rtc_start; 61 uint8_t dm_rtc_size; 62 uint8_t dm_nvram_start; 63 uint8_t dm_nvram_size; 64 uint8_t dm_flags; 65 #define DSRTC_FLAG_CLOCK_HOLD 1 66 #define DSRTC_FLAG_BCD 2 67 #define DSRTC_FLAG_TEMP 4 68 }; 69 70 static const struct dsrtc_model dsrtc_models[] = { 71 { 72 .dm_model = 1307, 73 .dm_ch_reg = DSXXXX_SECONDS, 74 .dm_ch_value = DS1307_SECONDS_CH, 75 .dm_rtc_start = DS1307_RTC_START, 76 .dm_rtc_size = DS1307_RTC_SIZE, 77 .dm_nvram_start = DS1307_NVRAM_START, 78 .dm_nvram_size = DS1307_NVRAM_SIZE, 79 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 80 }, { 81 .dm_model = 1339, 82 .dm_rtc_start = DS1339_RTC_START, 83 .dm_rtc_size = DS1339_RTC_SIZE, 84 .dm_flags = DSRTC_FLAG_BCD, 85 }, { 86 .dm_model = 1672, 87 .dm_rtc_start = DS1672_RTC_START, 88 .dm_rtc_size = DS1672_RTC_SIZE, 89 .dm_ch_reg = DS1672_CONTROL, 90 .dm_ch_value = DS1672_CONTROL_CH, 91 .dm_flags = 0, 92 }, { 93 .dm_model = 3231, 94 .dm_rtc_start = DS3232_RTC_START, 95 .dm_rtc_size = DS3232_RTC_SIZE, 96 /* 97 * XXX 98 * the DS3232 likely has the temperature sensor too but I can't 99 * easily verify or test that right now 100 */ 101 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 102 }, { 103 .dm_model = 3232, 104 .dm_rtc_start = DS3232_RTC_START, 105 .dm_rtc_size = DS3232_RTC_SIZE, 106 .dm_nvram_start = DS3232_NVRAM_START, 107 .dm_nvram_size = DS3232_NVRAM_SIZE, 108 .dm_flags = DSRTC_FLAG_BCD, 109 }, 110 }; 111 112 struct dsrtc_softc { 113 device_t sc_dev; 114 i2c_tag_t sc_tag; 115 uint8_t sc_address; 116 bool sc_open; 117 struct dsrtc_model sc_model; 118 struct todr_chip_handle sc_todr; 119 struct sysmon_envsys *sc_sme; 120 envsys_data_t sc_sensor; 121 }; 122 123 static void dsrtc_attach(device_t, device_t, void *); 124 static int dsrtc_match(device_t, cfdata_t, void *); 125 126 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 127 dsrtc_match, dsrtc_attach, NULL, NULL); 128 extern struct cfdriver dsrtc_cd; 129 130 dev_type_open(dsrtc_open); 131 dev_type_close(dsrtc_close); 132 dev_type_read(dsrtc_read); 133 dev_type_write(dsrtc_write); 134 135 const struct cdevsw dsrtc_cdevsw = { 136 .d_open = dsrtc_open, 137 .d_close = dsrtc_close, 138 .d_read = dsrtc_read, 139 .d_write = dsrtc_write, 140 .d_ioctl = noioctl, 141 .d_stop = nostop, 142 .d_tty = notty, 143 .d_poll = nopoll, 144 .d_mmap = nommap, 145 .d_kqfilter = nokqfilter, 146 .d_discard = nodiscard, 147 .d_flag = D_OTHER 148 }; 149 150 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 151 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 152 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 153 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 154 155 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 156 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 157 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 158 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 159 160 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 161 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 162 163 static const struct dsrtc_model * 164 dsrtc_model(u_int model) 165 { 166 /* no model given, assume it's a DS1307 (the first one) */ 167 if (model == 0) 168 return &dsrtc_models[0]; 169 170 for (const struct dsrtc_model *dm = dsrtc_models; 171 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 172 if (dm->dm_model == model) 173 return dm; 174 } 175 return NULL; 176 } 177 178 static int 179 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 180 { 181 struct i2c_attach_args *ia = arg; 182 183 if (ia->ia_name) { 184 /* direct config - check name */ 185 if (strcmp(ia->ia_name, "dsrtc") == 0) 186 return 1; 187 } else { 188 /* indirect config - check typical address */ 189 if (ia->ia_addr == DS1307_ADDR) 190 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 191 } 192 return 0; 193 } 194 195 static void 196 dsrtc_attach(device_t parent, device_t self, void *arg) 197 { 198 struct dsrtc_softc *sc = device_private(self); 199 struct i2c_attach_args *ia = arg; 200 const struct dsrtc_model * const dm = 201 dsrtc_model(device_cfdata(self)->cf_flags); 202 203 aprint_naive(": Real-time Clock%s\n", 204 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 205 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 206 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 207 208 sc->sc_tag = ia->ia_tag; 209 sc->sc_address = ia->ia_addr; 210 sc->sc_model = *dm; 211 sc->sc_dev = self; 212 sc->sc_open = 0; 213 sc->sc_todr.cookie = sc; 214 if (dm->dm_flags & DSRTC_FLAG_BCD) { 215 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 216 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 217 } else { 218 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 219 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 220 } 221 sc->sc_todr.todr_setwen = NULL; 222 223 todr_attach(&sc->sc_todr); 224 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 225 int error; 226 227 sc->sc_sme = sysmon_envsys_create(); 228 sc->sc_sme->sme_name = device_xname(self); 229 sc->sc_sme->sme_cookie = sc; 230 sc->sc_sme->sme_refresh = dsrtc_refresh; 231 232 sc->sc_sensor.units = ENVSYS_STEMP; 233 sc->sc_sensor.state = ENVSYS_SINVALID; 234 sc->sc_sensor.flags = 0; 235 (void)strlcpy(sc->sc_sensor.desc, "temperature", 236 sizeof(sc->sc_sensor.desc)); 237 238 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 239 aprint_error_dev(self, "unable to attach sensor\n"); 240 goto bad; 241 } 242 243 error = sysmon_envsys_register(sc->sc_sme); 244 if (error) { 245 aprint_error_dev(self, 246 "error %d registering with sysmon\n", error); 247 goto bad; 248 } 249 } 250 return; 251 bad: 252 sysmon_envsys_destroy(sc->sc_sme); 253 } 254 255 /*ARGSUSED*/ 256 int 257 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 258 { 259 struct dsrtc_softc *sc; 260 261 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 262 return ENXIO; 263 264 /* XXX: Locking */ 265 if (sc->sc_open) 266 return EBUSY; 267 268 sc->sc_open = true; 269 return 0; 270 } 271 272 /*ARGSUSED*/ 273 int 274 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 275 { 276 struct dsrtc_softc *sc; 277 278 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 279 return ENXIO; 280 281 sc->sc_open = false; 282 return 0; 283 } 284 285 /*ARGSUSED*/ 286 int 287 dsrtc_read(dev_t dev, struct uio *uio, int flags) 288 { 289 struct dsrtc_softc *sc; 290 int error; 291 292 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 293 return ENXIO; 294 295 const struct dsrtc_model * const dm = &sc->sc_model; 296 if (uio->uio_offset >= dm->dm_nvram_size) 297 return EINVAL; 298 299 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 300 return error; 301 302 KASSERT(uio->uio_offset >= 0); 303 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 304 uint8_t ch, cmd; 305 const u_int a = uio->uio_offset; 306 cmd = a + dm->dm_nvram_start; 307 if ((error = iic_exec(sc->sc_tag, 308 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 309 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 310 iic_release_bus(sc->sc_tag, 0); 311 aprint_error_dev(sc->sc_dev, 312 "%s: read failed at 0x%x: %d\n", 313 __func__, a, error); 314 return error; 315 } 316 if ((error = uiomove(&ch, 1, uio)) != 0) { 317 iic_release_bus(sc->sc_tag, 0); 318 return error; 319 } 320 } 321 322 iic_release_bus(sc->sc_tag, 0); 323 324 return 0; 325 } 326 327 /*ARGSUSED*/ 328 int 329 dsrtc_write(dev_t dev, struct uio *uio, int flags) 330 { 331 struct dsrtc_softc *sc; 332 int error; 333 334 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 335 return ENXIO; 336 337 const struct dsrtc_model * const dm = &sc->sc_model; 338 if (uio->uio_offset >= dm->dm_nvram_size) 339 return EINVAL; 340 341 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 342 return error; 343 344 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 345 uint8_t cmdbuf[2]; 346 const u_int a = (int)uio->uio_offset; 347 cmdbuf[0] = a + dm->dm_nvram_start; 348 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 349 break; 350 351 if ((error = iic_exec(sc->sc_tag, 352 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 353 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 354 aprint_error_dev(sc->sc_dev, 355 "%s: write failed at 0x%x: %d\n", 356 __func__, a, error); 357 break; 358 } 359 } 360 361 iic_release_bus(sc->sc_tag, 0); 362 363 return error; 364 } 365 366 static int 367 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 368 { 369 struct dsrtc_softc *sc = ch->cookie; 370 struct clock_ymdhms check; 371 int retries; 372 373 memset(dt, 0, sizeof(*dt)); 374 memset(&check, 0, sizeof(check)); 375 376 /* 377 * Since we don't support Burst Read, we have to read the clock twice 378 * until we get two consecutive identical results. 379 */ 380 retries = 5; 381 do { 382 dsrtc_clock_read_ymdhms(sc, dt); 383 dsrtc_clock_read_ymdhms(sc, &check); 384 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 385 386 return 0; 387 } 388 389 static int 390 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 391 { 392 struct dsrtc_softc *sc = ch->cookie; 393 394 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 395 return -1; 396 397 return 0; 398 } 399 400 static int 401 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 402 { 403 struct dsrtc_model * const dm = &sc->sc_model; 404 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 405 int error; 406 407 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 408 409 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 410 aprint_error_dev(sc->sc_dev, 411 "%s: failed to acquire I2C bus: %d\n", 412 __func__, error); 413 return 0; 414 } 415 416 /* Read each RTC register in order. */ 417 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 418 cmdbuf[0] = dm->dm_rtc_start + i; 419 420 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 421 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 422 } 423 424 /* Done with I2C */ 425 iic_release_bus(sc->sc_tag, I2C_F_POLL); 426 427 if (error != 0) { 428 aprint_error_dev(sc->sc_dev, 429 "%s: failed to read rtc at 0x%x: %d\n", 430 __func__, cmdbuf[0], error); 431 return 0; 432 } 433 434 /* 435 * Convert the RTC's register values into something useable 436 */ 437 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 438 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 439 440 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 441 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 442 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 443 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 444 dt->dt_hour += 12; 445 } else 446 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 447 DSXXXX_HOURS_24MASK); 448 449 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 450 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 451 452 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 453 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 454 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 455 dt->dt_year += 100; 456 457 return 1; 458 } 459 460 static int 461 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 462 { 463 struct dsrtc_model * const dm = &sc->sc_model; 464 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 465 int error; 466 467 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 468 469 /* 470 * Convert our time representation into something the DSXXXX 471 * can understand. 472 */ 473 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 474 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 475 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 476 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 477 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 478 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 479 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 480 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 481 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 482 483 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 484 aprint_error_dev(sc->sc_dev, 485 "%s: failed to acquire I2C bus: %d\n", 486 __func__, error); 487 return 0; 488 } 489 490 /* Stop the clock */ 491 cmdbuf[0] = dm->dm_ch_reg; 492 493 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 494 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 495 iic_release_bus(sc->sc_tag, I2C_F_POLL); 496 aprint_error_dev(sc->sc_dev, 497 "%s: failed to read Hold Clock: %d\n", 498 __func__, error); 499 return 0; 500 } 501 502 cmdbuf[1] |= dm->dm_ch_value; 503 504 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 505 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 506 iic_release_bus(sc->sc_tag, I2C_F_POLL); 507 aprint_error_dev(sc->sc_dev, 508 "%s: failed to write Hold Clock: %d\n", 509 __func__, error); 510 return 0; 511 } 512 513 /* 514 * Write registers in reverse order. The last write (to the Seconds 515 * register) will undo the Clock Hold, above. 516 */ 517 uint8_t op = I2C_OP_WRITE; 518 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 519 cmdbuf[0] = dm->dm_rtc_start + i; 520 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 521 op = I2C_OP_WRITE_WITH_STOP; 522 } 523 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 524 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 525 iic_release_bus(sc->sc_tag, I2C_F_POLL); 526 aprint_error_dev(sc->sc_dev, 527 "%s: failed to write rtc at 0x%x: %d\n", 528 __func__, i, error); 529 /* XXX: Clock Hold is likely still asserted! */ 530 return 0; 531 } 532 } 533 /* 534 * If the clock hold register isn't the same register as seconds, 535 * we need to reeanble the clock. 536 */ 537 if (op != I2C_OP_WRITE_WITH_STOP) { 538 cmdbuf[0] = dm->dm_ch_reg; 539 cmdbuf[1] &= ~dm->dm_ch_value; 540 541 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 542 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 543 I2C_F_POLL)) != 0) { 544 iic_release_bus(sc->sc_tag, I2C_F_POLL); 545 aprint_error_dev(sc->sc_dev, 546 "%s: failed to Hold Clock: %d\n", 547 __func__, error); 548 return 0; 549 } 550 } 551 552 iic_release_bus(sc->sc_tag, I2C_F_POLL); 553 554 return 1; 555 } 556 557 static int 558 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 559 { 560 struct dsrtc_softc *sc = ch->cookie; 561 struct timeval check; 562 int retries; 563 564 memset(tv, 0, sizeof(*tv)); 565 memset(&check, 0, sizeof(check)); 566 567 /* 568 * Since we don't support Burst Read, we have to read the clock twice 569 * until we get two consecutive identical results. 570 */ 571 retries = 5; 572 do { 573 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 574 dsrtc_clock_read_timeval(sc, &check.tv_sec); 575 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 576 577 return 0; 578 } 579 580 static int 581 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 582 { 583 struct dsrtc_softc *sc = ch->cookie; 584 585 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 586 return -1; 587 588 return 0; 589 } 590 591 /* 592 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 593 * it, since some I2C controllers don't support anything other than single-byte 594 * transfers. 595 */ 596 static int 597 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 598 { 599 const struct dsrtc_model * const dm = &sc->sc_model; 600 uint8_t buf[4]; 601 int error; 602 603 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 604 aprint_error_dev(sc->sc_dev, 605 "%s: failed to acquire I2C bus: %d\n", 606 __func__, error); 607 return 0; 608 } 609 610 /* read all registers: */ 611 uint8_t reg = dm->dm_rtc_start; 612 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 613 ®, 1, buf, 4, I2C_F_POLL); 614 615 /* Done with I2C */ 616 iic_release_bus(sc->sc_tag, I2C_F_POLL); 617 618 if (error != 0) { 619 aprint_error_dev(sc->sc_dev, 620 "%s: failed to read rtc at 0x%x: %d\n", 621 __func__, reg, error); 622 return 0; 623 } 624 625 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 626 *tp = v; 627 628 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 629 __func__, v); 630 631 return 1; 632 } 633 634 static int 635 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 636 { 637 const struct dsrtc_model * const dm = &sc->sc_model; 638 size_t buflen = dm->dm_rtc_size + 2; 639 uint8_t buf[buflen]; 640 int error; 641 642 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 643 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 644 645 buf[0] = dm->dm_rtc_start; 646 buf[1] = (t >> 0) & 0xff; 647 buf[2] = (t >> 8) & 0xff; 648 buf[3] = (t >> 16) & 0xff; 649 buf[4] = (t >> 24) & 0xff; 650 buf[5] = 0; 651 652 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 653 aprint_error_dev(sc->sc_dev, 654 "%s: failed to acquire I2C bus: %d\n", 655 __func__, error); 656 return 0; 657 } 658 659 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 660 &buf, buflen, NULL, 0, I2C_F_POLL); 661 662 /* Done with I2C */ 663 iic_release_bus(sc->sc_tag, I2C_F_POLL); 664 665 /* send data */ 666 if (error != 0) { 667 aprint_error_dev(sc->sc_dev, 668 "%s: failed to set time: %d\n", 669 __func__, error); 670 return 0; 671 } 672 673 return 1; 674 } 675 676 static int 677 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 678 { 679 int error, tc; 680 uint8_t reg = DS3232_TEMP_MSB; 681 uint8_t buf[2]; 682 683 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 684 return ENOTSUP; 685 686 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 687 aprint_error_dev(sc->sc_dev, 688 "%s: failed to acquire I2C bus: %d\n", 689 __func__, error); 690 return 0; 691 } 692 693 /* read temperature registers: */ 694 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 695 ®, 1, buf, 2, I2C_F_POLL); 696 697 /* Done with I2C */ 698 iic_release_bus(sc->sc_tag, I2C_F_POLL); 699 700 if (error != 0) { 701 aprint_error_dev(sc->sc_dev, 702 "%s: failed to read temperature: %d\n", 703 __func__, error); 704 return 0; 705 } 706 707 /* convert to microkelvin */ 708 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 709 *temp = tc + 273150000; 710 return 1; 711 } 712 713 static void 714 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 715 { 716 struct dsrtc_softc *sc = sme->sme_cookie; 717 uint32_t temp = 0; /* XXX gcc */ 718 719 if (dsrtc_read_temp(sc, &temp) == 0) { 720 edata->state = ENVSYS_SINVALID; 721 return; 722 } 723 724 edata->value_cur = temp; 725 726 edata->state = ENVSYS_SVALID; 727 } 728
Indexes created Thu Oct 02 10:09:58 GMT 2025