ds1307.c revision 1.22.2.1
1 /* $NetBSD: ds1307.c,v 1.22.2.1 2016/11/04 14:49:08 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.22.2.1 2016/11/04 14:49:08 pgoyette Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 struct dsrtc_model { 57 uint16_t dm_model; 58 uint8_t dm_ch_reg; 59 uint8_t dm_ch_value; 60 uint8_t dm_vbaten_reg; 61 uint8_t dm_vbaten_value; 62 uint8_t dm_rtc_start; 63 uint8_t dm_rtc_size; 64 uint8_t dm_nvram_start; 65 uint8_t dm_nvram_size; 66 uint8_t dm_flags; 67 #define DSRTC_FLAG_CLOCK_HOLD 0x01 68 #define DSRTC_FLAG_BCD 0x02 69 #define DSRTC_FLAG_TEMP 0x04 70 #define DSRTC_FLAG_VBATEN 0x08 71 #define DSRTC_FLAG_YEAR_START_2K 0x10 72 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 73 }; 74 75 static const struct dsrtc_model dsrtc_models[] = { 76 { 77 .dm_model = 1307, 78 .dm_ch_reg = DSXXXX_SECONDS, 79 .dm_ch_value = DS1307_SECONDS_CH, 80 .dm_rtc_start = DS1307_RTC_START, 81 .dm_rtc_size = DS1307_RTC_SIZE, 82 .dm_nvram_start = DS1307_NVRAM_START, 83 .dm_nvram_size = DS1307_NVRAM_SIZE, 84 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 85 }, { 86 .dm_model = 1339, 87 .dm_rtc_start = DS1339_RTC_START, 88 .dm_rtc_size = DS1339_RTC_SIZE, 89 .dm_flags = DSRTC_FLAG_BCD, 90 }, { 91 .dm_model = 1340, 92 .dm_ch_reg = DSXXXX_SECONDS, 93 .dm_ch_value = DS1340_SECONDS_EOSC, 94 .dm_rtc_start = DS1340_RTC_START, 95 .dm_rtc_size = DS1340_RTC_SIZE, 96 .dm_flags = DSRTC_FLAG_BCD, 97 }, { 98 .dm_model = 1672, 99 .dm_rtc_start = DS1672_RTC_START, 100 .dm_rtc_size = DS1672_RTC_SIZE, 101 .dm_ch_reg = DS1672_CONTROL, 102 .dm_ch_value = DS1672_CONTROL_CH, 103 .dm_flags = 0, 104 }, { 105 .dm_model = 3231, 106 .dm_rtc_start = DS3232_RTC_START, 107 .dm_rtc_size = DS3232_RTC_SIZE, 108 /* 109 * XXX 110 * the DS3232 likely has the temperature sensor too but I can't 111 * easily verify or test that right now 112 */ 113 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 114 }, { 115 .dm_model = 3232, 116 .dm_rtc_start = DS3232_RTC_START, 117 .dm_rtc_size = DS3232_RTC_SIZE, 118 .dm_nvram_start = DS3232_NVRAM_START, 119 .dm_nvram_size = DS3232_NVRAM_SIZE, 120 .dm_flags = DSRTC_FLAG_BCD, 121 }, { 122 /* MCP7940 */ 123 .dm_model = 7940, 124 .dm_rtc_start = DS1307_RTC_START, 125 .dm_rtc_size = DS1307_RTC_SIZE, 126 .dm_ch_reg = DSXXXX_SECONDS, 127 .dm_ch_value = DS1307_SECONDS_CH, 128 .dm_vbaten_reg = DSXXXX_DAY, 129 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 130 .dm_nvram_start = MCP7940_NVRAM_START, 131 .dm_nvram_size = MCP7940_NVRAM_SIZE, 132 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 133 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 134 }, 135 }; 136 137 struct dsrtc_softc { 138 device_t sc_dev; 139 i2c_tag_t sc_tag; 140 uint8_t sc_address; 141 bool sc_open; 142 struct dsrtc_model sc_model; 143 struct todr_chip_handle sc_todr; 144 struct sysmon_envsys *sc_sme; 145 envsys_data_t sc_sensor; 146 }; 147 148 static void dsrtc_attach(device_t, device_t, void *); 149 static int dsrtc_match(device_t, cfdata_t, void *); 150 151 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 152 dsrtc_match, dsrtc_attach, NULL, NULL); 153 extern struct cfdriver dsrtc_cd; 154 155 dev_type_open(dsrtc_open); 156 dev_type_close(dsrtc_close); 157 dev_type_read(dsrtc_read); 158 dev_type_write(dsrtc_write); 159 160 const struct cdevsw dsrtc_cdevsw = { 161 .d_open = dsrtc_open, 162 .d_close = dsrtc_close, 163 .d_read = dsrtc_read, 164 .d_write = dsrtc_write, 165 .d_ioctl = noioctl, 166 .d_stop = nostop, 167 .d_tty = notty, 168 .d_poll = nopoll, 169 .d_mmap = nommap, 170 .d_kqfilter = nokqfilter, 171 .d_discard = nodiscard, 172 .d_flag = D_OTHER 173 }; 174 175 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 176 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 177 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 178 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 179 180 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 181 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 182 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 183 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 184 185 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 186 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 187 188 static const struct dsrtc_model * 189 dsrtc_model(u_int model) 190 { 191 /* no model given, assume it's a DS1307 (the first one) */ 192 if (model == 0) 193 return &dsrtc_models[0]; 194 195 for (const struct dsrtc_model *dm = dsrtc_models; 196 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 197 if (dm->dm_model == model) 198 return dm; 199 } 200 return NULL; 201 } 202 203 static int 204 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 205 { 206 struct i2c_attach_args *ia = arg; 207 208 if (ia->ia_name) { 209 /* direct config - check name */ 210 if (strcmp(ia->ia_name, "dsrtc") == 0) 211 return 1; 212 } else { 213 /* indirect config - check typical address */ 214 if (ia->ia_addr == DS1307_ADDR || ia->ia_addr == MCP7940_ADDR) 215 return dsrtc_model(cf->cf_flags & 0xffff) != NULL; 216 } 217 return 0; 218 } 219 220 static void 221 dsrtc_attach(device_t parent, device_t self, void *arg) 222 { 223 struct dsrtc_softc *sc = device_private(self); 224 struct i2c_attach_args *ia = arg; 225 const struct dsrtc_model * const dm = 226 dsrtc_model(device_cfdata(self)->cf_flags); 227 228 aprint_naive(": Real-time Clock%s\n", 229 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 230 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 231 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 232 233 sc->sc_tag = ia->ia_tag; 234 sc->sc_address = ia->ia_addr; 235 sc->sc_model = *dm; 236 sc->sc_dev = self; 237 sc->sc_open = 0; 238 sc->sc_todr.cookie = sc; 239 if (dm->dm_flags & DSRTC_FLAG_BCD) { 240 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 241 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 242 } else { 243 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 244 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 245 } 246 sc->sc_todr.todr_setwen = NULL; 247 248 todr_attach(&sc->sc_todr); 249 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 250 int error; 251 252 sc->sc_sme = sysmon_envsys_create(); 253 sc->sc_sme->sme_name = device_xname(self); 254 sc->sc_sme->sme_cookie = sc; 255 sc->sc_sme->sme_refresh = dsrtc_refresh; 256 257 sc->sc_sensor.units = ENVSYS_STEMP; 258 sc->sc_sensor.state = ENVSYS_SINVALID; 259 sc->sc_sensor.flags = 0; 260 (void)strlcpy(sc->sc_sensor.desc, "temperature", 261 sizeof(sc->sc_sensor.desc)); 262 263 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 264 aprint_error_dev(self, "unable to attach sensor\n"); 265 goto bad; 266 } 267 268 error = sysmon_envsys_register(sc->sc_sme); 269 if (error) { 270 aprint_error_dev(self, 271 "error %d registering with sysmon\n", error); 272 goto bad; 273 } 274 } 275 return; 276 bad: 277 sysmon_envsys_destroy(sc->sc_sme); 278 } 279 280 /*ARGSUSED*/ 281 int 282 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 283 { 284 struct dsrtc_softc *sc; 285 286 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 287 return ENXIO; 288 289 /* XXX: Locking */ 290 if (sc->sc_open) 291 return EBUSY; 292 293 sc->sc_open = true; 294 return 0; 295 } 296 297 /*ARGSUSED*/ 298 int 299 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 300 { 301 struct dsrtc_softc *sc; 302 303 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 304 return ENXIO; 305 306 sc->sc_open = false; 307 return 0; 308 } 309 310 /*ARGSUSED*/ 311 int 312 dsrtc_read(dev_t dev, struct uio *uio, int flags) 313 { 314 struct dsrtc_softc *sc; 315 int error; 316 317 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 318 return ENXIO; 319 320 const struct dsrtc_model * const dm = &sc->sc_model; 321 if (uio->uio_offset >= dm->dm_nvram_size) 322 return EINVAL; 323 324 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 325 return error; 326 327 KASSERT(uio->uio_offset >= 0); 328 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 329 uint8_t ch, cmd; 330 const u_int a = uio->uio_offset; 331 cmd = a + dm->dm_nvram_start; 332 if ((error = iic_exec(sc->sc_tag, 333 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 334 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 335 iic_release_bus(sc->sc_tag, 0); 336 aprint_error_dev(sc->sc_dev, 337 "%s: read failed at 0x%x: %d\n", 338 __func__, a, error); 339 return error; 340 } 341 if ((error = uiomove(&ch, 1, uio)) != 0) { 342 iic_release_bus(sc->sc_tag, 0); 343 return error; 344 } 345 } 346 347 iic_release_bus(sc->sc_tag, 0); 348 349 return 0; 350 } 351 352 /*ARGSUSED*/ 353 int 354 dsrtc_write(dev_t dev, struct uio *uio, int flags) 355 { 356 struct dsrtc_softc *sc; 357 int error; 358 359 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 360 return ENXIO; 361 362 const struct dsrtc_model * const dm = &sc->sc_model; 363 if (uio->uio_offset >= dm->dm_nvram_size) 364 return EINVAL; 365 366 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 367 return error; 368 369 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 370 uint8_t cmdbuf[2]; 371 const u_int a = (int)uio->uio_offset; 372 cmdbuf[0] = a + dm->dm_nvram_start; 373 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 374 break; 375 376 if ((error = iic_exec(sc->sc_tag, 377 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 378 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 379 aprint_error_dev(sc->sc_dev, 380 "%s: write failed at 0x%x: %d\n", 381 __func__, a, error); 382 break; 383 } 384 } 385 386 iic_release_bus(sc->sc_tag, 0); 387 388 return error; 389 } 390 391 static int 392 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 393 { 394 struct dsrtc_softc *sc = ch->cookie; 395 struct clock_ymdhms check; 396 int retries; 397 398 memset(dt, 0, sizeof(*dt)); 399 memset(&check, 0, sizeof(check)); 400 401 /* 402 * Since we don't support Burst Read, we have to read the clock twice 403 * until we get two consecutive identical results. 404 */ 405 retries = 5; 406 do { 407 dsrtc_clock_read_ymdhms(sc, dt); 408 dsrtc_clock_read_ymdhms(sc, &check); 409 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 410 411 return 0; 412 } 413 414 static int 415 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 416 { 417 struct dsrtc_softc *sc = ch->cookie; 418 419 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 420 return -1; 421 422 return 0; 423 } 424 425 static int 426 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 427 { 428 struct dsrtc_model * const dm = &sc->sc_model; 429 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 430 int error; 431 432 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 433 434 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 435 aprint_error_dev(sc->sc_dev, 436 "%s: failed to acquire I2C bus: %d\n", 437 __func__, error); 438 return 0; 439 } 440 441 /* Read each RTC register in order. */ 442 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 443 cmdbuf[0] = dm->dm_rtc_start + i; 444 445 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 446 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 447 } 448 449 /* Done with I2C */ 450 iic_release_bus(sc->sc_tag, I2C_F_POLL); 451 452 if (error != 0) { 453 aprint_error_dev(sc->sc_dev, 454 "%s: failed to read rtc at 0x%x: %d\n", 455 __func__, cmdbuf[0], error); 456 return 0; 457 } 458 459 /* 460 * Convert the RTC's register values into something useable 461 */ 462 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 463 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 464 465 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 466 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 467 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 468 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 469 dt->dt_hour += 12; 470 } else 471 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 472 DSXXXX_HOURS_24MASK); 473 474 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 475 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 476 477 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 478 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 479 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 480 else { 481 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 482 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 483 dt->dt_year += 100; 484 } 485 486 return 1; 487 } 488 489 static int 490 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 491 { 492 struct dsrtc_model * const dm = &sc->sc_model; 493 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 494 int error; 495 496 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 497 498 /* 499 * Convert our time representation into something the DSXXXX 500 * can understand. 501 */ 502 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 503 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 504 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 505 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 506 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 507 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 508 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 509 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 510 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 511 512 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 513 aprint_error_dev(sc->sc_dev, 514 "%s: failed to acquire I2C bus: %d\n", 515 __func__, error); 516 return 0; 517 } 518 519 /* Stop the clock */ 520 cmdbuf[0] = dm->dm_ch_reg; 521 522 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 523 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 524 iic_release_bus(sc->sc_tag, I2C_F_POLL); 525 aprint_error_dev(sc->sc_dev, 526 "%s: failed to read Hold Clock: %d\n", 527 __func__, error); 528 return 0; 529 } 530 531 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 532 cmdbuf[1] &= ~dm->dm_ch_value; 533 else 534 cmdbuf[1] |= dm->dm_ch_value; 535 536 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 537 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 538 iic_release_bus(sc->sc_tag, I2C_F_POLL); 539 aprint_error_dev(sc->sc_dev, 540 "%s: failed to write Hold Clock: %d\n", 541 __func__, error); 542 return 0; 543 } 544 545 /* 546 * Write registers in reverse order. The last write (to the Seconds 547 * register) will undo the Clock Hold, above. 548 */ 549 uint8_t op = I2C_OP_WRITE; 550 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 551 cmdbuf[0] = dm->dm_rtc_start + i; 552 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 553 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 554 bcd[i] |= dm->dm_vbaten_value; 555 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 556 op = I2C_OP_WRITE_WITH_STOP; 557 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 558 bcd[i] |= dm->dm_ch_value; 559 } 560 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 561 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 562 iic_release_bus(sc->sc_tag, I2C_F_POLL); 563 aprint_error_dev(sc->sc_dev, 564 "%s: failed to write rtc at 0x%x: %d\n", 565 __func__, i, error); 566 /* XXX: Clock Hold is likely still asserted! */ 567 return 0; 568 } 569 } 570 /* 571 * If the clock hold register isn't the same register as seconds, 572 * we need to reeanble the clock. 573 */ 574 if (op != I2C_OP_WRITE_WITH_STOP) { 575 cmdbuf[0] = dm->dm_ch_reg; 576 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 577 cmdbuf[1] |= dm->dm_ch_value; 578 else 579 cmdbuf[1] &= ~dm->dm_ch_value; 580 581 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 582 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 583 I2C_F_POLL)) != 0) { 584 iic_release_bus(sc->sc_tag, I2C_F_POLL); 585 aprint_error_dev(sc->sc_dev, 586 "%s: failed to Hold Clock: %d\n", 587 __func__, error); 588 return 0; 589 } 590 } 591 592 iic_release_bus(sc->sc_tag, I2C_F_POLL); 593 594 return 1; 595 } 596 597 static int 598 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 599 { 600 struct dsrtc_softc *sc = ch->cookie; 601 struct timeval check; 602 int retries; 603 604 memset(tv, 0, sizeof(*tv)); 605 memset(&check, 0, sizeof(check)); 606 607 /* 608 * Since we don't support Burst Read, we have to read the clock twice 609 * until we get two consecutive identical results. 610 */ 611 retries = 5; 612 do { 613 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 614 dsrtc_clock_read_timeval(sc, &check.tv_sec); 615 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 616 617 return 0; 618 } 619 620 static int 621 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 622 { 623 struct dsrtc_softc *sc = ch->cookie; 624 625 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 626 return -1; 627 628 return 0; 629 } 630 631 /* 632 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 633 * it, since some I2C controllers don't support anything other than single-byte 634 * transfers. 635 */ 636 static int 637 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 638 { 639 const struct dsrtc_model * const dm = &sc->sc_model; 640 uint8_t buf[4]; 641 int error; 642 643 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 644 aprint_error_dev(sc->sc_dev, 645 "%s: failed to acquire I2C bus: %d\n", 646 __func__, error); 647 return 0; 648 } 649 650 /* read all registers: */ 651 uint8_t reg = dm->dm_rtc_start; 652 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 653 ®, 1, buf, 4, I2C_F_POLL); 654 655 /* Done with I2C */ 656 iic_release_bus(sc->sc_tag, I2C_F_POLL); 657 658 if (error != 0) { 659 aprint_error_dev(sc->sc_dev, 660 "%s: failed to read rtc at 0x%x: %d\n", 661 __func__, reg, error); 662 return 0; 663 } 664 665 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 666 *tp = v; 667 668 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 669 __func__, v); 670 671 return 1; 672 } 673 674 static int 675 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 676 { 677 const struct dsrtc_model * const dm = &sc->sc_model; 678 size_t buflen = dm->dm_rtc_size + 2; 679 uint8_t buf[buflen]; 680 int error; 681 682 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 683 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 684 685 buf[0] = dm->dm_rtc_start; 686 buf[1] = (t >> 0) & 0xff; 687 buf[2] = (t >> 8) & 0xff; 688 buf[3] = (t >> 16) & 0xff; 689 buf[4] = (t >> 24) & 0xff; 690 buf[5] = 0; 691 692 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 693 aprint_error_dev(sc->sc_dev, 694 "%s: failed to acquire I2C bus: %d\n", 695 __func__, error); 696 return 0; 697 } 698 699 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 700 &buf, buflen, NULL, 0, I2C_F_POLL); 701 702 /* Done with I2C */ 703 iic_release_bus(sc->sc_tag, I2C_F_POLL); 704 705 /* send data */ 706 if (error != 0) { 707 aprint_error_dev(sc->sc_dev, 708 "%s: failed to set time: %d\n", 709 __func__, error); 710 return 0; 711 } 712 713 return 1; 714 } 715 716 static int 717 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 718 { 719 int error, tc; 720 uint8_t reg = DS3232_TEMP_MSB; 721 uint8_t buf[2]; 722 723 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 724 return ENOTSUP; 725 726 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 727 aprint_error_dev(sc->sc_dev, 728 "%s: failed to acquire I2C bus: %d\n", 729 __func__, error); 730 return 0; 731 } 732 733 /* read temperature registers: */ 734 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 735 ®, 1, buf, 2, I2C_F_POLL); 736 737 /* Done with I2C */ 738 iic_release_bus(sc->sc_tag, I2C_F_POLL); 739 740 if (error != 0) { 741 aprint_error_dev(sc->sc_dev, 742 "%s: failed to read temperature: %d\n", 743 __func__, error); 744 return 0; 745 } 746 747 /* convert to microkelvin */ 748 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 749 *temp = tc + 273150000; 750 return 1; 751 } 752 753 static void 754 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 755 { 756 struct dsrtc_softc *sc = sme->sme_cookie; 757 uint32_t temp = 0; /* XXX gcc */ 758 759 if (dsrtc_read_temp(sc, &temp) == 0) { 760 edata->state = ENVSYS_SINVALID; 761 return; 762 } 763 764 edata->value_cur = temp; 765 766 edata->state = ENVSYS_SVALID; 767 } 768
Indexes created Thu Oct 02 14:10:14 GMT 2025