ds1307.c revision 1.25.2.2
1 /* $NetBSD: ds1307.c,v 1.25.2.2 2018/07/28 04:37:44 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.25.2.2 2018/07/28 04:37:44 pgoyette Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 58 struct dsrtc_model { 59 const i2c_addr_t *dm_valid_addrs; 60 uint16_t dm_model; 61 uint8_t dm_ch_reg; 62 uint8_t dm_ch_value; 63 uint8_t dm_vbaten_reg; 64 uint8_t dm_vbaten_value; 65 uint8_t dm_rtc_start; 66 uint8_t dm_rtc_size; 67 uint8_t dm_nvram_start; 68 uint8_t dm_nvram_size; 69 uint8_t dm_flags; 70 #define DSRTC_FLAG_CLOCK_HOLD 0x01 71 #define DSRTC_FLAG_BCD 0x02 72 #define DSRTC_FLAG_TEMP 0x04 73 #define DSRTC_FLAG_VBATEN 0x08 74 #define DSRTC_FLAG_YEAR_START_2K 0x10 75 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 76 }; 77 78 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 79 static const struct dsrtc_model ds1307_model = { 80 .dm_valid_addrs = ds1307_valid_addrs, 81 .dm_model = 1307, 82 .dm_ch_reg = DSXXXX_SECONDS, 83 .dm_ch_value = DS1307_SECONDS_CH, 84 .dm_rtc_start = DS1307_RTC_START, 85 .dm_rtc_size = DS1307_RTC_SIZE, 86 .dm_nvram_start = DS1307_NVRAM_START, 87 .dm_nvram_size = DS1307_NVRAM_SIZE, 88 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 89 }; 90 91 static const struct dsrtc_model ds1339_model = { 92 .dm_valid_addrs = ds1307_valid_addrs, 93 .dm_model = 1339, 94 .dm_rtc_start = DS1339_RTC_START, 95 .dm_rtc_size = DS1339_RTC_SIZE, 96 .dm_flags = DSRTC_FLAG_BCD, 97 }; 98 99 static const struct dsrtc_model ds1340_model = { 100 .dm_valid_addrs = ds1307_valid_addrs, 101 .dm_model = 1340, 102 .dm_ch_reg = DSXXXX_SECONDS, 103 .dm_ch_value = DS1340_SECONDS_EOSC, 104 .dm_rtc_start = DS1340_RTC_START, 105 .dm_rtc_size = DS1340_RTC_SIZE, 106 .dm_flags = DSRTC_FLAG_BCD, 107 }; 108 109 static const struct dsrtc_model ds1672_model = { 110 .dm_valid_addrs = ds1307_valid_addrs, 111 .dm_model = 1672, 112 .dm_rtc_start = DS1672_RTC_START, 113 .dm_rtc_size = DS1672_RTC_SIZE, 114 .dm_ch_reg = DS1672_CONTROL, 115 .dm_ch_value = DS1672_CONTROL_CH, 116 .dm_flags = 0, 117 }; 118 119 static const struct dsrtc_model ds3231_model = { 120 .dm_valid_addrs = ds1307_valid_addrs, 121 .dm_model = 3231, 122 .dm_rtc_start = DS3232_RTC_START, 123 .dm_rtc_size = DS3232_RTC_SIZE, 124 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 125 }; 126 127 static const struct dsrtc_model ds3232_model = { 128 .dm_valid_addrs = ds1307_valid_addrs, 129 .dm_model = 3232, 130 .dm_rtc_start = DS3232_RTC_START, 131 .dm_rtc_size = DS3232_RTC_SIZE, 132 .dm_nvram_start = DS3232_NVRAM_START, 133 .dm_nvram_size = DS3232_NVRAM_SIZE, 134 /* 135 * XXX 136 * the DS3232 likely has the temperature sensor too but I can't 137 * easily verify or test that right now 138 */ 139 .dm_flags = DSRTC_FLAG_BCD, 140 }; 141 142 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 143 static const struct dsrtc_model mcp7940_model = { 144 .dm_valid_addrs = mcp7940_valid_addrs, 145 .dm_model = 7940, 146 .dm_rtc_start = DS1307_RTC_START, 147 .dm_rtc_size = DS1307_RTC_SIZE, 148 .dm_ch_reg = DSXXXX_SECONDS, 149 .dm_ch_value = DS1307_SECONDS_CH, 150 .dm_vbaten_reg = DSXXXX_DAY, 151 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 152 .dm_nvram_start = MCP7940_NVRAM_START, 153 .dm_nvram_size = MCP7940_NVRAM_SIZE, 154 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 155 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 156 }; 157 158 static const struct device_compatible_entry compat_data[] = { 159 { "dallas,ds1307", (uintptr_t)&ds1307_model }, 160 { "maxim,ds1307", (uintptr_t)&ds1307_model }, 161 162 { "dallas,ds1339", (uintptr_t)&ds1339_model }, 163 { "maxim,ds1339", (uintptr_t)&ds1339_model }, 164 165 { "dallas,ds1340", (uintptr_t)&ds1340_model }, 166 { "maxim,ds1340", (uintptr_t)&ds1340_model }, 167 168 { "dallas,ds1672", (uintptr_t)&ds1672_model }, 169 { "maxim,ds1672", (uintptr_t)&ds1672_model }, 170 171 { "dallas,ds3231", (uintptr_t)&ds3231_model }, 172 { "maxim,ds3231", (uintptr_t)&ds3231_model }, 173 174 { "dallas,ds3232", (uintptr_t)&ds3232_model }, 175 { "maxim,ds3232", (uintptr_t)&ds3232_model }, 176 177 { "microchip,mcp7940", (uintptr_t)&mcp7940_model }, 178 179 { NULL, 0 } 180 }; 181 182 struct dsrtc_softc { 183 device_t sc_dev; 184 i2c_tag_t sc_tag; 185 uint8_t sc_address; 186 bool sc_open; 187 struct dsrtc_model sc_model; 188 struct todr_chip_handle sc_todr; 189 struct sysmon_envsys *sc_sme; 190 envsys_data_t sc_sensor; 191 }; 192 193 static void dsrtc_attach(device_t, device_t, void *); 194 static int dsrtc_match(device_t, cfdata_t, void *); 195 196 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 197 dsrtc_match, dsrtc_attach, NULL, NULL); 198 199 dev_type_open(dsrtc_open); 200 dev_type_close(dsrtc_close); 201 dev_type_read(dsrtc_read); 202 dev_type_write(dsrtc_write); 203 204 const struct cdevsw dsrtc_cdevsw = { 205 .d_open = dsrtc_open, 206 .d_close = dsrtc_close, 207 .d_read = dsrtc_read, 208 .d_write = dsrtc_write, 209 .d_ioctl = noioctl, 210 .d_stop = nostop, 211 .d_tty = notty, 212 .d_poll = nopoll, 213 .d_mmap = nommap, 214 .d_kqfilter = nokqfilter, 215 .d_discard = nodiscard, 216 .d_flag = D_OTHER 217 }; 218 219 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 220 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 221 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 222 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 223 224 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 225 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 226 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 227 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 228 229 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 230 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 231 232 static const struct dsrtc_model * 233 dsrtc_model_by_number(u_int model) 234 { 235 const struct device_compatible_entry *dce; 236 const struct dsrtc_model *dm; 237 238 /* no model given, assume it's a DS1307 */ 239 if (model == 0) 240 return &ds1307_model; 241 242 for (dce = compat_data; dce->compat != NULL; dce++) { 243 dm = (void *)dce->data; 244 if (dm->dm_model == model) 245 return dm; 246 } 247 return NULL; 248 } 249 250 static const struct dsrtc_model * 251 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 252 { 253 const struct dsrtc_model *dm = NULL; 254 const struct device_compatible_entry *dce; 255 256 if (iic_compatible_match(ia, compat_data, &dce)) 257 dm = (void *)dce->data; 258 259 return dm; 260 } 261 262 static bool 263 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 264 { 265 266 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 267 if (addr == dm->dm_valid_addrs[i]) 268 return true; 269 } 270 return false; 271 } 272 273 static int 274 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 275 { 276 struct i2c_attach_args *ia = arg; 277 const struct dsrtc_model *dm; 278 int match_result; 279 280 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 281 return match_result; 282 283 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 284 if (dm == NULL) 285 return 0; 286 287 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 288 return I2C_MATCH_ADDRESS_ONLY; 289 290 return 0; 291 } 292 293 static void 294 dsrtc_attach(device_t parent, device_t self, void *arg) 295 { 296 struct dsrtc_softc *sc = device_private(self); 297 struct i2c_attach_args *ia = arg; 298 const struct dsrtc_model *dm; 299 300 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 301 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 302 303 if (dm == NULL) { 304 aprint_error(": unable to determine model!\n"); 305 return; 306 } 307 308 aprint_naive(": Real-time Clock%s\n", 309 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 310 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 311 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 312 313 sc->sc_tag = ia->ia_tag; 314 sc->sc_address = ia->ia_addr; 315 sc->sc_model = *dm; 316 sc->sc_dev = self; 317 sc->sc_open = 0; 318 sc->sc_todr.cookie = sc; 319 if (dm->dm_flags & DSRTC_FLAG_BCD) { 320 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 321 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 322 } else { 323 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 324 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 325 } 326 sc->sc_todr.todr_setwen = NULL; 327 328 todr_attach(&sc->sc_todr); 329 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 330 int error; 331 332 sc->sc_sme = sysmon_envsys_create(); 333 sc->sc_sme->sme_name = device_xname(self); 334 sc->sc_sme->sme_cookie = sc; 335 sc->sc_sme->sme_refresh = dsrtc_refresh; 336 337 sc->sc_sensor.units = ENVSYS_STEMP; 338 sc->sc_sensor.state = ENVSYS_SINVALID; 339 sc->sc_sensor.flags = 0; 340 (void)strlcpy(sc->sc_sensor.desc, "temperature", 341 sizeof(sc->sc_sensor.desc)); 342 343 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 344 aprint_error_dev(self, "unable to attach sensor\n"); 345 goto bad; 346 } 347 348 error = sysmon_envsys_register(sc->sc_sme); 349 if (error) { 350 aprint_error_dev(self, 351 "error %d registering with sysmon\n", error); 352 goto bad; 353 } 354 } 355 return; 356 bad: 357 sysmon_envsys_destroy(sc->sc_sme); 358 } 359 360 /*ARGSUSED*/ 361 int 362 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 363 { 364 struct dsrtc_softc *sc; 365 366 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 367 return ENXIO; 368 369 /* XXX: Locking */ 370 if (sc->sc_open) 371 return EBUSY; 372 373 sc->sc_open = true; 374 return 0; 375 } 376 377 /*ARGSUSED*/ 378 int 379 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 380 { 381 struct dsrtc_softc *sc; 382 383 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 384 return ENXIO; 385 386 sc->sc_open = false; 387 return 0; 388 } 389 390 /*ARGSUSED*/ 391 int 392 dsrtc_read(dev_t dev, struct uio *uio, int flags) 393 { 394 struct dsrtc_softc *sc; 395 int error; 396 397 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 398 return ENXIO; 399 400 const struct dsrtc_model * const dm = &sc->sc_model; 401 if (uio->uio_offset >= dm->dm_nvram_size) 402 return EINVAL; 403 404 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 405 return error; 406 407 KASSERT(uio->uio_offset >= 0); 408 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 409 uint8_t ch, cmd; 410 const u_int a = uio->uio_offset; 411 cmd = a + dm->dm_nvram_start; 412 if ((error = iic_exec(sc->sc_tag, 413 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 414 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 415 iic_release_bus(sc->sc_tag, 0); 416 aprint_error_dev(sc->sc_dev, 417 "%s: read failed at 0x%x: %d\n", 418 __func__, a, error); 419 return error; 420 } 421 if ((error = uiomove(&ch, 1, uio)) != 0) { 422 iic_release_bus(sc->sc_tag, 0); 423 return error; 424 } 425 } 426 427 iic_release_bus(sc->sc_tag, 0); 428 429 return 0; 430 } 431 432 /*ARGSUSED*/ 433 int 434 dsrtc_write(dev_t dev, struct uio *uio, int flags) 435 { 436 struct dsrtc_softc *sc; 437 int error; 438 439 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 440 return ENXIO; 441 442 const struct dsrtc_model * const dm = &sc->sc_model; 443 if (uio->uio_offset >= dm->dm_nvram_size) 444 return EINVAL; 445 446 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 447 return error; 448 449 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 450 uint8_t cmdbuf[2]; 451 const u_int a = (int)uio->uio_offset; 452 cmdbuf[0] = a + dm->dm_nvram_start; 453 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 454 break; 455 456 if ((error = iic_exec(sc->sc_tag, 457 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 458 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 459 aprint_error_dev(sc->sc_dev, 460 "%s: write failed at 0x%x: %d\n", 461 __func__, a, error); 462 break; 463 } 464 } 465 466 iic_release_bus(sc->sc_tag, 0); 467 468 return error; 469 } 470 471 static int 472 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 473 { 474 struct dsrtc_softc *sc = ch->cookie; 475 struct clock_ymdhms check; 476 int retries; 477 478 memset(dt, 0, sizeof(*dt)); 479 memset(&check, 0, sizeof(check)); 480 481 /* 482 * Since we don't support Burst Read, we have to read the clock twice 483 * until we get two consecutive identical results. 484 */ 485 retries = 5; 486 do { 487 dsrtc_clock_read_ymdhms(sc, dt); 488 dsrtc_clock_read_ymdhms(sc, &check); 489 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 490 491 return 0; 492 } 493 494 static int 495 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 496 { 497 struct dsrtc_softc *sc = ch->cookie; 498 499 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 500 return -1; 501 502 return 0; 503 } 504 505 static int 506 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 507 { 508 struct dsrtc_model * const dm = &sc->sc_model; 509 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 510 int error; 511 512 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 513 514 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 515 aprint_error_dev(sc->sc_dev, 516 "%s: failed to acquire I2C bus: %d\n", 517 __func__, error); 518 return 0; 519 } 520 521 /* Read each RTC register in order. */ 522 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 523 cmdbuf[0] = dm->dm_rtc_start + i; 524 525 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 526 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 527 } 528 529 /* Done with I2C */ 530 iic_release_bus(sc->sc_tag, I2C_F_POLL); 531 532 if (error != 0) { 533 aprint_error_dev(sc->sc_dev, 534 "%s: failed to read rtc at 0x%x: %d\n", 535 __func__, cmdbuf[0], error); 536 return 0; 537 } 538 539 /* 540 * Convert the RTC's register values into something useable 541 */ 542 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 543 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 544 545 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 546 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 547 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 548 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 549 dt->dt_hour += 12; 550 } else 551 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 552 DSXXXX_HOURS_24MASK); 553 554 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 555 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 556 557 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 558 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 559 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 560 else { 561 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 562 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 563 dt->dt_year += 100; 564 } 565 566 return 1; 567 } 568 569 static int 570 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 571 { 572 struct dsrtc_model * const dm = &sc->sc_model; 573 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 574 int error; 575 576 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 577 578 /* 579 * Convert our time representation into something the DSXXXX 580 * can understand. 581 */ 582 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 583 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 584 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 585 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 586 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 587 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 588 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 589 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 590 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 591 592 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 593 aprint_error_dev(sc->sc_dev, 594 "%s: failed to acquire I2C bus: %d\n", 595 __func__, error); 596 return 0; 597 } 598 599 /* Stop the clock */ 600 cmdbuf[0] = dm->dm_ch_reg; 601 602 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 603 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 604 iic_release_bus(sc->sc_tag, I2C_F_POLL); 605 aprint_error_dev(sc->sc_dev, 606 "%s: failed to read Hold Clock: %d\n", 607 __func__, error); 608 return 0; 609 } 610 611 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 612 cmdbuf[1] &= ~dm->dm_ch_value; 613 else 614 cmdbuf[1] |= dm->dm_ch_value; 615 616 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 617 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 618 iic_release_bus(sc->sc_tag, I2C_F_POLL); 619 aprint_error_dev(sc->sc_dev, 620 "%s: failed to write Hold Clock: %d\n", 621 __func__, error); 622 return 0; 623 } 624 625 /* 626 * Write registers in reverse order. The last write (to the Seconds 627 * register) will undo the Clock Hold, above. 628 */ 629 uint8_t op = I2C_OP_WRITE; 630 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 631 cmdbuf[0] = dm->dm_rtc_start + i; 632 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 633 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 634 bcd[i] |= dm->dm_vbaten_value; 635 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 636 op = I2C_OP_WRITE_WITH_STOP; 637 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 638 bcd[i] |= dm->dm_ch_value; 639 } 640 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 641 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 642 iic_release_bus(sc->sc_tag, I2C_F_POLL); 643 aprint_error_dev(sc->sc_dev, 644 "%s: failed to write rtc at 0x%x: %d\n", 645 __func__, i, error); 646 /* XXX: Clock Hold is likely still asserted! */ 647 return 0; 648 } 649 } 650 /* 651 * If the clock hold register isn't the same register as seconds, 652 * we need to reeanble the clock. 653 */ 654 if (op != I2C_OP_WRITE_WITH_STOP) { 655 cmdbuf[0] = dm->dm_ch_reg; 656 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 657 cmdbuf[1] |= dm->dm_ch_value; 658 else 659 cmdbuf[1] &= ~dm->dm_ch_value; 660 661 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 662 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 663 I2C_F_POLL)) != 0) { 664 iic_release_bus(sc->sc_tag, I2C_F_POLL); 665 aprint_error_dev(sc->sc_dev, 666 "%s: failed to Hold Clock: %d\n", 667 __func__, error); 668 return 0; 669 } 670 } 671 672 iic_release_bus(sc->sc_tag, I2C_F_POLL); 673 674 return 1; 675 } 676 677 static int 678 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 679 { 680 struct dsrtc_softc *sc = ch->cookie; 681 struct timeval check; 682 int retries; 683 684 memset(tv, 0, sizeof(*tv)); 685 memset(&check, 0, sizeof(check)); 686 687 /* 688 * Since we don't support Burst Read, we have to read the clock twice 689 * until we get two consecutive identical results. 690 */ 691 retries = 5; 692 do { 693 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 694 dsrtc_clock_read_timeval(sc, &check.tv_sec); 695 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 696 697 return 0; 698 } 699 700 static int 701 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 702 { 703 struct dsrtc_softc *sc = ch->cookie; 704 705 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 706 return -1; 707 708 return 0; 709 } 710 711 /* 712 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 713 * it, since some I2C controllers don't support anything other than single-byte 714 * transfers. 715 */ 716 static int 717 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 718 { 719 const struct dsrtc_model * const dm = &sc->sc_model; 720 uint8_t buf[4]; 721 int error; 722 723 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 724 aprint_error_dev(sc->sc_dev, 725 "%s: failed to acquire I2C bus: %d\n", 726 __func__, error); 727 return 0; 728 } 729 730 /* read all registers: */ 731 uint8_t reg = dm->dm_rtc_start; 732 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 733 ®, 1, buf, 4, I2C_F_POLL); 734 735 /* Done with I2C */ 736 iic_release_bus(sc->sc_tag, I2C_F_POLL); 737 738 if (error != 0) { 739 aprint_error_dev(sc->sc_dev, 740 "%s: failed to read rtc at 0x%x: %d\n", 741 __func__, reg, error); 742 return 0; 743 } 744 745 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 746 *tp = v; 747 748 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 749 __func__, v); 750 751 return 1; 752 } 753 754 static int 755 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 756 { 757 const struct dsrtc_model * const dm = &sc->sc_model; 758 size_t buflen = dm->dm_rtc_size + 2; 759 uint8_t buf[buflen]; 760 int error; 761 762 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 763 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 764 765 buf[0] = dm->dm_rtc_start; 766 buf[1] = (t >> 0) & 0xff; 767 buf[2] = (t >> 8) & 0xff; 768 buf[3] = (t >> 16) & 0xff; 769 buf[4] = (t >> 24) & 0xff; 770 buf[5] = 0; 771 772 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 773 aprint_error_dev(sc->sc_dev, 774 "%s: failed to acquire I2C bus: %d\n", 775 __func__, error); 776 return 0; 777 } 778 779 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 780 &buf, buflen, NULL, 0, I2C_F_POLL); 781 782 /* Done with I2C */ 783 iic_release_bus(sc->sc_tag, I2C_F_POLL); 784 785 /* send data */ 786 if (error != 0) { 787 aprint_error_dev(sc->sc_dev, 788 "%s: failed to set time: %d\n", 789 __func__, error); 790 return 0; 791 } 792 793 return 1; 794 } 795 796 static int 797 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 798 { 799 int error, tc; 800 uint8_t reg = DS3232_TEMP_MSB; 801 uint8_t buf[2]; 802 803 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 804 return ENOTSUP; 805 806 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 807 aprint_error_dev(sc->sc_dev, 808 "%s: failed to acquire I2C bus: %d\n", 809 __func__, error); 810 return 0; 811 } 812 813 /* read temperature registers: */ 814 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 815 ®, 1, buf, 2, I2C_F_POLL); 816 817 /* Done with I2C */ 818 iic_release_bus(sc->sc_tag, I2C_F_POLL); 819 820 if (error != 0) { 821 aprint_error_dev(sc->sc_dev, 822 "%s: failed to read temperature: %d\n", 823 __func__, error); 824 return 0; 825 } 826 827 /* convert to microkelvin */ 828 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 829 *temp = tc + 273150000; 830 return 1; 831 } 832 833 static void 834 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 835 { 836 struct dsrtc_softc *sc = sme->sme_cookie; 837 uint32_t temp = 0; /* XXX gcc */ 838 839 if (dsrtc_read_temp(sc, &temp) == 0) { 840 edata->state = ENVSYS_SINVALID; 841 return; 842 } 843 844 edata->value_cur = temp; 845 846 edata->state = ENVSYS_SVALID; 847 } 848
Indexes created Thu Oct 02 10:09:58 GMT 2025