ds1307.c revision 1.26
1 /* $NetBSD: ds1307.c,v 1.26 2018/06/16 21:28:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.26 2018/06/16 21:28:07 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 58 struct dsrtc_model { 59 const char **dm_compats; 60 const i2c_addr_t *dm_valid_addrs; 61 uint16_t dm_model; 62 uint8_t dm_ch_reg; 63 uint8_t dm_ch_value; 64 uint8_t dm_vbaten_reg; 65 uint8_t dm_vbaten_value; 66 uint8_t dm_rtc_start; 67 uint8_t dm_rtc_size; 68 uint8_t dm_nvram_start; 69 uint8_t dm_nvram_size; 70 uint8_t dm_flags; 71 #define DSRTC_FLAG_CLOCK_HOLD 0x01 72 #define DSRTC_FLAG_BCD 0x02 73 #define DSRTC_FLAG_TEMP 0x04 74 #define DSRTC_FLAG_VBATEN 0x08 75 #define DSRTC_FLAG_YEAR_START_2K 0x10 76 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 77 }; 78 79 static const char *ds1307_compats[] = { "dallas,ds1307", "maxim,ds1307", NULL }; 80 static const char *ds1339_compats[] = { "dallas,ds1339", "maxim,ds1339", NULL }; 81 static const char *ds1340_compats[] = { "dallas,ds1340", "maxim,ds1340", NULL }; 82 static const char *ds1672_compats[] = { "dallas,ds1672", "maxim,ds1672", NULL }; 83 static const char *ds3231_compats[] = { "dallas,ds3231", "maxim,ds3231", NULL }; 84 static const char *ds3232_compats[] = { "dallas,ds3232", "maxim,ds3232", NULL }; 85 86 /* XXX vendor prefix */ 87 static const char *mcp7940_compats[] = { "microchip,mcp7940", NULL }; 88 89 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 90 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 91 92 static const struct dsrtc_model dsrtc_models[] = { 93 { 94 .dm_compats = ds1307_compats, 95 .dm_valid_addrs = ds1307_valid_addrs, 96 .dm_model = 1307, 97 .dm_ch_reg = DSXXXX_SECONDS, 98 .dm_ch_value = DS1307_SECONDS_CH, 99 .dm_rtc_start = DS1307_RTC_START, 100 .dm_rtc_size = DS1307_RTC_SIZE, 101 .dm_nvram_start = DS1307_NVRAM_START, 102 .dm_nvram_size = DS1307_NVRAM_SIZE, 103 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 104 }, { 105 .dm_compats = ds1339_compats, 106 .dm_valid_addrs = ds1307_valid_addrs, 107 .dm_model = 1339, 108 .dm_rtc_start = DS1339_RTC_START, 109 .dm_rtc_size = DS1339_RTC_SIZE, 110 .dm_flags = DSRTC_FLAG_BCD, 111 }, { 112 .dm_compats = ds1340_compats, 113 .dm_valid_addrs = ds1307_valid_addrs, 114 .dm_model = 1340, 115 .dm_ch_reg = DSXXXX_SECONDS, 116 .dm_ch_value = DS1340_SECONDS_EOSC, 117 .dm_rtc_start = DS1340_RTC_START, 118 .dm_rtc_size = DS1340_RTC_SIZE, 119 .dm_flags = DSRTC_FLAG_BCD, 120 }, { 121 .dm_compats = ds1672_compats, 122 .dm_valid_addrs = ds1307_valid_addrs, 123 .dm_model = 1672, 124 .dm_rtc_start = DS1672_RTC_START, 125 .dm_rtc_size = DS1672_RTC_SIZE, 126 .dm_ch_reg = DS1672_CONTROL, 127 .dm_ch_value = DS1672_CONTROL_CH, 128 .dm_flags = 0, 129 }, { 130 .dm_compats = ds3231_compats, 131 .dm_valid_addrs = ds1307_valid_addrs, 132 .dm_model = 3231, 133 .dm_rtc_start = DS3232_RTC_START, 134 .dm_rtc_size = DS3232_RTC_SIZE, 135 /* 136 * XXX 137 * the DS3232 likely has the temperature sensor too but I can't 138 * easily verify or test that right now 139 */ 140 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 141 }, { 142 .dm_compats = ds3232_compats, 143 .dm_valid_addrs = ds1307_valid_addrs, 144 .dm_model = 3232, 145 .dm_rtc_start = DS3232_RTC_START, 146 .dm_rtc_size = DS3232_RTC_SIZE, 147 .dm_nvram_start = DS3232_NVRAM_START, 148 .dm_nvram_size = DS3232_NVRAM_SIZE, 149 .dm_flags = DSRTC_FLAG_BCD, 150 }, { 151 /* MCP7940 */ 152 .dm_compats = mcp7940_compats, 153 .dm_valid_addrs = mcp7940_valid_addrs, 154 .dm_model = 7940, 155 .dm_rtc_start = DS1307_RTC_START, 156 .dm_rtc_size = DS1307_RTC_SIZE, 157 .dm_ch_reg = DSXXXX_SECONDS, 158 .dm_ch_value = DS1307_SECONDS_CH, 159 .dm_vbaten_reg = DSXXXX_DAY, 160 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 161 .dm_nvram_start = MCP7940_NVRAM_START, 162 .dm_nvram_size = MCP7940_NVRAM_SIZE, 163 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 164 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 165 }, 166 }; 167 168 struct dsrtc_softc { 169 device_t sc_dev; 170 i2c_tag_t sc_tag; 171 uint8_t sc_address; 172 bool sc_open; 173 struct dsrtc_model sc_model; 174 struct todr_chip_handle sc_todr; 175 struct sysmon_envsys *sc_sme; 176 envsys_data_t sc_sensor; 177 }; 178 179 static void dsrtc_attach(device_t, device_t, void *); 180 static int dsrtc_match(device_t, cfdata_t, void *); 181 182 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 183 dsrtc_match, dsrtc_attach, NULL, NULL); 184 185 dev_type_open(dsrtc_open); 186 dev_type_close(dsrtc_close); 187 dev_type_read(dsrtc_read); 188 dev_type_write(dsrtc_write); 189 190 const struct cdevsw dsrtc_cdevsw = { 191 .d_open = dsrtc_open, 192 .d_close = dsrtc_close, 193 .d_read = dsrtc_read, 194 .d_write = dsrtc_write, 195 .d_ioctl = noioctl, 196 .d_stop = nostop, 197 .d_tty = notty, 198 .d_poll = nopoll, 199 .d_mmap = nommap, 200 .d_kqfilter = nokqfilter, 201 .d_discard = nodiscard, 202 .d_flag = D_OTHER 203 }; 204 205 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 206 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 207 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 208 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 209 210 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 211 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 212 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 213 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 214 215 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 216 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 217 218 static const struct dsrtc_model * 219 dsrtc_model_by_number(u_int model) 220 { 221 /* no model given, assume it's a DS1307 (the first one) */ 222 if (model == 0) 223 return &dsrtc_models[0]; 224 225 for (const struct dsrtc_model *dm = dsrtc_models; 226 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 227 if (dm->dm_model == model) 228 return dm; 229 } 230 return NULL; 231 } 232 233 static const struct dsrtc_model * 234 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 235 { 236 const struct dsrtc_model *best_model = NULL, *dm; 237 int best_match = 0, match_result; 238 239 for (dm = dsrtc_models; 240 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 241 match_result = iic_compat_match(ia, dm->dm_compats); 242 if (match_result > best_match) { 243 best_match = match_result; 244 best_model = dm; 245 } 246 } 247 return best_model; 248 } 249 250 static bool 251 dsrtc_direct_match(const struct i2c_attach_args *ia, const cfdata_t cf, 252 int *best_matchp) 253 { 254 const struct dsrtc_model *dm; 255 int best_match = 0, match_result; 256 257 for (dm = dsrtc_models; 258 dm < dsrtc_models + __arraycount(dsrtc_models); dm++) { 259 if (iic_use_direct_match(ia, cf, dm->dm_compats, 260 &match_result) == false) 261 return false; 262 if (match_result > best_match) 263 best_match = match_result; 264 } 265 266 *best_matchp = best_match; 267 return true; 268 } 269 270 static bool 271 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 272 { 273 274 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 275 if (addr == dm->dm_valid_addrs[i]) 276 return true; 277 } 278 return false; 279 } 280 281 static int 282 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 283 { 284 struct i2c_attach_args *ia = arg; 285 const struct dsrtc_model *dm; 286 int match_result; 287 288 if (dsrtc_direct_match(ia, cf, &match_result)) 289 return match_result; 290 291 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 292 if (dm == NULL) 293 return 0; 294 295 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 296 return I2C_MATCH_ADDRESS_ONLY; 297 298 return 0; 299 } 300 301 static void 302 dsrtc_attach(device_t parent, device_t self, void *arg) 303 { 304 struct dsrtc_softc *sc = device_private(self); 305 struct i2c_attach_args *ia = arg; 306 const struct dsrtc_model *dm; 307 308 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 309 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 310 311 if (dm == NULL) { 312 aprint_error(": unable to determine model!\n"); 313 return; 314 } 315 316 aprint_naive(": Real-time Clock%s\n", 317 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 318 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 319 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 320 321 sc->sc_tag = ia->ia_tag; 322 sc->sc_address = ia->ia_addr; 323 sc->sc_model = *dm; 324 sc->sc_dev = self; 325 sc->sc_open = 0; 326 sc->sc_todr.cookie = sc; 327 if (dm->dm_flags & DSRTC_FLAG_BCD) { 328 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 329 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 330 } else { 331 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 332 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 333 } 334 sc->sc_todr.todr_setwen = NULL; 335 336 todr_attach(&sc->sc_todr); 337 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 338 int error; 339 340 sc->sc_sme = sysmon_envsys_create(); 341 sc->sc_sme->sme_name = device_xname(self); 342 sc->sc_sme->sme_cookie = sc; 343 sc->sc_sme->sme_refresh = dsrtc_refresh; 344 345 sc->sc_sensor.units = ENVSYS_STEMP; 346 sc->sc_sensor.state = ENVSYS_SINVALID; 347 sc->sc_sensor.flags = 0; 348 (void)strlcpy(sc->sc_sensor.desc, "temperature", 349 sizeof(sc->sc_sensor.desc)); 350 351 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 352 aprint_error_dev(self, "unable to attach sensor\n"); 353 goto bad; 354 } 355 356 error = sysmon_envsys_register(sc->sc_sme); 357 if (error) { 358 aprint_error_dev(self, 359 "error %d registering with sysmon\n", error); 360 goto bad; 361 } 362 } 363 return; 364 bad: 365 sysmon_envsys_destroy(sc->sc_sme); 366 } 367 368 /*ARGSUSED*/ 369 int 370 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 371 { 372 struct dsrtc_softc *sc; 373 374 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 375 return ENXIO; 376 377 /* XXX: Locking */ 378 if (sc->sc_open) 379 return EBUSY; 380 381 sc->sc_open = true; 382 return 0; 383 } 384 385 /*ARGSUSED*/ 386 int 387 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 388 { 389 struct dsrtc_softc *sc; 390 391 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 392 return ENXIO; 393 394 sc->sc_open = false; 395 return 0; 396 } 397 398 /*ARGSUSED*/ 399 int 400 dsrtc_read(dev_t dev, struct uio *uio, int flags) 401 { 402 struct dsrtc_softc *sc; 403 int error; 404 405 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 406 return ENXIO; 407 408 const struct dsrtc_model * const dm = &sc->sc_model; 409 if (uio->uio_offset >= dm->dm_nvram_size) 410 return EINVAL; 411 412 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 413 return error; 414 415 KASSERT(uio->uio_offset >= 0); 416 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 417 uint8_t ch, cmd; 418 const u_int a = uio->uio_offset; 419 cmd = a + dm->dm_nvram_start; 420 if ((error = iic_exec(sc->sc_tag, 421 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 422 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 423 iic_release_bus(sc->sc_tag, 0); 424 aprint_error_dev(sc->sc_dev, 425 "%s: read failed at 0x%x: %d\n", 426 __func__, a, error); 427 return error; 428 } 429 if ((error = uiomove(&ch, 1, uio)) != 0) { 430 iic_release_bus(sc->sc_tag, 0); 431 return error; 432 } 433 } 434 435 iic_release_bus(sc->sc_tag, 0); 436 437 return 0; 438 } 439 440 /*ARGSUSED*/ 441 int 442 dsrtc_write(dev_t dev, struct uio *uio, int flags) 443 { 444 struct dsrtc_softc *sc; 445 int error; 446 447 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 448 return ENXIO; 449 450 const struct dsrtc_model * const dm = &sc->sc_model; 451 if (uio->uio_offset >= dm->dm_nvram_size) 452 return EINVAL; 453 454 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 455 return error; 456 457 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 458 uint8_t cmdbuf[2]; 459 const u_int a = (int)uio->uio_offset; 460 cmdbuf[0] = a + dm->dm_nvram_start; 461 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 462 break; 463 464 if ((error = iic_exec(sc->sc_tag, 465 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 466 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 467 aprint_error_dev(sc->sc_dev, 468 "%s: write failed at 0x%x: %d\n", 469 __func__, a, error); 470 break; 471 } 472 } 473 474 iic_release_bus(sc->sc_tag, 0); 475 476 return error; 477 } 478 479 static int 480 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 481 { 482 struct dsrtc_softc *sc = ch->cookie; 483 struct clock_ymdhms check; 484 int retries; 485 486 memset(dt, 0, sizeof(*dt)); 487 memset(&check, 0, sizeof(check)); 488 489 /* 490 * Since we don't support Burst Read, we have to read the clock twice 491 * until we get two consecutive identical results. 492 */ 493 retries = 5; 494 do { 495 dsrtc_clock_read_ymdhms(sc, dt); 496 dsrtc_clock_read_ymdhms(sc, &check); 497 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 498 499 return 0; 500 } 501 502 static int 503 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 504 { 505 struct dsrtc_softc *sc = ch->cookie; 506 507 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 508 return -1; 509 510 return 0; 511 } 512 513 static int 514 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 515 { 516 struct dsrtc_model * const dm = &sc->sc_model; 517 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 518 int error; 519 520 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 521 522 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 523 aprint_error_dev(sc->sc_dev, 524 "%s: failed to acquire I2C bus: %d\n", 525 __func__, error); 526 return 0; 527 } 528 529 /* Read each RTC register in order. */ 530 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 531 cmdbuf[0] = dm->dm_rtc_start + i; 532 533 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 534 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 535 } 536 537 /* Done with I2C */ 538 iic_release_bus(sc->sc_tag, I2C_F_POLL); 539 540 if (error != 0) { 541 aprint_error_dev(sc->sc_dev, 542 "%s: failed to read rtc at 0x%x: %d\n", 543 __func__, cmdbuf[0], error); 544 return 0; 545 } 546 547 /* 548 * Convert the RTC's register values into something useable 549 */ 550 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 551 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 552 553 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 554 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 555 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 556 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 557 dt->dt_hour += 12; 558 } else 559 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 560 DSXXXX_HOURS_24MASK); 561 562 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 563 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 564 565 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 566 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 567 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 568 else { 569 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 570 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 571 dt->dt_year += 100; 572 } 573 574 return 1; 575 } 576 577 static int 578 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 579 { 580 struct dsrtc_model * const dm = &sc->sc_model; 581 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 582 int error; 583 584 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 585 586 /* 587 * Convert our time representation into something the DSXXXX 588 * can understand. 589 */ 590 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 591 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 592 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 593 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 594 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 595 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 596 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 597 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 598 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 599 600 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 601 aprint_error_dev(sc->sc_dev, 602 "%s: failed to acquire I2C bus: %d\n", 603 __func__, error); 604 return 0; 605 } 606 607 /* Stop the clock */ 608 cmdbuf[0] = dm->dm_ch_reg; 609 610 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 611 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 612 iic_release_bus(sc->sc_tag, I2C_F_POLL); 613 aprint_error_dev(sc->sc_dev, 614 "%s: failed to read Hold Clock: %d\n", 615 __func__, error); 616 return 0; 617 } 618 619 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 620 cmdbuf[1] &= ~dm->dm_ch_value; 621 else 622 cmdbuf[1] |= dm->dm_ch_value; 623 624 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 625 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 626 iic_release_bus(sc->sc_tag, I2C_F_POLL); 627 aprint_error_dev(sc->sc_dev, 628 "%s: failed to write Hold Clock: %d\n", 629 __func__, error); 630 return 0; 631 } 632 633 /* 634 * Write registers in reverse order. The last write (to the Seconds 635 * register) will undo the Clock Hold, above. 636 */ 637 uint8_t op = I2C_OP_WRITE; 638 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 639 cmdbuf[0] = dm->dm_rtc_start + i; 640 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 641 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 642 bcd[i] |= dm->dm_vbaten_value; 643 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 644 op = I2C_OP_WRITE_WITH_STOP; 645 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 646 bcd[i] |= dm->dm_ch_value; 647 } 648 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 649 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 650 iic_release_bus(sc->sc_tag, I2C_F_POLL); 651 aprint_error_dev(sc->sc_dev, 652 "%s: failed to write rtc at 0x%x: %d\n", 653 __func__, i, error); 654 /* XXX: Clock Hold is likely still asserted! */ 655 return 0; 656 } 657 } 658 /* 659 * If the clock hold register isn't the same register as seconds, 660 * we need to reeanble the clock. 661 */ 662 if (op != I2C_OP_WRITE_WITH_STOP) { 663 cmdbuf[0] = dm->dm_ch_reg; 664 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 665 cmdbuf[1] |= dm->dm_ch_value; 666 else 667 cmdbuf[1] &= ~dm->dm_ch_value; 668 669 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 670 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 671 I2C_F_POLL)) != 0) { 672 iic_release_bus(sc->sc_tag, I2C_F_POLL); 673 aprint_error_dev(sc->sc_dev, 674 "%s: failed to Hold Clock: %d\n", 675 __func__, error); 676 return 0; 677 } 678 } 679 680 iic_release_bus(sc->sc_tag, I2C_F_POLL); 681 682 return 1; 683 } 684 685 static int 686 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 687 { 688 struct dsrtc_softc *sc = ch->cookie; 689 struct timeval check; 690 int retries; 691 692 memset(tv, 0, sizeof(*tv)); 693 memset(&check, 0, sizeof(check)); 694 695 /* 696 * Since we don't support Burst Read, we have to read the clock twice 697 * until we get two consecutive identical results. 698 */ 699 retries = 5; 700 do { 701 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 702 dsrtc_clock_read_timeval(sc, &check.tv_sec); 703 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 704 705 return 0; 706 } 707 708 static int 709 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 710 { 711 struct dsrtc_softc *sc = ch->cookie; 712 713 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 714 return -1; 715 716 return 0; 717 } 718 719 /* 720 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 721 * it, since some I2C controllers don't support anything other than single-byte 722 * transfers. 723 */ 724 static int 725 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 726 { 727 const struct dsrtc_model * const dm = &sc->sc_model; 728 uint8_t buf[4]; 729 int error; 730 731 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 732 aprint_error_dev(sc->sc_dev, 733 "%s: failed to acquire I2C bus: %d\n", 734 __func__, error); 735 return 0; 736 } 737 738 /* read all registers: */ 739 uint8_t reg = dm->dm_rtc_start; 740 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 741 ®, 1, buf, 4, I2C_F_POLL); 742 743 /* Done with I2C */ 744 iic_release_bus(sc->sc_tag, I2C_F_POLL); 745 746 if (error != 0) { 747 aprint_error_dev(sc->sc_dev, 748 "%s: failed to read rtc at 0x%x: %d\n", 749 __func__, reg, error); 750 return 0; 751 } 752 753 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 754 *tp = v; 755 756 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 757 __func__, v); 758 759 return 1; 760 } 761 762 static int 763 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 764 { 765 const struct dsrtc_model * const dm = &sc->sc_model; 766 size_t buflen = dm->dm_rtc_size + 2; 767 uint8_t buf[buflen]; 768 int error; 769 770 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 771 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 772 773 buf[0] = dm->dm_rtc_start; 774 buf[1] = (t >> 0) & 0xff; 775 buf[2] = (t >> 8) & 0xff; 776 buf[3] = (t >> 16) & 0xff; 777 buf[4] = (t >> 24) & 0xff; 778 buf[5] = 0; 779 780 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 781 aprint_error_dev(sc->sc_dev, 782 "%s: failed to acquire I2C bus: %d\n", 783 __func__, error); 784 return 0; 785 } 786 787 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 788 &buf, buflen, NULL, 0, I2C_F_POLL); 789 790 /* Done with I2C */ 791 iic_release_bus(sc->sc_tag, I2C_F_POLL); 792 793 /* send data */ 794 if (error != 0) { 795 aprint_error_dev(sc->sc_dev, 796 "%s: failed to set time: %d\n", 797 __func__, error); 798 return 0; 799 } 800 801 return 1; 802 } 803 804 static int 805 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 806 { 807 int error, tc; 808 uint8_t reg = DS3232_TEMP_MSB; 809 uint8_t buf[2]; 810 811 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 812 return ENOTSUP; 813 814 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 815 aprint_error_dev(sc->sc_dev, 816 "%s: failed to acquire I2C bus: %d\n", 817 __func__, error); 818 return 0; 819 } 820 821 /* read temperature registers: */ 822 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 823 ®, 1, buf, 2, I2C_F_POLL); 824 825 /* Done with I2C */ 826 iic_release_bus(sc->sc_tag, I2C_F_POLL); 827 828 if (error != 0) { 829 aprint_error_dev(sc->sc_dev, 830 "%s: failed to read temperature: %d\n", 831 __func__, error); 832 return 0; 833 } 834 835 /* convert to microkelvin */ 836 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 837 *temp = tc + 273150000; 838 return 1; 839 } 840 841 static void 842 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 843 { 844 struct dsrtc_softc *sc = sme->sme_cookie; 845 uint32_t temp = 0; /* XXX gcc */ 846 847 if (dsrtc_read_temp(sc, &temp) == 0) { 848 edata->state = ENVSYS_SINVALID; 849 return; 850 } 851 852 edata->value_cur = temp; 853 854 edata->state = ENVSYS_SVALID; 855 } 856
Indexes created Thu Oct 02 10:09:58 GMT 2025