ds1307.c revision 1.27
1 /* $NetBSD: ds1307.c,v 1.27 2018/06/18 17:07:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.27 2018/06/18 17:07:07 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 58 struct dsrtc_model { 59 const i2c_addr_t *dm_valid_addrs; 60 uint16_t dm_model; 61 uint8_t dm_ch_reg; 62 uint8_t dm_ch_value; 63 uint8_t dm_vbaten_reg; 64 uint8_t dm_vbaten_value; 65 uint8_t dm_rtc_start; 66 uint8_t dm_rtc_size; 67 uint8_t dm_nvram_start; 68 uint8_t dm_nvram_size; 69 uint8_t dm_flags; 70 #define DSRTC_FLAG_CLOCK_HOLD 0x01 71 #define DSRTC_FLAG_BCD 0x02 72 #define DSRTC_FLAG_TEMP 0x04 73 #define DSRTC_FLAG_VBATEN 0x08 74 #define DSRTC_FLAG_YEAR_START_2K 0x10 75 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 76 }; 77 78 static const char *ds1307_compats[] = { "dallas,ds1307", "maxim,ds1307", NULL }; 79 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 80 static const struct dsrtc_model ds1307_model = { 81 .dm_valid_addrs = ds1307_valid_addrs, 82 .dm_model = 1307, 83 .dm_ch_reg = DSXXXX_SECONDS, 84 .dm_ch_value = DS1307_SECONDS_CH, 85 .dm_rtc_start = DS1307_RTC_START, 86 .dm_rtc_size = DS1307_RTC_SIZE, 87 .dm_nvram_start = DS1307_NVRAM_START, 88 .dm_nvram_size = DS1307_NVRAM_SIZE, 89 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 90 }; 91 92 static const char *ds1339_compats[] = { "dallas,ds1339", "maxim,ds1339", NULL }; 93 static const struct dsrtc_model ds1339_model = { 94 .dm_valid_addrs = ds1307_valid_addrs, 95 .dm_model = 1339, 96 .dm_rtc_start = DS1339_RTC_START, 97 .dm_rtc_size = DS1339_RTC_SIZE, 98 .dm_flags = DSRTC_FLAG_BCD, 99 }; 100 101 static const char *ds1340_compats[] = { "dallas,ds1340", "maxim,ds1340", NULL }; 102 static const struct dsrtc_model ds1340_model = { 103 .dm_valid_addrs = ds1307_valid_addrs, 104 .dm_model = 1340, 105 .dm_ch_reg = DSXXXX_SECONDS, 106 .dm_ch_value = DS1340_SECONDS_EOSC, 107 .dm_rtc_start = DS1340_RTC_START, 108 .dm_rtc_size = DS1340_RTC_SIZE, 109 .dm_flags = DSRTC_FLAG_BCD, 110 }; 111 112 static const char *ds1672_compats[] = { "dallas,ds1672", "maxim,ds1672", NULL }; 113 static const struct dsrtc_model ds1672_model = { 114 .dm_valid_addrs = ds1307_valid_addrs, 115 .dm_model = 1672, 116 .dm_rtc_start = DS1672_RTC_START, 117 .dm_rtc_size = DS1672_RTC_SIZE, 118 .dm_ch_reg = DS1672_CONTROL, 119 .dm_ch_value = DS1672_CONTROL_CH, 120 .dm_flags = 0, 121 }; 122 123 static const char *ds3231_compats[] = { "dallas,ds3231", "maxim,ds3231", NULL }; 124 static const struct dsrtc_model ds3231_model = { 125 .dm_valid_addrs = ds1307_valid_addrs, 126 .dm_model = 3231, 127 .dm_rtc_start = DS3232_RTC_START, 128 .dm_rtc_size = DS3232_RTC_SIZE, 129 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 130 }; 131 132 static const char *ds3232_compats[] = { "dallas,ds3232", "maxim,ds3232", NULL }; 133 static const struct dsrtc_model ds3232_model = { 134 .dm_valid_addrs = ds1307_valid_addrs, 135 .dm_model = 3232, 136 .dm_rtc_start = DS3232_RTC_START, 137 .dm_rtc_size = DS3232_RTC_SIZE, 138 .dm_nvram_start = DS3232_NVRAM_START, 139 .dm_nvram_size = DS3232_NVRAM_SIZE, 140 /* 141 * XXX 142 * the DS3232 likely has the temperature sensor too but I can't 143 * easily verify or test that right now 144 */ 145 .dm_flags = DSRTC_FLAG_BCD, 146 }; 147 148 /* XXX vendor prefix */ 149 static const char *mcp7940_compats[] = { "microchip,mcp7940", NULL }; 150 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 151 static const struct dsrtc_model mcp7940_model = { 152 .dm_valid_addrs = mcp7940_valid_addrs, 153 .dm_model = 7940, 154 .dm_rtc_start = DS1307_RTC_START, 155 .dm_rtc_size = DS1307_RTC_SIZE, 156 .dm_ch_reg = DSXXXX_SECONDS, 157 .dm_ch_value = DS1307_SECONDS_CH, 158 .dm_vbaten_reg = DSXXXX_DAY, 159 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 160 .dm_nvram_start = MCP7940_NVRAM_START, 161 .dm_nvram_size = MCP7940_NVRAM_SIZE, 162 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 163 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 164 }; 165 166 static const struct device_compatible_entry dsrtc_compat_data[] = { 167 DEVICE_COMPAT_ENTRY_WITH_DATA(ds1307_compats, &ds1307_model), 168 DEVICE_COMPAT_ENTRY_WITH_DATA(ds1339_compats, &ds1339_model), 169 DEVICE_COMPAT_ENTRY_WITH_DATA(ds1340_compats, &ds1340_model), 170 DEVICE_COMPAT_ENTRY_WITH_DATA(ds1672_compats, &ds1672_model), 171 DEVICE_COMPAT_ENTRY_WITH_DATA(ds3231_compats, &ds3231_model), 172 DEVICE_COMPAT_ENTRY_WITH_DATA(ds3232_compats, &ds3232_model), 173 DEVICE_COMPAT_ENTRY_WITH_DATA(mcp7940_compats, &mcp7940_model), 174 DEVICE_COMPAT_TERMINATOR 175 }; 176 177 struct dsrtc_softc { 178 device_t sc_dev; 179 i2c_tag_t sc_tag; 180 uint8_t sc_address; 181 bool sc_open; 182 struct dsrtc_model sc_model; 183 struct todr_chip_handle sc_todr; 184 struct sysmon_envsys *sc_sme; 185 envsys_data_t sc_sensor; 186 }; 187 188 static void dsrtc_attach(device_t, device_t, void *); 189 static int dsrtc_match(device_t, cfdata_t, void *); 190 191 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 192 dsrtc_match, dsrtc_attach, NULL, NULL); 193 194 dev_type_open(dsrtc_open); 195 dev_type_close(dsrtc_close); 196 dev_type_read(dsrtc_read); 197 dev_type_write(dsrtc_write); 198 199 const struct cdevsw dsrtc_cdevsw = { 200 .d_open = dsrtc_open, 201 .d_close = dsrtc_close, 202 .d_read = dsrtc_read, 203 .d_write = dsrtc_write, 204 .d_ioctl = noioctl, 205 .d_stop = nostop, 206 .d_tty = notty, 207 .d_poll = nopoll, 208 .d_mmap = nommap, 209 .d_kqfilter = nokqfilter, 210 .d_discard = nodiscard, 211 .d_flag = D_OTHER 212 }; 213 214 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 215 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 216 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 217 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 218 219 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 220 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 221 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 222 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 223 224 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 225 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 226 227 static const struct dsrtc_model * 228 dsrtc_model_by_number(u_int model) 229 { 230 const struct device_compatible_entry *dce; 231 const struct dsrtc_model *dm; 232 233 /* no model given, assume it's a DS1307 */ 234 if (model == 0) 235 return &ds1307_model; 236 237 for (dce = dsrtc_compat_data; 238 DEVICE_COMPAT_ENTRY_IS_TERMINATOR(dce) == false; dce++) { 239 dm = DEVICE_COMPAT_ENTRY_GET_PTR(dce); 240 if (dm->dm_model == model) 241 return dm; 242 } 243 return NULL; 244 } 245 246 static const struct dsrtc_model * 247 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 248 { 249 const struct dsrtc_model *dm = NULL; 250 const struct device_compatible_entry *dce; 251 252 dce = iic_compatible_match(ia, dsrtc_compat_data, NULL); 253 if (dce != NULL) 254 dm = DEVICE_COMPAT_ENTRY_GET_PTR(dce); 255 256 return dm; 257 } 258 259 static bool 260 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 261 { 262 263 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 264 if (addr == dm->dm_valid_addrs[i]) 265 return true; 266 } 267 return false; 268 } 269 270 static int 271 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 272 { 273 struct i2c_attach_args *ia = arg; 274 const struct dsrtc_model *dm; 275 int match_result; 276 277 if (iic_use_direct_match(ia, cf, dsrtc_compat_data, &match_result)) 278 return match_result; 279 280 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 281 if (dm == NULL) 282 return 0; 283 284 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 285 return I2C_MATCH_ADDRESS_ONLY; 286 287 return 0; 288 } 289 290 static void 291 dsrtc_attach(device_t parent, device_t self, void *arg) 292 { 293 struct dsrtc_softc *sc = device_private(self); 294 struct i2c_attach_args *ia = arg; 295 const struct dsrtc_model *dm; 296 297 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 298 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 299 300 if (dm == NULL) { 301 aprint_error(": unable to determine model!\n"); 302 return; 303 } 304 305 aprint_naive(": Real-time Clock%s\n", 306 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 307 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 308 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 309 310 sc->sc_tag = ia->ia_tag; 311 sc->sc_address = ia->ia_addr; 312 sc->sc_model = *dm; 313 sc->sc_dev = self; 314 sc->sc_open = 0; 315 sc->sc_todr.cookie = sc; 316 if (dm->dm_flags & DSRTC_FLAG_BCD) { 317 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 318 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 319 } else { 320 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 321 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 322 } 323 sc->sc_todr.todr_setwen = NULL; 324 325 todr_attach(&sc->sc_todr); 326 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 327 int error; 328 329 sc->sc_sme = sysmon_envsys_create(); 330 sc->sc_sme->sme_name = device_xname(self); 331 sc->sc_sme->sme_cookie = sc; 332 sc->sc_sme->sme_refresh = dsrtc_refresh; 333 334 sc->sc_sensor.units = ENVSYS_STEMP; 335 sc->sc_sensor.state = ENVSYS_SINVALID; 336 sc->sc_sensor.flags = 0; 337 (void)strlcpy(sc->sc_sensor.desc, "temperature", 338 sizeof(sc->sc_sensor.desc)); 339 340 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 341 aprint_error_dev(self, "unable to attach sensor\n"); 342 goto bad; 343 } 344 345 error = sysmon_envsys_register(sc->sc_sme); 346 if (error) { 347 aprint_error_dev(self, 348 "error %d registering with sysmon\n", error); 349 goto bad; 350 } 351 } 352 return; 353 bad: 354 sysmon_envsys_destroy(sc->sc_sme); 355 } 356 357 /*ARGSUSED*/ 358 int 359 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 360 { 361 struct dsrtc_softc *sc; 362 363 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 364 return ENXIO; 365 366 /* XXX: Locking */ 367 if (sc->sc_open) 368 return EBUSY; 369 370 sc->sc_open = true; 371 return 0; 372 } 373 374 /*ARGSUSED*/ 375 int 376 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 377 { 378 struct dsrtc_softc *sc; 379 380 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 381 return ENXIO; 382 383 sc->sc_open = false; 384 return 0; 385 } 386 387 /*ARGSUSED*/ 388 int 389 dsrtc_read(dev_t dev, struct uio *uio, int flags) 390 { 391 struct dsrtc_softc *sc; 392 int error; 393 394 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 395 return ENXIO; 396 397 const struct dsrtc_model * const dm = &sc->sc_model; 398 if (uio->uio_offset >= dm->dm_nvram_size) 399 return EINVAL; 400 401 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 402 return error; 403 404 KASSERT(uio->uio_offset >= 0); 405 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 406 uint8_t ch, cmd; 407 const u_int a = uio->uio_offset; 408 cmd = a + dm->dm_nvram_start; 409 if ((error = iic_exec(sc->sc_tag, 410 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 411 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 412 iic_release_bus(sc->sc_tag, 0); 413 aprint_error_dev(sc->sc_dev, 414 "%s: read failed at 0x%x: %d\n", 415 __func__, a, error); 416 return error; 417 } 418 if ((error = uiomove(&ch, 1, uio)) != 0) { 419 iic_release_bus(sc->sc_tag, 0); 420 return error; 421 } 422 } 423 424 iic_release_bus(sc->sc_tag, 0); 425 426 return 0; 427 } 428 429 /*ARGSUSED*/ 430 int 431 dsrtc_write(dev_t dev, struct uio *uio, int flags) 432 { 433 struct dsrtc_softc *sc; 434 int error; 435 436 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 437 return ENXIO; 438 439 const struct dsrtc_model * const dm = &sc->sc_model; 440 if (uio->uio_offset >= dm->dm_nvram_size) 441 return EINVAL; 442 443 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 444 return error; 445 446 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 447 uint8_t cmdbuf[2]; 448 const u_int a = (int)uio->uio_offset; 449 cmdbuf[0] = a + dm->dm_nvram_start; 450 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 451 break; 452 453 if ((error = iic_exec(sc->sc_tag, 454 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 455 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 456 aprint_error_dev(sc->sc_dev, 457 "%s: write failed at 0x%x: %d\n", 458 __func__, a, error); 459 break; 460 } 461 } 462 463 iic_release_bus(sc->sc_tag, 0); 464 465 return error; 466 } 467 468 static int 469 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 470 { 471 struct dsrtc_softc *sc = ch->cookie; 472 struct clock_ymdhms check; 473 int retries; 474 475 memset(dt, 0, sizeof(*dt)); 476 memset(&check, 0, sizeof(check)); 477 478 /* 479 * Since we don't support Burst Read, we have to read the clock twice 480 * until we get two consecutive identical results. 481 */ 482 retries = 5; 483 do { 484 dsrtc_clock_read_ymdhms(sc, dt); 485 dsrtc_clock_read_ymdhms(sc, &check); 486 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 487 488 return 0; 489 } 490 491 static int 492 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 493 { 494 struct dsrtc_softc *sc = ch->cookie; 495 496 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 497 return -1; 498 499 return 0; 500 } 501 502 static int 503 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 504 { 505 struct dsrtc_model * const dm = &sc->sc_model; 506 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 507 int error; 508 509 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 510 511 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 512 aprint_error_dev(sc->sc_dev, 513 "%s: failed to acquire I2C bus: %d\n", 514 __func__, error); 515 return 0; 516 } 517 518 /* Read each RTC register in order. */ 519 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 520 cmdbuf[0] = dm->dm_rtc_start + i; 521 522 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 523 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 524 } 525 526 /* Done with I2C */ 527 iic_release_bus(sc->sc_tag, I2C_F_POLL); 528 529 if (error != 0) { 530 aprint_error_dev(sc->sc_dev, 531 "%s: failed to read rtc at 0x%x: %d\n", 532 __func__, cmdbuf[0], error); 533 return 0; 534 } 535 536 /* 537 * Convert the RTC's register values into something useable 538 */ 539 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 540 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 541 542 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 543 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 544 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 545 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 546 dt->dt_hour += 12; 547 } else 548 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 549 DSXXXX_HOURS_24MASK); 550 551 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 552 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 553 554 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 555 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 556 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 557 else { 558 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 559 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 560 dt->dt_year += 100; 561 } 562 563 return 1; 564 } 565 566 static int 567 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 568 { 569 struct dsrtc_model * const dm = &sc->sc_model; 570 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 571 int error; 572 573 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 574 575 /* 576 * Convert our time representation into something the DSXXXX 577 * can understand. 578 */ 579 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 580 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 581 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 582 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 583 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 584 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 585 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 586 if (dt->dt_year - POSIX_BASE_YEAR >= 100) 587 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 588 589 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 590 aprint_error_dev(sc->sc_dev, 591 "%s: failed to acquire I2C bus: %d\n", 592 __func__, error); 593 return 0; 594 } 595 596 /* Stop the clock */ 597 cmdbuf[0] = dm->dm_ch_reg; 598 599 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 600 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 601 iic_release_bus(sc->sc_tag, I2C_F_POLL); 602 aprint_error_dev(sc->sc_dev, 603 "%s: failed to read Hold Clock: %d\n", 604 __func__, error); 605 return 0; 606 } 607 608 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 609 cmdbuf[1] &= ~dm->dm_ch_value; 610 else 611 cmdbuf[1] |= dm->dm_ch_value; 612 613 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 614 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 615 iic_release_bus(sc->sc_tag, I2C_F_POLL); 616 aprint_error_dev(sc->sc_dev, 617 "%s: failed to write Hold Clock: %d\n", 618 __func__, error); 619 return 0; 620 } 621 622 /* 623 * Write registers in reverse order. The last write (to the Seconds 624 * register) will undo the Clock Hold, above. 625 */ 626 uint8_t op = I2C_OP_WRITE; 627 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 628 cmdbuf[0] = dm->dm_rtc_start + i; 629 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 630 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 631 bcd[i] |= dm->dm_vbaten_value; 632 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 633 op = I2C_OP_WRITE_WITH_STOP; 634 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 635 bcd[i] |= dm->dm_ch_value; 636 } 637 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 638 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 639 iic_release_bus(sc->sc_tag, I2C_F_POLL); 640 aprint_error_dev(sc->sc_dev, 641 "%s: failed to write rtc at 0x%x: %d\n", 642 __func__, i, error); 643 /* XXX: Clock Hold is likely still asserted! */ 644 return 0; 645 } 646 } 647 /* 648 * If the clock hold register isn't the same register as seconds, 649 * we need to reeanble the clock. 650 */ 651 if (op != I2C_OP_WRITE_WITH_STOP) { 652 cmdbuf[0] = dm->dm_ch_reg; 653 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 654 cmdbuf[1] |= dm->dm_ch_value; 655 else 656 cmdbuf[1] &= ~dm->dm_ch_value; 657 658 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 659 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 660 I2C_F_POLL)) != 0) { 661 iic_release_bus(sc->sc_tag, I2C_F_POLL); 662 aprint_error_dev(sc->sc_dev, 663 "%s: failed to Hold Clock: %d\n", 664 __func__, error); 665 return 0; 666 } 667 } 668 669 iic_release_bus(sc->sc_tag, I2C_F_POLL); 670 671 return 1; 672 } 673 674 static int 675 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 676 { 677 struct dsrtc_softc *sc = ch->cookie; 678 struct timeval check; 679 int retries; 680 681 memset(tv, 0, sizeof(*tv)); 682 memset(&check, 0, sizeof(check)); 683 684 /* 685 * Since we don't support Burst Read, we have to read the clock twice 686 * until we get two consecutive identical results. 687 */ 688 retries = 5; 689 do { 690 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 691 dsrtc_clock_read_timeval(sc, &check.tv_sec); 692 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 693 694 return 0; 695 } 696 697 static int 698 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 699 { 700 struct dsrtc_softc *sc = ch->cookie; 701 702 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 703 return -1; 704 705 return 0; 706 } 707 708 /* 709 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 710 * it, since some I2C controllers don't support anything other than single-byte 711 * transfers. 712 */ 713 static int 714 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 715 { 716 const struct dsrtc_model * const dm = &sc->sc_model; 717 uint8_t buf[4]; 718 int error; 719 720 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 721 aprint_error_dev(sc->sc_dev, 722 "%s: failed to acquire I2C bus: %d\n", 723 __func__, error); 724 return 0; 725 } 726 727 /* read all registers: */ 728 uint8_t reg = dm->dm_rtc_start; 729 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 730 ®, 1, buf, 4, I2C_F_POLL); 731 732 /* Done with I2C */ 733 iic_release_bus(sc->sc_tag, I2C_F_POLL); 734 735 if (error != 0) { 736 aprint_error_dev(sc->sc_dev, 737 "%s: failed to read rtc at 0x%x: %d\n", 738 __func__, reg, error); 739 return 0; 740 } 741 742 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 743 *tp = v; 744 745 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 746 __func__, v); 747 748 return 1; 749 } 750 751 static int 752 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 753 { 754 const struct dsrtc_model * const dm = &sc->sc_model; 755 size_t buflen = dm->dm_rtc_size + 2; 756 uint8_t buf[buflen]; 757 int error; 758 759 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 760 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 761 762 buf[0] = dm->dm_rtc_start; 763 buf[1] = (t >> 0) & 0xff; 764 buf[2] = (t >> 8) & 0xff; 765 buf[3] = (t >> 16) & 0xff; 766 buf[4] = (t >> 24) & 0xff; 767 buf[5] = 0; 768 769 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 770 aprint_error_dev(sc->sc_dev, 771 "%s: failed to acquire I2C bus: %d\n", 772 __func__, error); 773 return 0; 774 } 775 776 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 777 &buf, buflen, NULL, 0, I2C_F_POLL); 778 779 /* Done with I2C */ 780 iic_release_bus(sc->sc_tag, I2C_F_POLL); 781 782 /* send data */ 783 if (error != 0) { 784 aprint_error_dev(sc->sc_dev, 785 "%s: failed to set time: %d\n", 786 __func__, error); 787 return 0; 788 } 789 790 return 1; 791 } 792 793 static int 794 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 795 { 796 int error, tc; 797 uint8_t reg = DS3232_TEMP_MSB; 798 uint8_t buf[2]; 799 800 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 801 return ENOTSUP; 802 803 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 804 aprint_error_dev(sc->sc_dev, 805 "%s: failed to acquire I2C bus: %d\n", 806 __func__, error); 807 return 0; 808 } 809 810 /* read temperature registers: */ 811 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 812 ®, 1, buf, 2, I2C_F_POLL); 813 814 /* Done with I2C */ 815 iic_release_bus(sc->sc_tag, I2C_F_POLL); 816 817 if (error != 0) { 818 aprint_error_dev(sc->sc_dev, 819 "%s: failed to read temperature: %d\n", 820 __func__, error); 821 return 0; 822 } 823 824 /* convert to microkelvin */ 825 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 826 *temp = tc + 273150000; 827 return 1; 828 } 829 830 static void 831 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 832 { 833 struct dsrtc_softc *sc = sme->sme_cookie; 834 uint32_t temp = 0; /* XXX gcc */ 835 836 if (dsrtc_read_temp(sc, &temp) == 0) { 837 edata->state = ENVSYS_SINVALID; 838 return; 839 } 840 841 edata->value_cur = temp; 842 843 edata->state = ENVSYS_SVALID; 844 } 845
Indexes created Thu Oct 02 14:10:14 GMT 2025