ds1307.c revision 1.30
1 /* $NetBSD: ds1307.c,v 1.30 2018/12/14 22:05:36 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.30 2018/12/14 22:05:36 macallan Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 #include "opt_dsrtc.h" 58 59 struct dsrtc_model { 60 const i2c_addr_t *dm_valid_addrs; 61 uint16_t dm_model; 62 uint8_t dm_ch_reg; 63 uint8_t dm_ch_value; 64 uint8_t dm_vbaten_reg; 65 uint8_t dm_vbaten_value; 66 uint8_t dm_rtc_start; 67 uint8_t dm_rtc_size; 68 uint8_t dm_nvram_start; 69 uint8_t dm_nvram_size; 70 uint8_t dm_flags; 71 #define DSRTC_FLAG_CLOCK_HOLD 0x01 72 #define DSRTC_FLAG_BCD 0x02 73 #define DSRTC_FLAG_TEMP 0x04 74 #define DSRTC_FLAG_VBATEN 0x08 75 #define DSRTC_FLAG_YEAR_START_2K 0x10 76 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 77 }; 78 79 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 80 static const struct dsrtc_model ds1307_model = { 81 .dm_valid_addrs = ds1307_valid_addrs, 82 .dm_model = 1307, 83 .dm_ch_reg = DSXXXX_SECONDS, 84 .dm_ch_value = DS1307_SECONDS_CH, 85 .dm_rtc_start = DS1307_RTC_START, 86 .dm_rtc_size = DS1307_RTC_SIZE, 87 .dm_nvram_start = DS1307_NVRAM_START, 88 .dm_nvram_size = DS1307_NVRAM_SIZE, 89 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 90 }; 91 92 static const struct dsrtc_model ds1339_model = { 93 .dm_valid_addrs = ds1307_valid_addrs, 94 .dm_model = 1339, 95 .dm_rtc_start = DS1339_RTC_START, 96 .dm_rtc_size = DS1339_RTC_SIZE, 97 .dm_flags = DSRTC_FLAG_BCD, 98 }; 99 100 static const struct dsrtc_model ds1340_model = { 101 .dm_valid_addrs = ds1307_valid_addrs, 102 .dm_model = 1340, 103 .dm_ch_reg = DSXXXX_SECONDS, 104 .dm_ch_value = DS1340_SECONDS_EOSC, 105 .dm_rtc_start = DS1340_RTC_START, 106 .dm_rtc_size = DS1340_RTC_SIZE, 107 .dm_flags = DSRTC_FLAG_BCD, 108 }; 109 110 static const struct dsrtc_model ds1672_model = { 111 .dm_valid_addrs = ds1307_valid_addrs, 112 .dm_model = 1672, 113 .dm_rtc_start = DS1672_RTC_START, 114 .dm_rtc_size = DS1672_RTC_SIZE, 115 .dm_ch_reg = DS1672_CONTROL, 116 .dm_ch_value = DS1672_CONTROL_CH, 117 .dm_flags = 0, 118 }; 119 120 static const struct dsrtc_model ds3231_model = { 121 .dm_valid_addrs = ds1307_valid_addrs, 122 .dm_model = 3231, 123 .dm_rtc_start = DS3232_RTC_START, 124 .dm_rtc_size = DS3232_RTC_SIZE, 125 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 126 }; 127 128 static const struct dsrtc_model ds3232_model = { 129 .dm_valid_addrs = ds1307_valid_addrs, 130 .dm_model = 3232, 131 .dm_rtc_start = DS3232_RTC_START, 132 .dm_rtc_size = DS3232_RTC_SIZE, 133 .dm_nvram_start = DS3232_NVRAM_START, 134 .dm_nvram_size = DS3232_NVRAM_SIZE, 135 /* 136 * XXX 137 * the DS3232 likely has the temperature sensor too but I can't 138 * easily verify or test that right now 139 */ 140 .dm_flags = DSRTC_FLAG_BCD, 141 }; 142 143 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 144 static const struct dsrtc_model mcp7940_model = { 145 .dm_valid_addrs = mcp7940_valid_addrs, 146 .dm_model = 7940, 147 .dm_rtc_start = DS1307_RTC_START, 148 .dm_rtc_size = DS1307_RTC_SIZE, 149 .dm_ch_reg = DSXXXX_SECONDS, 150 .dm_ch_value = DS1307_SECONDS_CH, 151 .dm_vbaten_reg = DSXXXX_DAY, 152 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 153 .dm_nvram_start = MCP7940_NVRAM_START, 154 .dm_nvram_size = MCP7940_NVRAM_SIZE, 155 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 156 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 157 }; 158 159 static const struct device_compatible_entry compat_data[] = { 160 { "dallas,ds1307", (uintptr_t)&ds1307_model }, 161 { "maxim,ds1307", (uintptr_t)&ds1307_model }, 162 163 { "dallas,ds1339", (uintptr_t)&ds1339_model }, 164 { "maxim,ds1339", (uintptr_t)&ds1339_model }, 165 166 { "dallas,ds1340", (uintptr_t)&ds1340_model }, 167 { "maxim,ds1340", (uintptr_t)&ds1340_model }, 168 169 { "dallas,ds1672", (uintptr_t)&ds1672_model }, 170 { "maxim,ds1672", (uintptr_t)&ds1672_model }, 171 172 { "dallas,ds3231", (uintptr_t)&ds3231_model }, 173 { "maxim,ds3231", (uintptr_t)&ds3231_model }, 174 175 { "dallas,ds3232", (uintptr_t)&ds3232_model }, 176 { "maxim,ds3232", (uintptr_t)&ds3232_model }, 177 178 { "microchip,mcp7940", (uintptr_t)&mcp7940_model }, 179 180 { NULL, 0 } 181 }; 182 183 struct dsrtc_softc { 184 device_t sc_dev; 185 i2c_tag_t sc_tag; 186 uint8_t sc_address; 187 bool sc_open; 188 struct dsrtc_model sc_model; 189 struct todr_chip_handle sc_todr; 190 struct sysmon_envsys *sc_sme; 191 envsys_data_t sc_sensor; 192 }; 193 194 static void dsrtc_attach(device_t, device_t, void *); 195 static int dsrtc_match(device_t, cfdata_t, void *); 196 197 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 198 dsrtc_match, dsrtc_attach, NULL, NULL); 199 200 dev_type_open(dsrtc_open); 201 dev_type_close(dsrtc_close); 202 dev_type_read(dsrtc_read); 203 dev_type_write(dsrtc_write); 204 205 const struct cdevsw dsrtc_cdevsw = { 206 .d_open = dsrtc_open, 207 .d_close = dsrtc_close, 208 .d_read = dsrtc_read, 209 .d_write = dsrtc_write, 210 .d_ioctl = noioctl, 211 .d_stop = nostop, 212 .d_tty = notty, 213 .d_poll = nopoll, 214 .d_mmap = nommap, 215 .d_kqfilter = nokqfilter, 216 .d_discard = nodiscard, 217 .d_flag = D_OTHER 218 }; 219 220 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 221 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 222 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 223 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 224 225 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 226 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 227 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 228 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 229 230 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 231 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 232 233 static const struct dsrtc_model * 234 dsrtc_model_by_number(u_int model) 235 { 236 const struct device_compatible_entry *dce; 237 const struct dsrtc_model *dm; 238 239 /* no model given, assume it's a DS1307 */ 240 if (model == 0) 241 return &ds1307_model; 242 243 for (dce = compat_data; dce->compat != NULL; dce++) { 244 dm = (void *)dce->data; 245 if (dm->dm_model == model) 246 return dm; 247 } 248 return NULL; 249 } 250 251 static const struct dsrtc_model * 252 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 253 { 254 const struct dsrtc_model *dm = NULL; 255 const struct device_compatible_entry *dce; 256 257 if (iic_compatible_match(ia, compat_data, &dce)) 258 dm = (void *)dce->data; 259 260 return dm; 261 } 262 263 static bool 264 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 265 { 266 267 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 268 if (addr == dm->dm_valid_addrs[i]) 269 return true; 270 } 271 return false; 272 } 273 274 static int 275 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 276 { 277 struct i2c_attach_args *ia = arg; 278 const struct dsrtc_model *dm; 279 int match_result; 280 281 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 282 return match_result; 283 284 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 285 if (dm == NULL) 286 return 0; 287 288 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 289 return I2C_MATCH_ADDRESS_ONLY; 290 291 return 0; 292 } 293 294 static void 295 dsrtc_attach(device_t parent, device_t self, void *arg) 296 { 297 struct dsrtc_softc *sc = device_private(self); 298 struct i2c_attach_args *ia = arg; 299 const struct dsrtc_model *dm; 300 301 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 302 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 303 304 if (dm == NULL) { 305 aprint_error(": unable to determine model!\n"); 306 return; 307 } 308 309 aprint_naive(": Real-time Clock%s\n", 310 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 311 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 312 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 313 314 sc->sc_tag = ia->ia_tag; 315 sc->sc_address = ia->ia_addr; 316 sc->sc_model = *dm; 317 sc->sc_dev = self; 318 sc->sc_open = 0; 319 sc->sc_todr.cookie = sc; 320 321 if (dm->dm_flags & DSRTC_FLAG_BCD) { 322 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 323 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 324 } else { 325 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 326 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 327 } 328 sc->sc_todr.todr_setwen = NULL; 329 330 #ifdef DSRTC_YEAR_START_2K 331 sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 332 #endif 333 334 todr_attach(&sc->sc_todr); 335 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 336 int error; 337 338 sc->sc_sme = sysmon_envsys_create(); 339 sc->sc_sme->sme_name = device_xname(self); 340 sc->sc_sme->sme_cookie = sc; 341 sc->sc_sme->sme_refresh = dsrtc_refresh; 342 343 sc->sc_sensor.units = ENVSYS_STEMP; 344 sc->sc_sensor.state = ENVSYS_SINVALID; 345 sc->sc_sensor.flags = 0; 346 (void)strlcpy(sc->sc_sensor.desc, "temperature", 347 sizeof(sc->sc_sensor.desc)); 348 349 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 350 aprint_error_dev(self, "unable to attach sensor\n"); 351 goto bad; 352 } 353 354 error = sysmon_envsys_register(sc->sc_sme); 355 if (error) { 356 aprint_error_dev(self, 357 "error %d registering with sysmon\n", error); 358 goto bad; 359 } 360 } 361 return; 362 bad: 363 sysmon_envsys_destroy(sc->sc_sme); 364 } 365 366 /*ARGSUSED*/ 367 int 368 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 369 { 370 struct dsrtc_softc *sc; 371 372 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 373 return ENXIO; 374 375 /* XXX: Locking */ 376 if (sc->sc_open) 377 return EBUSY; 378 379 sc->sc_open = true; 380 return 0; 381 } 382 383 /*ARGSUSED*/ 384 int 385 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 386 { 387 struct dsrtc_softc *sc; 388 389 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 390 return ENXIO; 391 392 sc->sc_open = false; 393 return 0; 394 } 395 396 /*ARGSUSED*/ 397 int 398 dsrtc_read(dev_t dev, struct uio *uio, int flags) 399 { 400 struct dsrtc_softc *sc; 401 int error; 402 403 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 404 return ENXIO; 405 406 const struct dsrtc_model * const dm = &sc->sc_model; 407 if (uio->uio_offset >= dm->dm_nvram_size) 408 return EINVAL; 409 410 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 411 return error; 412 413 KASSERT(uio->uio_offset >= 0); 414 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 415 uint8_t ch, cmd; 416 const u_int a = uio->uio_offset; 417 cmd = a + dm->dm_nvram_start; 418 if ((error = iic_exec(sc->sc_tag, 419 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 420 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 421 iic_release_bus(sc->sc_tag, 0); 422 aprint_error_dev(sc->sc_dev, 423 "%s: read failed at 0x%x: %d\n", 424 __func__, a, error); 425 return error; 426 } 427 if ((error = uiomove(&ch, 1, uio)) != 0) { 428 iic_release_bus(sc->sc_tag, 0); 429 return error; 430 } 431 } 432 433 iic_release_bus(sc->sc_tag, 0); 434 435 return 0; 436 } 437 438 /*ARGSUSED*/ 439 int 440 dsrtc_write(dev_t dev, struct uio *uio, int flags) 441 { 442 struct dsrtc_softc *sc; 443 int error; 444 445 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 446 return ENXIO; 447 448 const struct dsrtc_model * const dm = &sc->sc_model; 449 if (uio->uio_offset >= dm->dm_nvram_size) 450 return EINVAL; 451 452 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 453 return error; 454 455 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 456 uint8_t cmdbuf[2]; 457 const u_int a = (int)uio->uio_offset; 458 cmdbuf[0] = a + dm->dm_nvram_start; 459 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 460 break; 461 462 if ((error = iic_exec(sc->sc_tag, 463 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 464 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 465 aprint_error_dev(sc->sc_dev, 466 "%s: write failed at 0x%x: %d\n", 467 __func__, a, error); 468 break; 469 } 470 } 471 472 iic_release_bus(sc->sc_tag, 0); 473 474 return error; 475 } 476 477 static int 478 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 479 { 480 struct dsrtc_softc *sc = ch->cookie; 481 struct clock_ymdhms check; 482 int retries; 483 484 memset(dt, 0, sizeof(*dt)); 485 memset(&check, 0, sizeof(check)); 486 487 /* 488 * Since we don't support Burst Read, we have to read the clock twice 489 * until we get two consecutive identical results. 490 */ 491 retries = 5; 492 do { 493 dsrtc_clock_read_ymdhms(sc, dt); 494 dsrtc_clock_read_ymdhms(sc, &check); 495 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 496 497 return 0; 498 } 499 500 static int 501 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 502 { 503 struct dsrtc_softc *sc = ch->cookie; 504 505 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 506 return -1; 507 508 return 0; 509 } 510 511 static int 512 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 513 { 514 struct dsrtc_model * const dm = &sc->sc_model; 515 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 516 int error; 517 518 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 519 520 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 521 aprint_error_dev(sc->sc_dev, 522 "%s: failed to acquire I2C bus: %d\n", 523 __func__, error); 524 return 0; 525 } 526 527 /* Read each RTC register in order. */ 528 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 529 cmdbuf[0] = dm->dm_rtc_start + i; 530 531 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 532 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 533 } 534 535 /* Done with I2C */ 536 iic_release_bus(sc->sc_tag, I2C_F_POLL); 537 538 if (error != 0) { 539 aprint_error_dev(sc->sc_dev, 540 "%s: failed to read rtc at 0x%x: %d\n", 541 __func__, cmdbuf[0], error); 542 return 0; 543 } 544 545 /* 546 * Convert the RTC's register values into something useable 547 */ 548 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 549 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 550 551 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 552 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 553 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 554 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 555 dt->dt_hour += 12; 556 } else 557 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 558 DSXXXX_HOURS_24MASK); 559 560 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 561 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 562 563 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 564 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 565 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 566 else { 567 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 568 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 569 dt->dt_year += 100; 570 } 571 572 return 1; 573 } 574 575 static int 576 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 577 { 578 struct dsrtc_model * const dm = &sc->sc_model; 579 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 580 int error, offset; 581 582 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 583 584 /* 585 * Convert our time representation into something the DSXXXX 586 * can understand. 587 */ 588 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 589 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 590 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 591 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 592 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 593 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 594 595 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) { 596 offset = 2000; 597 } else { 598 offset = POSIX_BASE_YEAR; 599 } 600 601 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - offset) % 100); 602 if (dt->dt_year - offset >= 100) 603 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 604 605 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 606 aprint_error_dev(sc->sc_dev, 607 "%s: failed to acquire I2C bus: %d\n", 608 __func__, error); 609 return 0; 610 } 611 612 /* Stop the clock */ 613 cmdbuf[0] = dm->dm_ch_reg; 614 615 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 616 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 617 iic_release_bus(sc->sc_tag, I2C_F_POLL); 618 aprint_error_dev(sc->sc_dev, 619 "%s: failed to read Hold Clock: %d\n", 620 __func__, error); 621 return 0; 622 } 623 624 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 625 cmdbuf[1] &= ~dm->dm_ch_value; 626 else 627 cmdbuf[1] |= dm->dm_ch_value; 628 629 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 630 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 631 iic_release_bus(sc->sc_tag, I2C_F_POLL); 632 aprint_error_dev(sc->sc_dev, 633 "%s: failed to write Hold Clock: %d\n", 634 __func__, error); 635 return 0; 636 } 637 638 /* 639 * Write registers in reverse order. The last write (to the Seconds 640 * register) will undo the Clock Hold, above. 641 */ 642 uint8_t op = I2C_OP_WRITE; 643 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 644 cmdbuf[0] = dm->dm_rtc_start + i; 645 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 646 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 647 bcd[i] |= dm->dm_vbaten_value; 648 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 649 op = I2C_OP_WRITE_WITH_STOP; 650 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 651 bcd[i] |= dm->dm_ch_value; 652 } 653 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 654 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 655 iic_release_bus(sc->sc_tag, I2C_F_POLL); 656 aprint_error_dev(sc->sc_dev, 657 "%s: failed to write rtc at 0x%x: %d\n", 658 __func__, i, error); 659 /* XXX: Clock Hold is likely still asserted! */ 660 return 0; 661 } 662 } 663 /* 664 * If the clock hold register isn't the same register as seconds, 665 * we need to reeanble the clock. 666 */ 667 if (op != I2C_OP_WRITE_WITH_STOP) { 668 cmdbuf[0] = dm->dm_ch_reg; 669 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 670 cmdbuf[1] |= dm->dm_ch_value; 671 else 672 cmdbuf[1] &= ~dm->dm_ch_value; 673 674 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 675 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 676 I2C_F_POLL)) != 0) { 677 iic_release_bus(sc->sc_tag, I2C_F_POLL); 678 aprint_error_dev(sc->sc_dev, 679 "%s: failed to Hold Clock: %d\n", 680 __func__, error); 681 return 0; 682 } 683 } 684 685 iic_release_bus(sc->sc_tag, I2C_F_POLL); 686 687 return 1; 688 } 689 690 static int 691 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 692 { 693 struct dsrtc_softc *sc = ch->cookie; 694 struct timeval check; 695 int retries; 696 697 memset(tv, 0, sizeof(*tv)); 698 memset(&check, 0, sizeof(check)); 699 700 /* 701 * Since we don't support Burst Read, we have to read the clock twice 702 * until we get two consecutive identical results. 703 */ 704 retries = 5; 705 do { 706 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 707 dsrtc_clock_read_timeval(sc, &check.tv_sec); 708 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 709 710 return 0; 711 } 712 713 static int 714 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 715 { 716 struct dsrtc_softc *sc = ch->cookie; 717 718 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 719 return -1; 720 721 return 0; 722 } 723 724 /* 725 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 726 * it, since some I2C controllers don't support anything other than single-byte 727 * transfers. 728 */ 729 static int 730 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 731 { 732 const struct dsrtc_model * const dm = &sc->sc_model; 733 uint8_t buf[4]; 734 int error; 735 736 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 737 aprint_error_dev(sc->sc_dev, 738 "%s: failed to acquire I2C bus: %d\n", 739 __func__, error); 740 return 0; 741 } 742 743 /* read all registers: */ 744 uint8_t reg = dm->dm_rtc_start; 745 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 746 ®, 1, buf, 4, I2C_F_POLL); 747 748 /* Done with I2C */ 749 iic_release_bus(sc->sc_tag, I2C_F_POLL); 750 751 if (error != 0) { 752 aprint_error_dev(sc->sc_dev, 753 "%s: failed to read rtc at 0x%x: %d\n", 754 __func__, reg, error); 755 return 0; 756 } 757 758 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 759 *tp = v; 760 761 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 762 __func__, v); 763 764 return 1; 765 } 766 767 static int 768 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 769 { 770 const struct dsrtc_model * const dm = &sc->sc_model; 771 size_t buflen = dm->dm_rtc_size + 2; 772 uint8_t buf[buflen]; 773 int error; 774 775 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 776 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 777 778 buf[0] = dm->dm_rtc_start; 779 buf[1] = (t >> 0) & 0xff; 780 buf[2] = (t >> 8) & 0xff; 781 buf[3] = (t >> 16) & 0xff; 782 buf[4] = (t >> 24) & 0xff; 783 buf[5] = 0; 784 785 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 786 aprint_error_dev(sc->sc_dev, 787 "%s: failed to acquire I2C bus: %d\n", 788 __func__, error); 789 return 0; 790 } 791 792 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 793 &buf, buflen, NULL, 0, I2C_F_POLL); 794 795 /* Done with I2C */ 796 iic_release_bus(sc->sc_tag, I2C_F_POLL); 797 798 /* send data */ 799 if (error != 0) { 800 aprint_error_dev(sc->sc_dev, 801 "%s: failed to set time: %d\n", 802 __func__, error); 803 return 0; 804 } 805 806 return 1; 807 } 808 809 static int 810 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 811 { 812 int error, tc; 813 uint8_t reg = DS3232_TEMP_MSB; 814 uint8_t buf[2]; 815 816 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 817 return ENOTSUP; 818 819 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 820 aprint_error_dev(sc->sc_dev, 821 "%s: failed to acquire I2C bus: %d\n", 822 __func__, error); 823 return 0; 824 } 825 826 /* read temperature registers: */ 827 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 828 ®, 1, buf, 2, I2C_F_POLL); 829 830 /* Done with I2C */ 831 iic_release_bus(sc->sc_tag, I2C_F_POLL); 832 833 if (error != 0) { 834 aprint_error_dev(sc->sc_dev, 835 "%s: failed to read temperature: %d\n", 836 __func__, error); 837 return 0; 838 } 839 840 /* convert to microkelvin */ 841 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 842 *temp = tc + 273150000; 843 return 1; 844 } 845 846 static void 847 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 848 { 849 struct dsrtc_softc *sc = sme->sme_cookie; 850 uint32_t temp = 0; /* XXX gcc */ 851 852 if (dsrtc_read_temp(sc, &temp) == 0) { 853 edata->state = ENVSYS_SINVALID; 854 return; 855 } 856 857 edata->value_cur = temp; 858 859 edata->state = ENVSYS_SVALID; 860 } 861
Indexes created Thu Oct 02 10:09:58 GMT 2025