ds1307.c revision 1.33
1 /* $NetBSD: ds1307.c,v 1.33 2019/09/29 05:35:29 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.33 2019/09/29 05:35:29 macallan Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 #include "opt_dsrtc.h" 58 59 struct dsrtc_model { 60 const i2c_addr_t *dm_valid_addrs; 61 uint16_t dm_model; 62 uint8_t dm_ch_reg; 63 uint8_t dm_ch_value; 64 uint8_t dm_vbaten_reg; 65 uint8_t dm_vbaten_value; 66 uint8_t dm_rtc_start; 67 uint8_t dm_rtc_size; 68 uint8_t dm_nvram_start; 69 uint8_t dm_nvram_size; 70 uint8_t dm_flags; 71 #define DSRTC_FLAG_CLOCK_HOLD 0x01 72 #define DSRTC_FLAG_BCD 0x02 73 #define DSRTC_FLAG_TEMP 0x04 74 #define DSRTC_FLAG_VBATEN 0x08 75 #define DSRTC_FLAG_YEAR_START_2K 0x10 76 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 77 }; 78 79 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 80 static const struct dsrtc_model ds1307_model = { 81 .dm_valid_addrs = ds1307_valid_addrs, 82 .dm_model = 1307, 83 .dm_ch_reg = DSXXXX_SECONDS, 84 .dm_ch_value = DS1307_SECONDS_CH, 85 .dm_rtc_start = DS1307_RTC_START, 86 .dm_rtc_size = DS1307_RTC_SIZE, 87 .dm_nvram_start = DS1307_NVRAM_START, 88 .dm_nvram_size = DS1307_NVRAM_SIZE, 89 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 90 }; 91 92 static const struct dsrtc_model ds1339_model = { 93 .dm_valid_addrs = ds1307_valid_addrs, 94 .dm_model = 1339, 95 .dm_rtc_start = DS1339_RTC_START, 96 .dm_rtc_size = DS1339_RTC_SIZE, 97 .dm_flags = DSRTC_FLAG_BCD, 98 }; 99 100 static const struct dsrtc_model ds1340_model = { 101 .dm_valid_addrs = ds1307_valid_addrs, 102 .dm_model = 1340, 103 .dm_ch_reg = DSXXXX_SECONDS, 104 .dm_ch_value = DS1340_SECONDS_EOSC, 105 .dm_rtc_start = DS1340_RTC_START, 106 .dm_rtc_size = DS1340_RTC_SIZE, 107 .dm_flags = DSRTC_FLAG_BCD, 108 }; 109 110 static const struct dsrtc_model ds1672_model = { 111 .dm_valid_addrs = ds1307_valid_addrs, 112 .dm_model = 1672, 113 .dm_rtc_start = DS1672_RTC_START, 114 .dm_rtc_size = DS1672_RTC_SIZE, 115 .dm_ch_reg = DS1672_CONTROL, 116 .dm_ch_value = DS1672_CONTROL_CH, 117 .dm_flags = 0, 118 }; 119 120 static const struct dsrtc_model ds3231_model = { 121 .dm_valid_addrs = ds1307_valid_addrs, 122 .dm_model = 3231, 123 .dm_rtc_start = DS3232_RTC_START, 124 .dm_rtc_size = DS3232_RTC_SIZE, 125 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 126 }; 127 128 static const struct dsrtc_model ds3232_model = { 129 .dm_valid_addrs = ds1307_valid_addrs, 130 .dm_model = 3232, 131 .dm_rtc_start = DS3232_RTC_START, 132 .dm_rtc_size = DS3232_RTC_SIZE, 133 .dm_nvram_start = DS3232_NVRAM_START, 134 .dm_nvram_size = DS3232_NVRAM_SIZE, 135 /* 136 * XXX 137 * the DS3232 likely has the temperature sensor too but I can't 138 * easily verify or test that right now 139 */ 140 .dm_flags = DSRTC_FLAG_BCD, 141 }; 142 143 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 144 static const struct dsrtc_model mcp7940_model = { 145 .dm_valid_addrs = mcp7940_valid_addrs, 146 .dm_model = 7940, 147 .dm_rtc_start = DS1307_RTC_START, 148 .dm_rtc_size = DS1307_RTC_SIZE, 149 .dm_ch_reg = DSXXXX_SECONDS, 150 .dm_ch_value = DS1307_SECONDS_CH, 151 .dm_vbaten_reg = DSXXXX_DAY, 152 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 153 .dm_nvram_start = MCP7940_NVRAM_START, 154 .dm_nvram_size = MCP7940_NVRAM_SIZE, 155 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 156 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 157 }; 158 159 static const struct device_compatible_entry compat_data[] = { 160 { "dallas,ds1307", (uintptr_t)&ds1307_model }, 161 { "maxim,ds1307", (uintptr_t)&ds1307_model }, 162 { "i2c-ds1307", (uintptr_t)&ds1307_model }, 163 164 { "dallas,ds1339", (uintptr_t)&ds1339_model }, 165 { "maxim,ds1339", (uintptr_t)&ds1339_model }, 166 167 { "dallas,ds1340", (uintptr_t)&ds1340_model }, 168 { "maxim,ds1340", (uintptr_t)&ds1340_model }, 169 170 { "dallas,ds1672", (uintptr_t)&ds1672_model }, 171 { "maxim,ds1672", (uintptr_t)&ds1672_model }, 172 173 { "dallas,ds3231", (uintptr_t)&ds3231_model }, 174 { "maxim,ds3231", (uintptr_t)&ds3231_model }, 175 176 { "dallas,ds3232", (uintptr_t)&ds3232_model }, 177 { "maxim,ds3232", (uintptr_t)&ds3232_model }, 178 179 { "microchip,mcp7940", (uintptr_t)&mcp7940_model }, 180 181 { NULL, 0 } 182 }; 183 184 struct dsrtc_softc { 185 device_t sc_dev; 186 i2c_tag_t sc_tag; 187 uint8_t sc_address; 188 bool sc_open; 189 struct dsrtc_model sc_model; 190 struct todr_chip_handle sc_todr; 191 struct sysmon_envsys *sc_sme; 192 envsys_data_t sc_sensor; 193 }; 194 195 static void dsrtc_attach(device_t, device_t, void *); 196 static int dsrtc_match(device_t, cfdata_t, void *); 197 198 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 199 dsrtc_match, dsrtc_attach, NULL, NULL); 200 201 dev_type_open(dsrtc_open); 202 dev_type_close(dsrtc_close); 203 dev_type_read(dsrtc_read); 204 dev_type_write(dsrtc_write); 205 206 const struct cdevsw dsrtc_cdevsw = { 207 .d_open = dsrtc_open, 208 .d_close = dsrtc_close, 209 .d_read = dsrtc_read, 210 .d_write = dsrtc_write, 211 .d_ioctl = noioctl, 212 .d_stop = nostop, 213 .d_tty = notty, 214 .d_poll = nopoll, 215 .d_mmap = nommap, 216 .d_kqfilter = nokqfilter, 217 .d_discard = nodiscard, 218 .d_flag = D_OTHER 219 }; 220 221 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 222 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 223 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 224 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 225 226 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 227 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 228 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 229 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 230 231 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 232 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 233 234 static const struct dsrtc_model * 235 dsrtc_model_by_number(u_int model) 236 { 237 const struct device_compatible_entry *dce; 238 const struct dsrtc_model *dm; 239 240 /* no model given, assume it's a DS1307 */ 241 if (model == 0) 242 return &ds1307_model; 243 244 for (dce = compat_data; dce->compat != NULL; dce++) { 245 dm = (void *)dce->data; 246 if (dm->dm_model == model) 247 return dm; 248 } 249 return NULL; 250 } 251 252 static const struct dsrtc_model * 253 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 254 { 255 const struct dsrtc_model *dm = NULL; 256 const struct device_compatible_entry *dce; 257 258 if (iic_compatible_match(ia, compat_data, &dce)) 259 dm = (void *)dce->data; 260 261 return dm; 262 } 263 264 static bool 265 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 266 { 267 268 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 269 if (addr == dm->dm_valid_addrs[i]) 270 return true; 271 } 272 return false; 273 } 274 275 static int 276 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 277 { 278 struct i2c_attach_args *ia = arg; 279 const struct dsrtc_model *dm; 280 int match_result; 281 282 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 283 return match_result; 284 285 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 286 if (dm == NULL) 287 return 0; 288 289 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 290 return I2C_MATCH_ADDRESS_ONLY; 291 292 return 0; 293 } 294 295 static void 296 dsrtc_attach(device_t parent, device_t self, void *arg) 297 { 298 struct dsrtc_softc *sc = device_private(self); 299 struct i2c_attach_args *ia = arg; 300 const struct dsrtc_model *dm; 301 prop_dictionary_t dict = device_properties(self); 302 bool base_2k = FALSE; 303 304 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 305 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 306 307 if (dm == NULL) { 308 aprint_error(": unable to determine model!\n"); 309 return; 310 } 311 312 aprint_naive(": Real-time Clock%s\n", 313 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 314 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 315 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 316 317 sc->sc_tag = ia->ia_tag; 318 sc->sc_address = ia->ia_addr; 319 sc->sc_model = *dm; 320 sc->sc_dev = self; 321 sc->sc_open = 0; 322 sc->sc_todr.cookie = sc; 323 324 if (dm->dm_flags & DSRTC_FLAG_BCD) { 325 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 326 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 327 } else { 328 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 329 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 330 } 331 sc->sc_todr.todr_setwen = NULL; 332 333 #ifdef DSRTC_YEAR_START_2K 334 sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 335 #endif 336 337 prop_dictionary_get_bool(dict, "base_year_is_2000", &base_2k); 338 if (base_2k) sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 339 340 341 todr_attach(&sc->sc_todr); 342 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 343 int error; 344 345 sc->sc_sme = sysmon_envsys_create(); 346 sc->sc_sme->sme_name = device_xname(self); 347 sc->sc_sme->sme_cookie = sc; 348 sc->sc_sme->sme_refresh = dsrtc_refresh; 349 350 sc->sc_sensor.units = ENVSYS_STEMP; 351 sc->sc_sensor.state = ENVSYS_SINVALID; 352 sc->sc_sensor.flags = 0; 353 (void)strlcpy(sc->sc_sensor.desc, "temperature", 354 sizeof(sc->sc_sensor.desc)); 355 356 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 357 aprint_error_dev(self, "unable to attach sensor\n"); 358 goto bad; 359 } 360 361 error = sysmon_envsys_register(sc->sc_sme); 362 if (error) { 363 aprint_error_dev(self, 364 "error %d registering with sysmon\n", error); 365 goto bad; 366 } 367 } 368 return; 369 bad: 370 sysmon_envsys_destroy(sc->sc_sme); 371 } 372 373 /*ARGSUSED*/ 374 int 375 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 376 { 377 struct dsrtc_softc *sc; 378 379 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 380 return ENXIO; 381 382 /* XXX: Locking */ 383 if (sc->sc_open) 384 return EBUSY; 385 386 sc->sc_open = true; 387 return 0; 388 } 389 390 /*ARGSUSED*/ 391 int 392 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 393 { 394 struct dsrtc_softc *sc; 395 396 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 397 return ENXIO; 398 399 sc->sc_open = false; 400 return 0; 401 } 402 403 /*ARGSUSED*/ 404 int 405 dsrtc_read(dev_t dev, struct uio *uio, int flags) 406 { 407 struct dsrtc_softc *sc; 408 int error; 409 410 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 411 return ENXIO; 412 413 const struct dsrtc_model * const dm = &sc->sc_model; 414 if (uio->uio_offset >= dm->dm_nvram_size) 415 return EINVAL; 416 417 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 418 return error; 419 420 KASSERT(uio->uio_offset >= 0); 421 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 422 uint8_t ch, cmd; 423 const u_int a = uio->uio_offset; 424 cmd = a + dm->dm_nvram_start; 425 if ((error = iic_exec(sc->sc_tag, 426 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 427 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 428 iic_release_bus(sc->sc_tag, 0); 429 aprint_error_dev(sc->sc_dev, 430 "%s: read failed at 0x%x: %d\n", 431 __func__, a, error); 432 return error; 433 } 434 if ((error = uiomove(&ch, 1, uio)) != 0) { 435 iic_release_bus(sc->sc_tag, 0); 436 return error; 437 } 438 } 439 440 iic_release_bus(sc->sc_tag, 0); 441 442 return 0; 443 } 444 445 /*ARGSUSED*/ 446 int 447 dsrtc_write(dev_t dev, struct uio *uio, int flags) 448 { 449 struct dsrtc_softc *sc; 450 int error; 451 452 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 453 return ENXIO; 454 455 const struct dsrtc_model * const dm = &sc->sc_model; 456 if (uio->uio_offset >= dm->dm_nvram_size) 457 return EINVAL; 458 459 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 460 return error; 461 462 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 463 uint8_t cmdbuf[2]; 464 const u_int a = (int)uio->uio_offset; 465 cmdbuf[0] = a + dm->dm_nvram_start; 466 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 467 break; 468 469 if ((error = iic_exec(sc->sc_tag, 470 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 471 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 472 aprint_error_dev(sc->sc_dev, 473 "%s: write failed at 0x%x: %d\n", 474 __func__, a, error); 475 break; 476 } 477 } 478 479 iic_release_bus(sc->sc_tag, 0); 480 481 return error; 482 } 483 484 static int 485 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 486 { 487 struct dsrtc_softc *sc = ch->cookie; 488 struct clock_ymdhms check; 489 int retries; 490 491 memset(dt, 0, sizeof(*dt)); 492 memset(&check, 0, sizeof(check)); 493 494 /* 495 * Since we don't support Burst Read, we have to read the clock twice 496 * until we get two consecutive identical results. 497 */ 498 retries = 5; 499 do { 500 dsrtc_clock_read_ymdhms(sc, dt); 501 dsrtc_clock_read_ymdhms(sc, &check); 502 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 503 504 return 0; 505 } 506 507 static int 508 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 509 { 510 struct dsrtc_softc *sc = ch->cookie; 511 512 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 513 return -1; 514 515 return 0; 516 } 517 518 static int 519 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 520 { 521 struct dsrtc_model * const dm = &sc->sc_model; 522 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 523 int error; 524 525 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 526 527 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 528 aprint_error_dev(sc->sc_dev, 529 "%s: failed to acquire I2C bus: %d\n", 530 __func__, error); 531 return 0; 532 } 533 534 /* Read each RTC register in order. */ 535 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 536 cmdbuf[0] = dm->dm_rtc_start + i; 537 538 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 539 sc->sc_address, cmdbuf, 1, &bcd[i], 1, I2C_F_POLL); 540 } 541 542 /* Done with I2C */ 543 iic_release_bus(sc->sc_tag, I2C_F_POLL); 544 545 if (error != 0) { 546 aprint_error_dev(sc->sc_dev, 547 "%s: failed to read rtc at 0x%x: %d\n", 548 __func__, cmdbuf[0], error); 549 return 0; 550 } 551 552 /* 553 * Convert the RTC's register values into something useable 554 */ 555 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 556 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 557 558 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 559 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 560 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 561 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 562 dt->dt_hour += 12; 563 } else 564 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 565 DSXXXX_HOURS_24MASK); 566 567 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 568 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 569 570 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 571 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 572 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 573 else { 574 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 575 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 576 dt->dt_year += 100; 577 } 578 579 return 1; 580 } 581 582 static int 583 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 584 { 585 struct dsrtc_model * const dm = &sc->sc_model; 586 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 587 int error, offset; 588 589 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 590 591 /* 592 * Convert our time representation into something the DSXXXX 593 * can understand. 594 */ 595 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 596 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 597 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 598 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 599 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 600 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 601 602 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) { 603 offset = 2000; 604 } else { 605 offset = POSIX_BASE_YEAR; 606 } 607 608 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - offset) % 100); 609 if (dt->dt_year - offset >= 100) 610 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 611 612 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 613 aprint_error_dev(sc->sc_dev, 614 "%s: failed to acquire I2C bus: %d\n", 615 __func__, error); 616 return 0; 617 } 618 619 /* Stop the clock */ 620 cmdbuf[0] = dm->dm_ch_reg; 621 622 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 623 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 624 iic_release_bus(sc->sc_tag, I2C_F_POLL); 625 aprint_error_dev(sc->sc_dev, 626 "%s: failed to read Hold Clock: %d\n", 627 __func__, error); 628 return 0; 629 } 630 631 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 632 cmdbuf[1] &= ~dm->dm_ch_value; 633 else 634 cmdbuf[1] |= dm->dm_ch_value; 635 636 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 637 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) != 0) { 638 iic_release_bus(sc->sc_tag, I2C_F_POLL); 639 aprint_error_dev(sc->sc_dev, 640 "%s: failed to write Hold Clock: %d\n", 641 __func__, error); 642 return 0; 643 } 644 645 /* 646 * Write registers in reverse order. The last write (to the Seconds 647 * register) will undo the Clock Hold, above. 648 */ 649 uint8_t op = I2C_OP_WRITE; 650 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 651 cmdbuf[0] = dm->dm_rtc_start + i; 652 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 653 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 654 bcd[i] |= dm->dm_vbaten_value; 655 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 656 op = I2C_OP_WRITE_WITH_STOP; 657 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 658 bcd[i] |= dm->dm_ch_value; 659 } 660 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 661 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) != 0) { 662 iic_release_bus(sc->sc_tag, I2C_F_POLL); 663 aprint_error_dev(sc->sc_dev, 664 "%s: failed to write rtc at 0x%x: %d\n", 665 __func__, i, error); 666 /* XXX: Clock Hold is likely still asserted! */ 667 return 0; 668 } 669 } 670 /* 671 * If the clock hold register isn't the same register as seconds, 672 * we need to reeanble the clock. 673 */ 674 if (op != I2C_OP_WRITE_WITH_STOP) { 675 cmdbuf[0] = dm->dm_ch_reg; 676 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 677 cmdbuf[1] |= dm->dm_ch_value; 678 else 679 cmdbuf[1] &= ~dm->dm_ch_value; 680 681 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 682 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 683 I2C_F_POLL)) != 0) { 684 iic_release_bus(sc->sc_tag, I2C_F_POLL); 685 aprint_error_dev(sc->sc_dev, 686 "%s: failed to Hold Clock: %d\n", 687 __func__, error); 688 return 0; 689 } 690 } 691 692 iic_release_bus(sc->sc_tag, I2C_F_POLL); 693 694 return 1; 695 } 696 697 static int 698 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 699 { 700 struct dsrtc_softc *sc = ch->cookie; 701 struct timeval check; 702 int retries; 703 704 memset(tv, 0, sizeof(*tv)); 705 memset(&check, 0, sizeof(check)); 706 707 /* 708 * Since we don't support Burst Read, we have to read the clock twice 709 * until we get two consecutive identical results. 710 */ 711 retries = 5; 712 do { 713 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 714 dsrtc_clock_read_timeval(sc, &check.tv_sec); 715 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 716 717 return 0; 718 } 719 720 static int 721 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 722 { 723 struct dsrtc_softc *sc = ch->cookie; 724 725 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 726 return -1; 727 728 return 0; 729 } 730 731 /* 732 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 733 * it, since some I2C controllers don't support anything other than single-byte 734 * transfers. 735 */ 736 static int 737 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 738 { 739 const struct dsrtc_model * const dm = &sc->sc_model; 740 uint8_t buf[4]; 741 int error; 742 743 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 744 aprint_error_dev(sc->sc_dev, 745 "%s: failed to acquire I2C bus: %d\n", 746 __func__, error); 747 return 0; 748 } 749 750 /* read all registers: */ 751 uint8_t reg = dm->dm_rtc_start; 752 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 753 ®, 1, buf, 4, I2C_F_POLL); 754 755 /* Done with I2C */ 756 iic_release_bus(sc->sc_tag, I2C_F_POLL); 757 758 if (error != 0) { 759 aprint_error_dev(sc->sc_dev, 760 "%s: failed to read rtc at 0x%x: %d\n", 761 __func__, reg, error); 762 return 0; 763 } 764 765 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 766 *tp = v; 767 768 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 769 __func__, v); 770 771 return 1; 772 } 773 774 static int 775 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 776 { 777 const struct dsrtc_model * const dm = &sc->sc_model; 778 size_t buflen = dm->dm_rtc_size + 2; 779 /* XXX: the biggest dm_rtc_size we have now is 7, so we should be ok */ 780 uint8_t buf[16]; 781 int error; 782 783 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 784 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 785 786 buf[0] = dm->dm_rtc_start; 787 buf[1] = (t >> 0) & 0xff; 788 buf[2] = (t >> 8) & 0xff; 789 buf[3] = (t >> 16) & 0xff; 790 buf[4] = (t >> 24) & 0xff; 791 buf[5] = 0; 792 793 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 794 aprint_error_dev(sc->sc_dev, 795 "%s: failed to acquire I2C bus: %d\n", 796 __func__, error); 797 return 0; 798 } 799 800 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 801 &buf, buflen, NULL, 0, I2C_F_POLL); 802 803 /* Done with I2C */ 804 iic_release_bus(sc->sc_tag, I2C_F_POLL); 805 806 /* send data */ 807 if (error != 0) { 808 aprint_error_dev(sc->sc_dev, 809 "%s: failed to set time: %d\n", 810 __func__, error); 811 return 0; 812 } 813 814 return 1; 815 } 816 817 static int 818 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 819 { 820 int error, tc; 821 uint8_t reg = DS3232_TEMP_MSB; 822 uint8_t buf[2]; 823 824 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 825 return ENOTSUP; 826 827 if ((error = iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) != 0) { 828 aprint_error_dev(sc->sc_dev, 829 "%s: failed to acquire I2C bus: %d\n", 830 __func__, error); 831 return 0; 832 } 833 834 /* read temperature registers: */ 835 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 836 ®, 1, buf, 2, I2C_F_POLL); 837 838 /* Done with I2C */ 839 iic_release_bus(sc->sc_tag, I2C_F_POLL); 840 841 if (error != 0) { 842 aprint_error_dev(sc->sc_dev, 843 "%s: failed to read temperature: %d\n", 844 __func__, error); 845 return 0; 846 } 847 848 /* convert to microkelvin */ 849 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 850 *temp = tc + 273150000; 851 return 1; 852 } 853 854 static void 855 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 856 { 857 struct dsrtc_softc *sc = sme->sme_cookie; 858 uint32_t temp = 0; /* XXX gcc */ 859 860 if (dsrtc_read_temp(sc, &temp) == 0) { 861 edata->state = ENVSYS_SINVALID; 862 return; 863 } 864 865 edata->value_cur = temp; 866 867 edata->state = ENVSYS_SVALID; 868 } 869
Indexes created Thu Oct 02 10:09:58 GMT 2025