ds1307.c revision 1.42
1 /* $NetBSD: ds1307.c,v 1.42 2025/09/07 21:45:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.42 2025/09/07 21:45:15 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/ds1307reg.h> 54 #include <dev/sysmon/sysmonvar.h> 55 56 #include "ioconf.h" 57 #include "opt_dsrtc.h" 58 59 struct dsrtc_model { 60 const i2c_addr_t *dm_valid_addrs; 61 uint16_t dm_model; 62 uint8_t dm_ch_reg; 63 uint8_t dm_ch_value; 64 uint8_t dm_vbaten_reg; 65 uint8_t dm_vbaten_value; 66 uint8_t dm_rtc_start; 67 uint8_t dm_rtc_size; 68 uint8_t dm_nvram_start; 69 uint8_t dm_nvram_size; 70 uint8_t dm_flags; 71 #define DSRTC_FLAG_CLOCK_HOLD 0x01 72 #define DSRTC_FLAG_BCD 0x02 73 #define DSRTC_FLAG_TEMP 0x04 74 #define DSRTC_FLAG_VBATEN 0x08 75 #define DSRTC_FLAG_YEAR_START_2K 0x10 76 #define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 77 }; 78 79 static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 80 static const struct dsrtc_model ds1307_model = { 81 .dm_valid_addrs = ds1307_valid_addrs, 82 .dm_model = 1307, 83 .dm_ch_reg = DSXXXX_SECONDS, 84 .dm_ch_value = DS1307_SECONDS_CH, 85 .dm_rtc_start = DS1307_RTC_START, 86 .dm_rtc_size = DS1307_RTC_SIZE, 87 .dm_nvram_start = DS1307_NVRAM_START, 88 .dm_nvram_size = DS1307_NVRAM_SIZE, 89 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 90 }; 91 92 static const struct dsrtc_model ds1339_model = { 93 .dm_valid_addrs = ds1307_valid_addrs, 94 .dm_model = 1339, 95 .dm_rtc_start = DS1339_RTC_START, 96 .dm_rtc_size = DS1339_RTC_SIZE, 97 .dm_flags = DSRTC_FLAG_BCD, 98 }; 99 100 static const struct dsrtc_model ds1340_model = { 101 .dm_valid_addrs = ds1307_valid_addrs, 102 .dm_model = 1340, 103 .dm_ch_reg = DSXXXX_SECONDS, 104 .dm_ch_value = DS1340_SECONDS_EOSC, 105 .dm_rtc_start = DS1340_RTC_START, 106 .dm_rtc_size = DS1340_RTC_SIZE, 107 .dm_flags = DSRTC_FLAG_BCD, 108 }; 109 110 static const struct dsrtc_model ds1672_model = { 111 .dm_valid_addrs = ds1307_valid_addrs, 112 .dm_model = 1672, 113 .dm_rtc_start = DS1672_RTC_START, 114 .dm_rtc_size = DS1672_RTC_SIZE, 115 .dm_ch_reg = DS1672_CONTROL, 116 .dm_ch_value = DS1672_CONTROL_CH, 117 .dm_flags = 0, 118 }; 119 120 static const struct dsrtc_model ds3231_model = { 121 .dm_valid_addrs = ds1307_valid_addrs, 122 .dm_model = 3231, 123 .dm_rtc_start = DS3232_RTC_START, 124 .dm_rtc_size = DS3232_RTC_SIZE, 125 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 126 }; 127 128 static const struct dsrtc_model ds3232_model = { 129 .dm_valid_addrs = ds1307_valid_addrs, 130 .dm_model = 3232, 131 .dm_rtc_start = DS3232_RTC_START, 132 .dm_rtc_size = DS3232_RTC_SIZE, 133 .dm_nvram_start = DS3232_NVRAM_START, 134 .dm_nvram_size = DS3232_NVRAM_SIZE, 135 /* 136 * XXX 137 * the DS3232 likely has the temperature sensor too but I can't 138 * easily verify or test that right now 139 */ 140 .dm_flags = DSRTC_FLAG_BCD, 141 }; 142 143 static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 144 static const struct dsrtc_model mcp7940_model = { 145 .dm_valid_addrs = mcp7940_valid_addrs, 146 .dm_model = 7940, 147 .dm_rtc_start = DS1307_RTC_START, 148 .dm_rtc_size = DS1307_RTC_SIZE, 149 .dm_ch_reg = DSXXXX_SECONDS, 150 .dm_ch_value = DS1307_SECONDS_CH, 151 .dm_vbaten_reg = DSXXXX_DAY, 152 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 153 .dm_nvram_start = MCP7940_NVRAM_START, 154 .dm_nvram_size = MCP7940_NVRAM_SIZE, 155 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 156 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 157 }; 158 159 static const struct device_compatible_entry compat_data[] = { 160 { .compat = "dallas,ds1307", .data = &ds1307_model }, 161 { .compat = "maxim,ds1307", .data = &ds1307_model }, 162 { .compat = "i2c-ds1307", .data = &ds1307_model }, 163 164 { .compat = "dallas,ds1339", .data = &ds1339_model }, 165 { .compat = "maxim,ds1339", .data = &ds1339_model }, 166 167 { .compat = "dallas,ds1340", .data = &ds1340_model }, 168 { .compat = "maxim,ds1340", .data = &ds1340_model }, 169 170 { .compat = "dallas,ds1672", .data = &ds1672_model }, 171 { .compat = "maxim,ds1672", .data = &ds1672_model }, 172 173 { .compat = "dallas,ds3231", .data = &ds3231_model }, 174 { .compat = "maxim,ds3231", .data = &ds3231_model }, 175 176 { .compat = "dallas,ds3232", .data = &ds3232_model }, 177 { .compat = "maxim,ds3232", .data = &ds3232_model }, 178 179 { .compat = "microchip,mcp7940", .data = &mcp7940_model }, 180 181 DEVICE_COMPAT_EOL 182 }; 183 184 struct dsrtc_softc { 185 device_t sc_dev; 186 i2c_tag_t sc_tag; 187 uint8_t sc_address; 188 bool sc_open; 189 struct dsrtc_model sc_model; 190 struct todr_chip_handle sc_todr; 191 struct sysmon_envsys *sc_sme; 192 envsys_data_t sc_sensor; 193 }; 194 195 static void dsrtc_attach(device_t, device_t, void *); 196 static int dsrtc_match(device_t, cfdata_t, void *); 197 198 CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 199 dsrtc_match, dsrtc_attach, NULL, NULL); 200 201 dev_type_open(dsrtc_open); 202 dev_type_close(dsrtc_close); 203 dev_type_read(dsrtc_read); 204 dev_type_write(dsrtc_write); 205 206 const struct cdevsw dsrtc_cdevsw = { 207 .d_open = dsrtc_open, 208 .d_close = dsrtc_close, 209 .d_read = dsrtc_read, 210 .d_write = dsrtc_write, 211 .d_ioctl = noioctl, 212 .d_stop = nostop, 213 .d_tty = notty, 214 .d_poll = nopoll, 215 .d_mmap = nommap, 216 .d_kqfilter = nokqfilter, 217 .d_discard = nodiscard, 218 .d_flag = D_OTHER 219 }; 220 221 static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 222 static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 223 static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 224 static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 225 226 static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 227 static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 228 static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 229 static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 230 231 static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 232 static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 233 234 static const struct dsrtc_model * 235 dsrtc_model_by_number(u_int model) 236 { 237 const struct device_compatible_entry *dce; 238 const struct dsrtc_model *dm; 239 240 /* no model given, assume it's a DS1307 */ 241 if (model == 0) 242 return &ds1307_model; 243 244 for (dce = compat_data; dce->compat != NULL; dce++) { 245 dm = dce->data; 246 if (dm->dm_model == model) 247 return dm; 248 } 249 return NULL; 250 } 251 252 static const struct dsrtc_model * 253 dsrtc_model_by_compat(const struct i2c_attach_args *ia) 254 { 255 const struct dsrtc_model *dm = NULL; 256 const struct device_compatible_entry *dce; 257 258 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL) 259 dm = dce->data; 260 261 return dm; 262 } 263 264 static bool 265 dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 266 { 267 268 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 269 if (addr == dm->dm_valid_addrs[i]) 270 return true; 271 } 272 return false; 273 } 274 275 static int 276 dsrtc_match(device_t parent, cfdata_t cf, void *arg) 277 { 278 struct i2c_attach_args *ia = arg; 279 const struct dsrtc_model *dm; 280 int match_result; 281 282 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 283 return match_result; 284 285 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 286 if (dm == NULL) 287 return 0; 288 289 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 290 return I2C_MATCH_ADDRESS_ONLY; 291 292 return 0; 293 } 294 295 static void 296 dsrtc_attach(device_t parent, device_t self, void *arg) 297 { 298 struct dsrtc_softc *sc = device_private(self); 299 struct i2c_attach_args *ia = arg; 300 const struct dsrtc_model *dm; 301 prop_dictionary_t dict = device_properties(self); 302 bool base_2k = FALSE; 303 304 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 305 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 306 307 if (dm == NULL) { 308 aprint_error(": unable to determine model!\n"); 309 return; 310 } 311 312 aprint_naive(": Real-time Clock%s\n", 313 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 314 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 315 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 316 317 sc->sc_tag = ia->ia_tag; 318 sc->sc_address = ia->ia_addr; 319 sc->sc_model = *dm; 320 sc->sc_dev = self; 321 sc->sc_open = 0; 322 sc->sc_todr.todr_dev = self; 323 324 if (dm->dm_flags & DSRTC_FLAG_BCD) { 325 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 326 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 327 } else { 328 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 329 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 330 } 331 332 #ifdef DSRTC_YEAR_START_2K 333 sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 334 #endif 335 336 prop_dictionary_get_bool(dict, "base_year_is_2000", &base_2k); 337 if (base_2k) sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 338 339 340 todr_attach(&sc->sc_todr); 341 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 342 int error; 343 344 sc->sc_sme = sysmon_envsys_create(); 345 sc->sc_sme->sme_name = device_xname(self); 346 sc->sc_sme->sme_cookie = sc; 347 sc->sc_sme->sme_refresh = dsrtc_refresh; 348 349 sc->sc_sensor.units = ENVSYS_STEMP; 350 sc->sc_sensor.state = ENVSYS_SINVALID; 351 sc->sc_sensor.flags = 0; 352 (void)strlcpy(sc->sc_sensor.desc, "temperature", 353 sizeof(sc->sc_sensor.desc)); 354 355 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 356 aprint_error_dev(self, "unable to attach sensor\n"); 357 goto bad; 358 } 359 360 error = sysmon_envsys_register(sc->sc_sme); 361 if (error) { 362 aprint_error_dev(self, 363 "error %d registering with sysmon\n", error); 364 goto bad; 365 } 366 } 367 return; 368 bad: 369 sysmon_envsys_destroy(sc->sc_sme); 370 } 371 372 /*ARGSUSED*/ 373 int 374 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 375 { 376 struct dsrtc_softc *sc; 377 378 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 379 return ENXIO; 380 381 /* XXX: Locking */ 382 if (sc->sc_open) 383 return EBUSY; 384 385 sc->sc_open = true; 386 return 0; 387 } 388 389 /*ARGSUSED*/ 390 int 391 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 392 { 393 struct dsrtc_softc *sc; 394 395 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 396 return ENXIO; 397 398 sc->sc_open = false; 399 return 0; 400 } 401 402 /*ARGSUSED*/ 403 int 404 dsrtc_read(dev_t dev, struct uio *uio, int flags) 405 { 406 struct dsrtc_softc *sc; 407 int error; 408 409 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 410 return ENXIO; 411 412 const struct dsrtc_model * const dm = &sc->sc_model; 413 if (uio->uio_offset < 0 || uio->uio_offset >= dm->dm_nvram_size) 414 return EINVAL; 415 416 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 417 return error; 418 419 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 420 uint8_t ch, cmd; 421 const u_int a = uio->uio_offset; 422 cmd = a + dm->dm_nvram_start; 423 if ((error = iic_exec(sc->sc_tag, 424 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 425 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 426 iic_release_bus(sc->sc_tag, 0); 427 aprint_error_dev(sc->sc_dev, 428 "%s: read failed at 0x%x: %d\n", 429 __func__, a, error); 430 return error; 431 } 432 if ((error = uiomove(&ch, 1, uio)) != 0) { 433 iic_release_bus(sc->sc_tag, 0); 434 return error; 435 } 436 } 437 438 iic_release_bus(sc->sc_tag, 0); 439 440 return 0; 441 } 442 443 /*ARGSUSED*/ 444 int 445 dsrtc_write(dev_t dev, struct uio *uio, int flags) 446 { 447 struct dsrtc_softc *sc; 448 int error; 449 450 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 451 return ENXIO; 452 453 const struct dsrtc_model * const dm = &sc->sc_model; 454 if (uio->uio_offset >= dm->dm_nvram_size) 455 return EINVAL; 456 457 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 458 return error; 459 460 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 461 uint8_t cmdbuf[2]; 462 const u_int a = (int)uio->uio_offset; 463 cmdbuf[0] = a + dm->dm_nvram_start; 464 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 465 break; 466 467 if ((error = iic_exec(sc->sc_tag, 468 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 469 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 470 aprint_error_dev(sc->sc_dev, 471 "%s: write failed at 0x%x: %d\n", 472 __func__, a, error); 473 break; 474 } 475 } 476 477 iic_release_bus(sc->sc_tag, 0); 478 479 return error; 480 } 481 482 static int 483 dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 484 { 485 struct dsrtc_softc *sc = device_private(ch->todr_dev); 486 struct clock_ymdhms check; 487 int retries; 488 489 memset(dt, 0, sizeof(*dt)); 490 memset(&check, 0, sizeof(check)); 491 492 /* 493 * Since we don't support Burst Read, we have to read the clock twice 494 * until we get two consecutive identical results. 495 */ 496 retries = 5; 497 do { 498 dsrtc_clock_read_ymdhms(sc, dt); 499 dsrtc_clock_read_ymdhms(sc, &check); 500 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 501 502 return 0; 503 } 504 505 static int 506 dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 507 { 508 struct dsrtc_softc *sc = device_private(ch->todr_dev); 509 510 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 511 return -1; 512 513 return 0; 514 } 515 516 static int 517 dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 518 { 519 struct dsrtc_model * const dm = &sc->sc_model; 520 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 521 int error; 522 523 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 524 525 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 526 aprint_error_dev(sc->sc_dev, 527 "%s: failed to acquire I2C bus: %d\n", 528 __func__, error); 529 return 0; 530 } 531 532 /* Read each RTC register in order. */ 533 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 534 cmdbuf[0] = dm->dm_rtc_start + i; 535 536 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 537 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0); 538 } 539 540 /* Done with I2C */ 541 iic_release_bus(sc->sc_tag, 0); 542 543 if (error != 0) { 544 aprint_error_dev(sc->sc_dev, 545 "%s: failed to read rtc at 0x%x: %d\n", 546 __func__, cmdbuf[0], error); 547 return 0; 548 } 549 550 /* 551 * Convert the RTC's register values into something useable 552 */ 553 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 554 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 555 556 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 557 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 558 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 559 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 560 dt->dt_hour += 12; 561 } else 562 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 563 DSXXXX_HOURS_24MASK); 564 565 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 566 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 567 568 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 569 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 570 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 571 else { 572 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 573 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 574 dt->dt_year += 100; 575 } 576 577 return 1; 578 } 579 580 static int 581 dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 582 { 583 struct dsrtc_model * const dm = &sc->sc_model; 584 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 585 int error, offset; 586 587 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 588 589 /* 590 * Convert our time representation into something the DSXXXX 591 * can understand. 592 */ 593 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 594 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 595 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 596 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 597 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 598 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 599 600 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) { 601 offset = 2000; 602 } else { 603 offset = POSIX_BASE_YEAR; 604 } 605 606 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - offset) % 100); 607 if (dt->dt_year - offset >= 100) 608 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 609 610 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 611 aprint_error_dev(sc->sc_dev, 612 "%s: failed to acquire I2C bus: %d\n", 613 __func__, error); 614 return 0; 615 } 616 617 /* Stop the clock */ 618 cmdbuf[0] = dm->dm_ch_reg; 619 620 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 621 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 622 iic_release_bus(sc->sc_tag, 0); 623 aprint_error_dev(sc->sc_dev, 624 "%s: failed to read Hold Clock: %d\n", 625 __func__, error); 626 return 0; 627 } 628 629 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 630 cmdbuf[1] &= ~dm->dm_ch_value; 631 else 632 cmdbuf[1] |= dm->dm_ch_value; 633 634 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 635 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 636 iic_release_bus(sc->sc_tag, 0); 637 aprint_error_dev(sc->sc_dev, 638 "%s: failed to write Hold Clock: %d\n", 639 __func__, error); 640 return 0; 641 } 642 643 /* 644 * Write registers in reverse order. The last write (to the Seconds 645 * register) will undo the Clock Hold, above. 646 */ 647 uint8_t op = I2C_OP_WRITE; 648 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 649 cmdbuf[0] = dm->dm_rtc_start + i; 650 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 651 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 652 bcd[i] |= dm->dm_vbaten_value; 653 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 654 op = I2C_OP_WRITE_WITH_STOP; 655 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 656 bcd[i] |= dm->dm_ch_value; 657 } 658 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 659 cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 660 iic_release_bus(sc->sc_tag, 0); 661 aprint_error_dev(sc->sc_dev, 662 "%s: failed to write rtc at 0x%x: %d\n", 663 __func__, i, error); 664 /* XXX: Clock Hold is likely still asserted! */ 665 return 0; 666 } 667 } 668 /* 669 * If the clock hold register isn't the same register as seconds, 670 * we need to reenable the clock. 671 */ 672 if (op != I2C_OP_WRITE_WITH_STOP) { 673 cmdbuf[0] = dm->dm_ch_reg; 674 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 675 cmdbuf[1] |= dm->dm_ch_value; 676 else 677 cmdbuf[1] &= ~dm->dm_ch_value; 678 679 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 680 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 681 iic_release_bus(sc->sc_tag, 0); 682 aprint_error_dev(sc->sc_dev, 683 "%s: failed to Hold Clock: %d\n", 684 __func__, error); 685 return 0; 686 } 687 } 688 689 iic_release_bus(sc->sc_tag, 0); 690 691 return 1; 692 } 693 694 static int 695 dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 696 { 697 struct dsrtc_softc *sc = device_private(ch->todr_dev); 698 struct timeval check; 699 int retries; 700 701 memset(tv, 0, sizeof(*tv)); 702 memset(&check, 0, sizeof(check)); 703 704 /* 705 * Since we don't support Burst Read, we have to read the clock twice 706 * until we get two consecutive identical results. 707 */ 708 retries = 5; 709 do { 710 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 711 dsrtc_clock_read_timeval(sc, &check.tv_sec); 712 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 713 714 return 0; 715 } 716 717 static int 718 dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 719 { 720 struct dsrtc_softc *sc = device_private(ch->todr_dev); 721 722 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 723 return -1; 724 725 return 0; 726 } 727 728 /* 729 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 730 * it, since some I2C controllers don't support anything other than single-byte 731 * transfers. 732 */ 733 static int 734 dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 735 { 736 const struct dsrtc_model * const dm = &sc->sc_model; 737 uint8_t buf[4]; 738 int error; 739 740 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 741 aprint_error_dev(sc->sc_dev, 742 "%s: failed to acquire I2C bus: %d\n", 743 __func__, error); 744 return 0; 745 } 746 747 /* read all registers: */ 748 uint8_t reg = dm->dm_rtc_start; 749 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 750 ®, 1, buf, 4, 0); 751 752 /* Done with I2C */ 753 iic_release_bus(sc->sc_tag, 0); 754 755 if (error != 0) { 756 aprint_error_dev(sc->sc_dev, 757 "%s: failed to read rtc at 0x%x: %d\n", 758 __func__, reg, error); 759 return 0; 760 } 761 762 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 763 *tp = v; 764 765 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 766 __func__, v); 767 768 return 1; 769 } 770 771 static int 772 dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 773 { 774 const struct dsrtc_model * const dm = &sc->sc_model; 775 size_t buflen = dm->dm_rtc_size + 2; 776 /* XXX: the biggest dm_rtc_size we have now is 7, so we should be ok */ 777 uint8_t buf[16]; 778 int error; 779 780 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 781 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 782 783 buf[0] = dm->dm_rtc_start; 784 buf[1] = (t >> 0) & 0xff; 785 buf[2] = (t >> 8) & 0xff; 786 buf[3] = (t >> 16) & 0xff; 787 buf[4] = (t >> 24) & 0xff; 788 buf[5] = 0; 789 790 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 791 aprint_error_dev(sc->sc_dev, 792 "%s: failed to acquire I2C bus: %d\n", 793 __func__, error); 794 return 0; 795 } 796 797 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 798 &buf, buflen, NULL, 0, 0); 799 800 /* Done with I2C */ 801 iic_release_bus(sc->sc_tag, 0); 802 803 /* send data */ 804 if (error != 0) { 805 aprint_error_dev(sc->sc_dev, 806 "%s: failed to set time: %d\n", 807 __func__, error); 808 return 0; 809 } 810 811 return 1; 812 } 813 814 static int 815 dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 816 { 817 int error, tc; 818 uint8_t reg = DS3232_TEMP_MSB; 819 uint8_t buf[2]; 820 821 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 822 return ENOTSUP; 823 824 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 825 aprint_error_dev(sc->sc_dev, 826 "%s: failed to acquire I2C bus: %d\n", 827 __func__, error); 828 return 0; 829 } 830 831 /* read temperature registers: */ 832 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 833 ®, 1, buf, 2, 0); 834 835 /* Done with I2C */ 836 iic_release_bus(sc->sc_tag, 0); 837 838 if (error != 0) { 839 aprint_error_dev(sc->sc_dev, 840 "%s: failed to read temperature: %d\n", 841 __func__, error); 842 return 0; 843 } 844 845 /* convert to microkelvin */ 846 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 847 *temp = tc + 273150000; 848 return 1; 849 } 850 851 static void 852 dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 853 { 854 struct dsrtc_softc *sc = sme->sme_cookie; 855 uint32_t temp = 0; /* XXX gcc */ 856 857 if (dsrtc_read_temp(sc, &temp) == 0) { 858 edata->state = ENVSYS_SINVALID; 859 return; 860 } 861 862 edata->value_cur = temp; 863 864 edata->state = ENVSYS_SVALID; 865 } 866
Indexes created Thu Oct 02 10:09:58 GMT 2025