ds1307.c revision 1.6
1 /* $NetBSD: ds1307.c,v 1.6 2006/09/04 23:45:30 gdamore Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/fcntl.h> 43 #include <sys/uio.h> 44 #include <sys/conf.h> 45 #include <sys/event.h> 46 47 #include <dev/clock_subr.h> 48 49 #include <dev/i2c/i2cvar.h> 50 #include <dev/i2c/ds1307reg.h> 51 52 struct dsrtc_softc { 53 struct device sc_dev; 54 i2c_tag_t sc_tag; 55 int sc_address; 56 int sc_open; 57 struct todr_chip_handle sc_todr; 58 }; 59 60 static void dsrtc_attach(struct device *, struct device *, void *); 61 static int dsrtc_match(struct device *, struct cfdata *, void *); 62 63 CFATTACH_DECL(dsrtc, sizeof(struct dsrtc_softc), 64 dsrtc_match, dsrtc_attach, NULL, NULL); 65 extern struct cfdriver dsrtc_cd; 66 67 dev_type_open(dsrtc_open); 68 dev_type_close(dsrtc_close); 69 dev_type_read(dsrtc_read); 70 dev_type_write(dsrtc_write); 71 72 const struct cdevsw dsrtc_cdevsw = { 73 dsrtc_open, dsrtc_close, dsrtc_read, dsrtc_write, noioctl, 74 nostop, notty, nopoll, nommap, nokqfilter 75 }; 76 77 static int dsrtc_clock_read(struct dsrtc_softc *, struct clock_ymdhms *); 78 static int dsrtc_clock_write(struct dsrtc_softc *, struct clock_ymdhms *); 79 static int dsrtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 80 static int dsrtc_settime(struct todr_chip_handle *, volatile struct timeval *); 81 82 static int 83 dsrtc_match(struct device *parent, struct cfdata *cf, void *arg) 84 { 85 struct i2c_attach_args *ia = arg; 86 87 if (ia->ia_addr == DS1307_ADDR) 88 return (1); 89 90 return (0); 91 } 92 93 static void 94 dsrtc_attach(struct device *parent, struct device *self, void *arg) 95 { 96 struct dsrtc_softc *sc = device_private(self); 97 struct i2c_attach_args *ia = arg; 98 99 aprint_naive(": Real-time Clock/NVRAM\n"); 100 aprint_normal(": DS1307 Real-time Clock/NVRAM\n"); 101 102 sc->sc_tag = ia->ia_tag; 103 sc->sc_address = ia->ia_addr; 104 sc->sc_open = 0; 105 sc->sc_todr.cookie = sc; 106 sc->sc_todr.todr_gettime = dsrtc_gettime; 107 sc->sc_todr.todr_settime = dsrtc_settime; 108 sc->sc_todr.todr_setwen = NULL; 109 110 todr_attach(&sc->sc_todr); 111 } 112 113 /*ARGSUSED*/ 114 int 115 dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 116 { 117 struct dsrtc_softc *sc; 118 119 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 120 return (ENXIO); 121 122 /* XXX: Locking */ 123 124 if (sc->sc_open) 125 return (EBUSY); 126 127 sc->sc_open = 1; 128 return (0); 129 } 130 131 /*ARGSUSED*/ 132 int 133 dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 134 { 135 struct dsrtc_softc *sc; 136 137 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 138 return (ENXIO); 139 140 sc->sc_open = 0; 141 return (0); 142 } 143 144 /*ARGSUSED*/ 145 int 146 dsrtc_read(dev_t dev, struct uio *uio, int flags) 147 { 148 struct dsrtc_softc *sc; 149 u_int8_t ch, cmdbuf[1]; 150 int a, error; 151 152 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 153 return (ENXIO); 154 155 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 156 return (EINVAL); 157 158 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 159 return (error); 160 161 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 162 a = (int)uio->uio_offset; 163 cmdbuf[0] = a + DS1307_NVRAM_START; 164 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 165 sc->sc_address, cmdbuf, 1, 166 &ch, 1, 0)) != 0) { 167 iic_release_bus(sc->sc_tag, 0); 168 printf("%s: dsrtc_read: read failed at 0x%x\n", 169 sc->sc_dev.dv_xname, a); 170 return (error); 171 } 172 if ((error = uiomove(&ch, 1, uio)) != 0) { 173 iic_release_bus(sc->sc_tag, 0); 174 return (error); 175 } 176 } 177 178 iic_release_bus(sc->sc_tag, 0); 179 180 return (0); 181 } 182 183 /*ARGSUSED*/ 184 int 185 dsrtc_write(dev_t dev, struct uio *uio, int flags) 186 { 187 struct dsrtc_softc *sc; 188 u_int8_t cmdbuf[2]; 189 int a, error; 190 191 if ((sc = device_lookup(&dsrtc_cd, minor(dev))) == NULL) 192 return (ENXIO); 193 194 if (uio->uio_offset >= DS1307_NVRAM_SIZE) 195 return (EINVAL); 196 197 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 198 return (error); 199 200 while (uio->uio_resid && uio->uio_offset < DS1307_NVRAM_SIZE) { 201 a = (int)uio->uio_offset; 202 cmdbuf[0] = a + DS1307_NVRAM_START; 203 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 204 break; 205 206 if ((error = iic_exec(sc->sc_tag, 207 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 208 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 209 printf("%s: dsrtc_write: write failed at 0x%x\n", 210 sc->sc_dev.dv_xname, a); 211 break; 212 } 213 } 214 215 iic_release_bus(sc->sc_tag, 0); 216 217 return (error); 218 } 219 220 static int 221 dsrtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 222 { 223 struct dsrtc_softc *sc = ch->cookie; 224 struct clock_ymdhms dt, check; 225 int retries; 226 227 memset(&dt, 0, sizeof(dt)); 228 memset(&check, 0, sizeof(check)); 229 230 /* 231 * Since we don't support Burst Read, we have to read the clock twice 232 * until we get two consecutive identical results. 233 */ 234 retries = 5; 235 do { 236 dsrtc_clock_read(sc, &dt); 237 dsrtc_clock_read(sc, &check); 238 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 239 240 tv->tv_sec = clock_ymdhms_to_secs(&dt); 241 tv->tv_usec = 0; 242 243 return (0); 244 } 245 246 static int 247 dsrtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 248 { 249 struct dsrtc_softc *sc = ch->cookie; 250 struct clock_ymdhms dt; 251 252 clock_secs_to_ymdhms(tv->tv_sec, &dt); 253 254 if (dsrtc_clock_write(sc, &dt) == 0) 255 return (-1); 256 257 return (0); 258 } 259 260 static int 261 dsrtc_clock_read(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 262 { 263 u_int8_t bcd[DS1307_NRTC_REGS], cmdbuf[1]; 264 int i; 265 266 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 267 printf("%s: dsrtc_clock_read: failed to acquire I2C bus\n", 268 sc->sc_dev.dv_xname); 269 return (0); 270 } 271 272 /* Read each RTC register in order. */ 273 for (i = DS1307_SECONDS; i < DS1307_NRTC_REGS; i++) { 274 cmdbuf[0] = i; 275 276 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 277 sc->sc_address, cmdbuf, 1, 278 &bcd[i], 1, I2C_F_POLL)) { 279 iic_release_bus(sc->sc_tag, I2C_F_POLL); 280 printf("%s: dsrtc_clock_read: failed to read rtc " 281 "at 0x%x\n", sc->sc_dev.dv_xname, i); 282 return (0); 283 } 284 } 285 286 /* Done with I2C */ 287 iic_release_bus(sc->sc_tag, I2C_F_POLL); 288 289 /* 290 * Convert the DS1307's register values into something useable 291 */ 292 dt->dt_sec = FROMBCD(bcd[DS1307_SECONDS] & DS1307_SECONDS_MASK); 293 dt->dt_min = FROMBCD(bcd[DS1307_MINUTES] & DS1307_MINUTES_MASK); 294 295 if ((bcd[DS1307_HOURS] & DS1307_HOURS_24HRS) == 0) { 296 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 297 DS1307_HOURS_12MASK); 298 if (bcd[DS1307_HOURS] & DS1307_HOURS_12HRS_PM) 299 dt->dt_hour += 12; 300 } else { 301 dt->dt_hour = FROMBCD(bcd[DS1307_HOURS] & 302 DS1307_HOURS_24MASK); 303 } 304 305 dt->dt_day = FROMBCD(bcd[DS1307_DATE] & DS1307_DATE_MASK); 306 dt->dt_mon = FROMBCD(bcd[DS1307_MONTH] & DS1307_MONTH_MASK); 307 308 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 309 dt->dt_year = FROMBCD(bcd[DS1307_YEAR]) + POSIX_BASE_YEAR; 310 311 return (1); 312 } 313 314 static int 315 dsrtc_clock_write(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 316 { 317 uint8_t bcd[DS1307_NRTC_REGS], cmdbuf[2]; 318 int i; 319 320 /* 321 * Convert our time representation into something the DS1307 322 * can understand. 323 */ 324 bcd[DS1307_SECONDS] = TOBCD(dt->dt_sec); 325 bcd[DS1307_MINUTES] = TOBCD(dt->dt_min); 326 bcd[DS1307_HOURS] = TOBCD(dt->dt_hour) | DS1307_HOURS_24HRS; 327 bcd[DS1307_DATE] = TOBCD(dt->dt_day); 328 bcd[DS1307_DAY] = TOBCD(dt->dt_wday); 329 bcd[DS1307_MONTH] = TOBCD(dt->dt_mon); 330 bcd[DS1307_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 331 332 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 333 printf("%s: dsrtc_clock_write: failed to acquire I2C bus\n", 334 sc->sc_dev.dv_xname); 335 return (0); 336 } 337 338 /* Stop the clock */ 339 cmdbuf[0] = DS1307_SECONDS; 340 cmdbuf[1] = DS1307_SECONDS_CH; 341 342 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 343 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 344 iic_release_bus(sc->sc_tag, I2C_F_POLL); 345 printf("%s: dsrtc_clock_write: failed to Hold Clock\n", 346 sc->sc_dev.dv_xname); 347 return (0); 348 } 349 350 /* 351 * Write registers in reverse order. The last write (to the Seconds 352 * register) will undo the Clock Hold, above. 353 */ 354 for (i = DS1307_NRTC_REGS - 1; i >= 0; i--) { 355 cmdbuf[0] = i; 356 if (iic_exec(sc->sc_tag, 357 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 358 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 359 I2C_F_POLL)) { 360 iic_release_bus(sc->sc_tag, I2C_F_POLL); 361 printf("%s: dsrtc_clock_write: failed to write rtc " 362 " at 0x%x\n", sc->sc_dev.dv_xname, i); 363 /* XXX: Clock Hold is likely still asserted! */ 364 return (0); 365 } 366 } 367 368 iic_release_bus(sc->sc_tag, I2C_F_POLL); 369 370 return (1); 371 } 372
Indexes created Thu Oct 02 10:09:58 GMT 2025