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gttwsi_core.c revision 1.1
      1  1.1  matt /*	$NetBSD: gttwsi_core.c,v 1.1 2013/09/06 00:56:12 matt Exp $	*/
      2  1.1  matt /*
      3  1.1  matt  * Copyright (c) 2008 Eiji Kawauchi.
      4  1.1  matt  * All rights reserved.
      5  1.1  matt  *
      6  1.1  matt  * Redistribution and use in source and binary forms, with or without
      7  1.1  matt  * modification, are permitted provided that the following conditions
      8  1.1  matt  * are met:
      9  1.1  matt  * 1. Redistributions of source code must retain the above copyright
     10  1.1  matt  *    notice, this list of conditions and the following disclaimer.
     11  1.1  matt  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.1  matt  *    notice, this list of conditions and the following disclaimer in the
     13  1.1  matt  *    documentation and/or other materials provided with the distribution.
     14  1.1  matt  * 3. All advertising materials mentioning features or use of this software
     15  1.1  matt  *    must display the following acknowledgement:
     16  1.1  matt  *      This product includes software developed for the NetBSD Project by
     17  1.1  matt  *      Eiji Kawauchi.
     18  1.1  matt  * 4. The name of the author may not be used to endorse or promote products
     19  1.1  matt  *    derived from this software without specific prior written permission
     20  1.1  matt  *
     21  1.1  matt  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  1.1  matt  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  1.1  matt  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  1.1  matt  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  1.1  matt  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  1.1  matt  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  1.1  matt  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  1.1  matt  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  1.1  matt  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  1.1  matt  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  1.1  matt  */
     32  1.1  matt /*
     33  1.1  matt  * Copyright (c) 2005 Brocade Communcations, inc.
     34  1.1  matt  * All rights reserved.
     35  1.1  matt  *
     36  1.1  matt  * Written by Matt Thomas for Brocade Communcations, Inc.
     37  1.1  matt  *
     38  1.1  matt  * Redistribution and use in source and binary forms, with or without
     39  1.1  matt  * modification, are permitted provided that the following conditions
     40  1.1  matt  * are met:
     41  1.1  matt  * 1. Redistributions of source code must retain the above copyright
     42  1.1  matt  *    notice, this list of conditions and the following disclaimer.
     43  1.1  matt  * 2. Redistributions in binary form must reproduce the above copyright
     44  1.1  matt  *    notice, this list of conditions and the following disclaimer in the
     45  1.1  matt  *    documentation and/or other materials provided with the distribution.
     46  1.1  matt  * 3. The name of Brocade Communications, Inc. may not be used to endorse
     47  1.1  matt  *    or promote products derived from this software without specific prior
     48  1.1  matt  *    written permission.
     49  1.1  matt  *
     50  1.1  matt  * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
     51  1.1  matt  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     52  1.1  matt  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     53  1.1  matt  * ARE DISCLAIMED.  IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
     54  1.1  matt  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     55  1.1  matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     56  1.1  matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     57  1.1  matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     58  1.1  matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     59  1.1  matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
     60  1.1  matt  * OF THE POSSIBILITY OF SUCH DAMAGE.
     61  1.1  matt  */
     62  1.1  matt //#define TWSI_DEBUG
     63  1.1  matt 
     64  1.1  matt /*
     65  1.1  matt  * Marvell Two-Wire Serial Interface (aka I2C) master driver
     66  1.1  matt  */
     67  1.1  matt 
     68  1.1  matt #include <sys/cdefs.h>
     69  1.1  matt __KERNEL_RCSID(0, "$NetBSD: gttwsi_core.c,v 1.1 2013/09/06 00:56:12 matt Exp $");
     70  1.1  matt #include "locators.h"
     71  1.1  matt 
     72  1.1  matt #include <sys/param.h>
     73  1.1  matt #include <sys/bus.h>
     74  1.1  matt #include <sys/condvar.h>
     75  1.1  matt #include <sys/device.h>
     76  1.1  matt #include <sys/errno.h>
     77  1.1  matt #include <sys/kernel.h>
     78  1.1  matt #include <sys/mutex.h>
     79  1.1  matt #include <sys/systm.h>
     80  1.1  matt 
     81  1.1  matt #include <dev/i2c/i2cvar.h>
     82  1.1  matt 
     83  1.1  matt #include <dev/i2c/gttwsireg.h>
     84  1.1  matt #include <dev/i2c/gttwsivar.h>
     85  1.1  matt 
     86  1.1  matt static int	gttwsi_acquire_bus(void *, int);
     87  1.1  matt static void	gttwsi_release_bus(void *, int);
     88  1.1  matt static int	gttwsi_send_start(void *v, int flags);
     89  1.1  matt static int	gttwsi_send_stop(void *v, int flags);
     90  1.1  matt static int	gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags);
     91  1.1  matt static int	gttwsi_read_byte(void *v, uint8_t *valp, int flags);
     92  1.1  matt static int	gttwsi_write_byte(void *v, uint8_t val, int flags);
     93  1.1  matt 
     94  1.1  matt static int	gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t, int);
     95  1.1  matt 
     96  1.1  matt static inline uint32_t
     97  1.1  matt gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg)
     98  1.1  matt {
     99  1.1  matt 	uint32_t val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
    100  1.1  matt #ifdef TWSI_DEBUG
    101  1.1  matt 	printf("I2C:R:%02x:%02x\n", reg, val);
    102  1.1  matt #else
    103  1.1  matt 	DELAY(TWSI_READ_DELAY);
    104  1.1  matt #endif
    105  1.1  matt 	return val;
    106  1.1  matt }
    107  1.1  matt 
    108  1.1  matt static inline void
    109  1.1  matt gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
    110  1.1  matt {
    111  1.1  matt 	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
    112  1.1  matt #ifdef TWSI_DEBUG
    113  1.1  matt 	printf("I2C:W:%02x:%02x\n", reg, val);
    114  1.1  matt #else
    115  1.1  matt 	DELAY(TWSI_WRITE_DELAY);
    116  1.1  matt #endif
    117  1.1  matt 	return;
    118  1.1  matt }
    119  1.1  matt 
    120  1.1  matt 
    121  1.1  matt 
    122  1.1  matt /* ARGSUSED */
    123  1.1  matt void
    124  1.1  matt gttwsi_attach_subr(device_t self, bus_space_tag_t iot, bus_space_handle_t ioh)
    125  1.1  matt {
    126  1.1  matt 	struct gttwsi_softc * const sc = device_private(self);
    127  1.1  matt 
    128  1.1  matt 	aprint_naive("\n");
    129  1.1  matt 	aprint_normal(": Marvell TWSI controller\n");
    130  1.1  matt 
    131  1.1  matt 	sc->sc_dev = self;
    132  1.1  matt 	sc->sc_bust = iot;
    133  1.1  matt 	sc->sc_bush = ioh;
    134  1.1  matt 
    135  1.1  matt 	mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
    136  1.1  matt 	mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO);
    137  1.1  matt 	cv_init(&sc->sc_cv, device_xname(self));
    138  1.1  matt 
    139  1.1  matt 	sc->sc_started = false;
    140  1.1  matt 	sc->sc_i2c.ic_cookie = sc;
    141  1.1  matt 	sc->sc_i2c.ic_acquire_bus = gttwsi_acquire_bus;
    142  1.1  matt 	sc->sc_i2c.ic_release_bus = gttwsi_release_bus;
    143  1.1  matt 	sc->sc_i2c.ic_exec = NULL;
    144  1.1  matt 	sc->sc_i2c.ic_send_start = gttwsi_send_start;
    145  1.1  matt 	sc->sc_i2c.ic_send_stop = gttwsi_send_stop;
    146  1.1  matt 	sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer;
    147  1.1  matt 	sc->sc_i2c.ic_read_byte = gttwsi_read_byte;
    148  1.1  matt 	sc->sc_i2c.ic_write_byte = gttwsi_write_byte;
    149  1.1  matt 
    150  1.1  matt 	/*
    151  1.1  matt 	 * Put the controller into Soft Reset.
    152  1.1  matt 	 */
    153  1.1  matt 	/* reset */
    154  1.1  matt 	gttwsi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL);
    155  1.1  matt 
    156  1.1  matt }
    157  1.1  matt 
    158  1.1  matt void
    159  1.1  matt gttwsi_config_children(device_t self)
    160  1.1  matt {
    161  1.1  matt 	struct gttwsi_softc * const sc = device_private(self);
    162  1.1  matt 	struct i2cbus_attach_args iba;
    163  1.1  matt 
    164  1.1  matt 	memset(&iba, 0, sizeof(iba));
    165  1.1  matt 	iba.iba_tag = &sc->sc_i2c;
    166  1.1  matt 
    167  1.1  matt 	(void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
    168  1.1  matt }
    169  1.1  matt 
    170  1.1  matt int
    171  1.1  matt gttwsi_intr(void *arg)
    172  1.1  matt {
    173  1.1  matt 	struct gttwsi_softc *sc = arg;
    174  1.1  matt 	uint32_t val;
    175  1.1  matt 
    176  1.1  matt 	val = gttwsi_read_4(sc, TWSI_CONTROL);
    177  1.1  matt 	if (val & CONTROL_IFLG) {
    178  1.1  matt 		gttwsi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
    179  1.1  matt 		mutex_enter(&sc->sc_mtx);
    180  1.1  matt 		cv_signal(&sc->sc_cv);
    181  1.1  matt 		mutex_exit(&sc->sc_mtx);
    182  1.1  matt 
    183  1.1  matt 		return 1;	/* handled */
    184  1.1  matt 	}
    185  1.1  matt 	return 0;
    186  1.1  matt }
    187  1.1  matt 
    188  1.1  matt /* ARGSUSED */
    189  1.1  matt static int
    190  1.1  matt gttwsi_acquire_bus(void *arg, int flags)
    191  1.1  matt {
    192  1.1  matt 	struct gttwsi_softc *sc = arg;
    193  1.1  matt 
    194  1.1  matt 	mutex_enter(&sc->sc_buslock);
    195  1.1  matt 	return 0;
    196  1.1  matt }
    197  1.1  matt 
    198  1.1  matt /* ARGSUSED */
    199  1.1  matt static void
    200  1.1  matt gttwsi_release_bus(void *arg, int flags)
    201  1.1  matt {
    202  1.1  matt 	struct gttwsi_softc *sc = arg;
    203  1.1  matt 
    204  1.1  matt 	mutex_exit(&sc->sc_buslock);
    205  1.1  matt }
    206  1.1  matt 
    207  1.1  matt static int
    208  1.1  matt gttwsi_send_start(void *v, int flags)
    209  1.1  matt {
    210  1.1  matt 	struct gttwsi_softc *sc = v;
    211  1.1  matt 	int expect;
    212  1.1  matt 
    213  1.1  matt 	if (sc->sc_started)
    214  1.1  matt 		expect = STAT_RSCT;
    215  1.1  matt 	else
    216  1.1  matt 		expect = STAT_SCT;
    217  1.1  matt 	sc->sc_started = true;
    218  1.1  matt 	return gttwsi_wait(sc, CONTROL_START, expect, flags);
    219  1.1  matt }
    220  1.1  matt 
    221  1.1  matt static int
    222  1.1  matt gttwsi_send_stop(void *v, int flags)
    223  1.1  matt {
    224  1.1  matt 	struct gttwsi_softc *sc = v;
    225  1.1  matt 	int retry = TWSI_RETRY_COUNT;
    226  1.1  matt 
    227  1.1  matt 	sc->sc_started = false;
    228  1.1  matt 
    229  1.1  matt 	/* Interrupt is not generated for STAT_NRS. */
    230  1.1  matt 	gttwsi_write_4(sc, TWSI_CONTROL, CONTROL_STOP | CONTROL_TWSIEN);
    231  1.1  matt 	while (retry > 0) {
    232  1.1  matt 		if (gttwsi_read_4(sc, TWSI_STATUS) == STAT_NRS)
    233  1.1  matt 			return 0;
    234  1.1  matt 		retry--;
    235  1.1  matt 		DELAY(TWSI_STAT_DELAY);
    236  1.1  matt 	}
    237  1.1  matt 
    238  1.1  matt 	aprint_error_dev(sc->sc_dev, "send STOP failed\n");
    239  1.1  matt 	return -1;
    240  1.1  matt }
    241  1.1  matt 
    242  1.1  matt static int
    243  1.1  matt gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags)
    244  1.1  matt {
    245  1.1  matt 	struct gttwsi_softc *sc = v;
    246  1.1  matt 	uint32_t data, expect;
    247  1.1  matt 	int error, read;
    248  1.1  matt 
    249  1.1  matt 	gttwsi_send_start(v, flags);
    250  1.1  matt 
    251  1.1  matt 	read = (flags & I2C_F_READ) != 0;
    252  1.1  matt 	if (read)
    253  1.1  matt 		expect = STAT_ARBT_AR;
    254  1.1  matt 	else
    255  1.1  matt 		expect = STAT_AWBT_AR;
    256  1.1  matt 
    257  1.1  matt 	/*
    258  1.1  matt 	 * First byte contains whether this xfer is a read or write.
    259  1.1  matt 	 */
    260  1.1  matt 	data = read;
    261  1.1  matt 	if (addr > 0x7f) {
    262  1.1  matt 		/*
    263  1.1  matt 		 * If this is a 10bit request, the first address byte is
    264  1.1  matt 		 * 0b11110<b9><b8><r/w>.
    265  1.1  matt 		 */
    266  1.1  matt 		data |= 0xf0 | ((addr & 0x300) >> 7);
    267  1.1  matt 		gttwsi_write_4(sc, TWSI_DATA, data);
    268  1.1  matt 		error = gttwsi_wait(sc, 0, expect, flags);
    269  1.1  matt 		if (error)
    270  1.1  matt 			return error;
    271  1.1  matt 		/*
    272  1.1  matt 		 * The first address byte has been sent, now to send
    273  1.1  matt 		 * the second one.
    274  1.1  matt 		 */
    275  1.1  matt 		if (read)
    276  1.1  matt 			expect = STAT_SARBT_AR;
    277  1.1  matt 		else
    278  1.1  matt 			expect = STAT_SAWBT_AR;
    279  1.1  matt 		data = (uint8_t)addr;
    280  1.1  matt 	} else
    281  1.1  matt 		data |= (addr << 1);
    282  1.1  matt 
    283  1.1  matt 	gttwsi_write_4(sc, TWSI_DATA, data);
    284  1.1  matt 	return gttwsi_wait(sc, 0, expect, flags);
    285  1.1  matt }
    286  1.1  matt 
    287  1.1  matt static int
    288  1.1  matt gttwsi_read_byte(void *v, uint8_t *valp, int flags)
    289  1.1  matt {
    290  1.1  matt 	struct gttwsi_softc *sc = v;
    291  1.1  matt 	int error;
    292  1.1  matt 
    293  1.1  matt 	if (flags & I2C_F_LAST)
    294  1.1  matt 		error = gttwsi_wait(sc, 0, STAT_MRRD_ANT, flags);
    295  1.1  matt 	else
    296  1.1  matt 		error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, flags);
    297  1.1  matt 	if (!error)
    298  1.1  matt 		*valp = gttwsi_read_4(sc, TWSI_DATA);
    299  1.1  matt 	if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP))
    300  1.1  matt 		error = gttwsi_send_stop(sc, flags);
    301  1.1  matt 	return error;
    302  1.1  matt }
    303  1.1  matt 
    304  1.1  matt static int
    305  1.1  matt gttwsi_write_byte(void *v, uint8_t val, int flags)
    306  1.1  matt {
    307  1.1  matt 	struct gttwsi_softc *sc = v;
    308  1.1  matt 	int error;
    309  1.1  matt 
    310  1.1  matt 	gttwsi_write_4(sc, TWSI_DATA, val);
    311  1.1  matt 	error = gttwsi_wait(sc, 0, STAT_MTDB_AR, flags);
    312  1.1  matt 	if (flags & I2C_F_STOP)
    313  1.1  matt 		gttwsi_send_stop(sc, flags);
    314  1.1  matt 	return error;
    315  1.1  matt }
    316  1.1  matt 
    317  1.1  matt static int
    318  1.1  matt gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect,
    319  1.1  matt 	    int flags)
    320  1.1  matt {
    321  1.1  matt 	uint32_t status;
    322  1.1  matt 	int timo, error = 0;
    323  1.1  matt 
    324  1.1  matt 	DELAY(5);
    325  1.1  matt 	if (!(flags & I2C_F_POLL))
    326  1.1  matt 		control |= CONTROL_INTEN;
    327  1.1  matt 	gttwsi_write_4(sc, TWSI_CONTROL, control | CONTROL_TWSIEN);
    328  1.1  matt 
    329  1.1  matt 	timo = 0;
    330  1.1  matt 	for (;;) {
    331  1.1  matt 		control = gttwsi_read_4(sc, TWSI_CONTROL);
    332  1.1  matt 		if (control & CONTROL_IFLG)
    333  1.1  matt 			break;
    334  1.1  matt 		if (!(flags & I2C_F_POLL)) {
    335  1.1  matt 			mutex_enter(&sc->sc_mtx);
    336  1.1  matt 			error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz);
    337  1.1  matt 			mutex_exit(&sc->sc_mtx);
    338  1.1  matt 			if (error)
    339  1.1  matt 				return error;
    340  1.1  matt 		}
    341  1.1  matt 		DELAY(TWSI_RETRY_DELAY);
    342  1.1  matt 		if (timo++ > 1000000)	/* 1sec */
    343  1.1  matt 			break;
    344  1.1  matt 	}
    345  1.1  matt 
    346  1.1  matt 	status = gttwsi_read_4(sc, TWSI_STATUS);
    347  1.1  matt 	if (status != expect) {
    348  1.1  matt 		aprint_error_dev(sc->sc_dev,
    349  1.1  matt 		    "unexpected status 0x%x: expect 0x%x\n", status, expect);
    350  1.1  matt 		return EIO;
    351  1.1  matt 	}
    352  1.1  matt 	return error;
    353  1.1  matt }
    354