gttwsi_core.c revision 1.2.12.1 1 1.2.12.1 snj /* $NetBSD: gttwsi_core.c,v 1.2.12.1 2018/10/15 03:09:07 snj Exp $ */
2 1.1 matt /*
3 1.1 matt * Copyright (c) 2008 Eiji Kawauchi.
4 1.1 matt * All rights reserved.
5 1.1 matt *
6 1.1 matt * Redistribution and use in source and binary forms, with or without
7 1.1 matt * modification, are permitted provided that the following conditions
8 1.1 matt * are met:
9 1.1 matt * 1. Redistributions of source code must retain the above copyright
10 1.1 matt * notice, this list of conditions and the following disclaimer.
11 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 matt * notice, this list of conditions and the following disclaimer in the
13 1.1 matt * documentation and/or other materials provided with the distribution.
14 1.1 matt * 3. All advertising materials mentioning features or use of this software
15 1.1 matt * must display the following acknowledgement:
16 1.1 matt * This product includes software developed for the NetBSD Project by
17 1.1 matt * Eiji Kawauchi.
18 1.1 matt * 4. The name of the author may not be used to endorse or promote products
19 1.1 matt * derived from this software without specific prior written permission
20 1.1 matt *
21 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1 matt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1 matt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1 matt * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1 matt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1 matt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1 matt * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1 matt * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1 matt * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1 matt * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1 matt */
32 1.1 matt /*
33 1.1 matt * Copyright (c) 2005 Brocade Communcations, inc.
34 1.1 matt * All rights reserved.
35 1.1 matt *
36 1.1 matt * Written by Matt Thomas for Brocade Communcations, Inc.
37 1.1 matt *
38 1.1 matt * Redistribution and use in source and binary forms, with or without
39 1.1 matt * modification, are permitted provided that the following conditions
40 1.1 matt * are met:
41 1.1 matt * 1. Redistributions of source code must retain the above copyright
42 1.1 matt * notice, this list of conditions and the following disclaimer.
43 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
44 1.1 matt * notice, this list of conditions and the following disclaimer in the
45 1.1 matt * documentation and/or other materials provided with the distribution.
46 1.1 matt * 3. The name of Brocade Communications, Inc. may not be used to endorse
47 1.1 matt * or promote products derived from this software without specific prior
48 1.1 matt * written permission.
49 1.1 matt *
50 1.1 matt * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
51 1.1 matt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 1.1 matt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 1.1 matt * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
54 1.1 matt * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
60 1.1 matt * OF THE POSSIBILITY OF SUCH DAMAGE.
61 1.1 matt */
62 1.1 matt //#define TWSI_DEBUG
63 1.1 matt
64 1.1 matt /*
65 1.1 matt * Marvell Two-Wire Serial Interface (aka I2C) master driver
66 1.1 matt */
67 1.1 matt
68 1.1 matt #include <sys/cdefs.h>
69 1.2.12.1 snj __KERNEL_RCSID(0, "$NetBSD: gttwsi_core.c,v 1.2.12.1 2018/10/15 03:09:07 snj Exp $");
70 1.1 matt #include "locators.h"
71 1.1 matt
72 1.1 matt #include <sys/param.h>
73 1.1 matt #include <sys/bus.h>
74 1.1 matt #include <sys/condvar.h>
75 1.1 matt #include <sys/device.h>
76 1.1 matt #include <sys/errno.h>
77 1.1 matt #include <sys/kernel.h>
78 1.1 matt #include <sys/mutex.h>
79 1.1 matt #include <sys/systm.h>
80 1.1 matt
81 1.1 matt #include <dev/i2c/i2cvar.h>
82 1.1 matt
83 1.1 matt #include <dev/i2c/gttwsireg.h>
84 1.1 matt #include <dev/i2c/gttwsivar.h>
85 1.1 matt
86 1.1 matt static int gttwsi_acquire_bus(void *, int);
87 1.1 matt static void gttwsi_release_bus(void *, int);
88 1.1 matt static int gttwsi_send_start(void *v, int flags);
89 1.1 matt static int gttwsi_send_stop(void *v, int flags);
90 1.1 matt static int gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags);
91 1.1 matt static int gttwsi_read_byte(void *v, uint8_t *valp, int flags);
92 1.1 matt static int gttwsi_write_byte(void *v, uint8_t val, int flags);
93 1.1 matt
94 1.2.12.1 snj static int gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t,
95 1.2.12.1 snj uint32_t, int);
96 1.1 matt
97 1.1 matt static inline uint32_t
98 1.1 matt gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg)
99 1.1 matt {
100 1.1 matt uint32_t val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
101 1.1 matt #ifdef TWSI_DEBUG
102 1.1 matt printf("I2C:R:%02x:%02x\n", reg, val);
103 1.1 matt #else
104 1.1 matt DELAY(TWSI_READ_DELAY);
105 1.1 matt #endif
106 1.1 matt return val;
107 1.1 matt }
108 1.1 matt
109 1.1 matt static inline void
110 1.1 matt gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
111 1.1 matt {
112 1.1 matt bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
113 1.1 matt #ifdef TWSI_DEBUG
114 1.1 matt printf("I2C:W:%02x:%02x\n", reg, val);
115 1.1 matt #else
116 1.1 matt DELAY(TWSI_WRITE_DELAY);
117 1.1 matt #endif
118 1.1 matt return;
119 1.1 matt }
120 1.1 matt
121 1.1 matt
122 1.1 matt
123 1.1 matt /* ARGSUSED */
124 1.1 matt void
125 1.1 matt gttwsi_attach_subr(device_t self, bus_space_tag_t iot, bus_space_handle_t ioh)
126 1.1 matt {
127 1.1 matt struct gttwsi_softc * const sc = device_private(self);
128 1.2 jmcneill prop_dictionary_t cfg = device_properties(self);
129 1.1 matt
130 1.1 matt aprint_naive("\n");
131 1.1 matt aprint_normal(": Marvell TWSI controller\n");
132 1.1 matt
133 1.1 matt sc->sc_dev = self;
134 1.1 matt sc->sc_bust = iot;
135 1.1 matt sc->sc_bush = ioh;
136 1.1 matt
137 1.2.12.1 snj mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_VM);
138 1.1 matt mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO);
139 1.1 matt cv_init(&sc->sc_cv, device_xname(self));
140 1.1 matt
141 1.2 jmcneill prop_dictionary_get_bool(cfg, "iflg-rwc", &sc->sc_iflg_rwc);
142 1.2 jmcneill
143 1.1 matt sc->sc_started = false;
144 1.1 matt sc->sc_i2c.ic_cookie = sc;
145 1.1 matt sc->sc_i2c.ic_acquire_bus = gttwsi_acquire_bus;
146 1.1 matt sc->sc_i2c.ic_release_bus = gttwsi_release_bus;
147 1.1 matt sc->sc_i2c.ic_exec = NULL;
148 1.1 matt sc->sc_i2c.ic_send_start = gttwsi_send_start;
149 1.1 matt sc->sc_i2c.ic_send_stop = gttwsi_send_stop;
150 1.1 matt sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer;
151 1.1 matt sc->sc_i2c.ic_read_byte = gttwsi_read_byte;
152 1.1 matt sc->sc_i2c.ic_write_byte = gttwsi_write_byte;
153 1.1 matt
154 1.1 matt /*
155 1.1 matt * Put the controller into Soft Reset.
156 1.1 matt */
157 1.1 matt /* reset */
158 1.1 matt gttwsi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL);
159 1.1 matt
160 1.1 matt }
161 1.1 matt
162 1.1 matt void
163 1.1 matt gttwsi_config_children(device_t self)
164 1.1 matt {
165 1.1 matt struct gttwsi_softc * const sc = device_private(self);
166 1.1 matt struct i2cbus_attach_args iba;
167 1.1 matt
168 1.1 matt memset(&iba, 0, sizeof(iba));
169 1.1 matt iba.iba_tag = &sc->sc_i2c;
170 1.1 matt
171 1.1 matt (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
172 1.1 matt }
173 1.1 matt
174 1.1 matt int
175 1.1 matt gttwsi_intr(void *arg)
176 1.1 matt {
177 1.1 matt struct gttwsi_softc *sc = arg;
178 1.1 matt uint32_t val;
179 1.1 matt
180 1.2.12.1 snj mutex_enter(&sc->sc_mtx);
181 1.1 matt val = gttwsi_read_4(sc, TWSI_CONTROL);
182 1.1 matt if (val & CONTROL_IFLG) {
183 1.1 matt gttwsi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
184 1.2.12.1 snj cv_broadcast(&sc->sc_cv);
185 1.1 matt mutex_exit(&sc->sc_mtx);
186 1.1 matt return 1; /* handled */
187 1.1 matt }
188 1.2.12.1 snj mutex_exit(&sc->sc_mtx);
189 1.1 matt return 0;
190 1.1 matt }
191 1.1 matt
192 1.1 matt /* ARGSUSED */
193 1.1 matt static int
194 1.1 matt gttwsi_acquire_bus(void *arg, int flags)
195 1.1 matt {
196 1.1 matt struct gttwsi_softc *sc = arg;
197 1.1 matt
198 1.1 matt mutex_enter(&sc->sc_buslock);
199 1.2.12.1 snj while (sc->sc_inuse)
200 1.2.12.1 snj cv_wait(&sc->sc_cv, &sc->sc_buslock);
201 1.2.12.1 snj sc->sc_inuse = true;
202 1.2.12.1 snj mutex_exit(&sc->sc_buslock);
203 1.2.12.1 snj
204 1.1 matt return 0;
205 1.1 matt }
206 1.1 matt
207 1.1 matt /* ARGSUSED */
208 1.1 matt static void
209 1.1 matt gttwsi_release_bus(void *arg, int flags)
210 1.1 matt {
211 1.1 matt struct gttwsi_softc *sc = arg;
212 1.1 matt
213 1.2.12.1 snj mutex_enter(&sc->sc_buslock);
214 1.2.12.1 snj sc->sc_inuse = false;
215 1.2.12.1 snj cv_broadcast(&sc->sc_cv);
216 1.1 matt mutex_exit(&sc->sc_buslock);
217 1.1 matt }
218 1.1 matt
219 1.1 matt static int
220 1.1 matt gttwsi_send_start(void *v, int flags)
221 1.1 matt {
222 1.1 matt struct gttwsi_softc *sc = v;
223 1.1 matt int expect;
224 1.1 matt
225 1.2.12.1 snj KASSERT(sc->sc_inuse);
226 1.2.12.1 snj
227 1.1 matt if (sc->sc_started)
228 1.1 matt expect = STAT_RSCT;
229 1.1 matt else
230 1.1 matt expect = STAT_SCT;
231 1.1 matt sc->sc_started = true;
232 1.2.12.1 snj return gttwsi_wait(sc, CONTROL_START, expect, 0, flags);
233 1.1 matt }
234 1.1 matt
235 1.1 matt static int
236 1.1 matt gttwsi_send_stop(void *v, int flags)
237 1.1 matt {
238 1.1 matt struct gttwsi_softc *sc = v;
239 1.1 matt int retry = TWSI_RETRY_COUNT;
240 1.2 jmcneill uint32_t control;
241 1.1 matt
242 1.2.12.1 snj KASSERT(sc->sc_inuse);
243 1.2.12.1 snj
244 1.1 matt sc->sc_started = false;
245 1.1 matt
246 1.1 matt /* Interrupt is not generated for STAT_NRS. */
247 1.2 jmcneill control = CONTROL_STOP | CONTROL_TWSIEN;
248 1.2 jmcneill if (sc->sc_iflg_rwc)
249 1.2 jmcneill control |= CONTROL_IFLG;
250 1.2 jmcneill gttwsi_write_4(sc, TWSI_CONTROL, control);
251 1.1 matt while (retry > 0) {
252 1.1 matt if (gttwsi_read_4(sc, TWSI_STATUS) == STAT_NRS)
253 1.1 matt return 0;
254 1.1 matt retry--;
255 1.1 matt DELAY(TWSI_STAT_DELAY);
256 1.1 matt }
257 1.1 matt
258 1.1 matt aprint_error_dev(sc->sc_dev, "send STOP failed\n");
259 1.1 matt return -1;
260 1.1 matt }
261 1.1 matt
262 1.1 matt static int
263 1.1 matt gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags)
264 1.1 matt {
265 1.1 matt struct gttwsi_softc *sc = v;
266 1.2.12.1 snj uint32_t data, expect, alt;
267 1.1 matt int error, read;
268 1.1 matt
269 1.2.12.1 snj KASSERT(sc->sc_inuse);
270 1.2.12.1 snj
271 1.2.12.1 snj error = gttwsi_send_start(v, flags);
272 1.2.12.1 snj if (error)
273 1.2.12.1 snj return error;
274 1.1 matt
275 1.1 matt read = (flags & I2C_F_READ) != 0;
276 1.2.12.1 snj if (read) {
277 1.1 matt expect = STAT_ARBT_AR;
278 1.2.12.1 snj alt = STAT_ARBT_ANR;
279 1.2.12.1 snj } else {
280 1.1 matt expect = STAT_AWBT_AR;
281 1.2.12.1 snj alt = STAT_AWBT_ANR;
282 1.2.12.1 snj }
283 1.1 matt
284 1.1 matt /*
285 1.1 matt * First byte contains whether this xfer is a read or write.
286 1.1 matt */
287 1.1 matt data = read;
288 1.1 matt if (addr > 0x7f) {
289 1.1 matt /*
290 1.1 matt * If this is a 10bit request, the first address byte is
291 1.1 matt * 0b11110<b9><b8><r/w>.
292 1.1 matt */
293 1.1 matt data |= 0xf0 | ((addr & 0x300) >> 7);
294 1.1 matt gttwsi_write_4(sc, TWSI_DATA, data);
295 1.2.12.1 snj error = gttwsi_wait(sc, 0, expect, alt, flags);
296 1.1 matt if (error)
297 1.1 matt return error;
298 1.1 matt /*
299 1.1 matt * The first address byte has been sent, now to send
300 1.1 matt * the second one.
301 1.1 matt */
302 1.2.12.1 snj if (read) {
303 1.1 matt expect = STAT_SARBT_AR;
304 1.2.12.1 snj alt = STAT_SARBT_ANR;
305 1.2.12.1 snj } else {
306 1.1 matt expect = STAT_SAWBT_AR;
307 1.2.12.1 snj alt = STAT_SAWBT_ANR;
308 1.2.12.1 snj }
309 1.1 matt data = (uint8_t)addr;
310 1.1 matt } else
311 1.1 matt data |= (addr << 1);
312 1.1 matt
313 1.1 matt gttwsi_write_4(sc, TWSI_DATA, data);
314 1.2.12.1 snj return gttwsi_wait(sc, 0, expect, alt, flags);
315 1.1 matt }
316 1.1 matt
317 1.1 matt static int
318 1.1 matt gttwsi_read_byte(void *v, uint8_t *valp, int flags)
319 1.1 matt {
320 1.1 matt struct gttwsi_softc *sc = v;
321 1.1 matt int error;
322 1.1 matt
323 1.2.12.1 snj KASSERT(sc->sc_inuse);
324 1.2.12.1 snj
325 1.1 matt if (flags & I2C_F_LAST)
326 1.2.12.1 snj error = gttwsi_wait(sc, 0, STAT_MRRD_ANT, 0, flags);
327 1.1 matt else
328 1.2.12.1 snj error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, 0, flags);
329 1.1 matt if (!error)
330 1.1 matt *valp = gttwsi_read_4(sc, TWSI_DATA);
331 1.1 matt if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP))
332 1.1 matt error = gttwsi_send_stop(sc, flags);
333 1.1 matt return error;
334 1.1 matt }
335 1.1 matt
336 1.1 matt static int
337 1.1 matt gttwsi_write_byte(void *v, uint8_t val, int flags)
338 1.1 matt {
339 1.1 matt struct gttwsi_softc *sc = v;
340 1.1 matt int error;
341 1.1 matt
342 1.2.12.1 snj KASSERT(sc->sc_inuse);
343 1.2.12.1 snj
344 1.1 matt gttwsi_write_4(sc, TWSI_DATA, val);
345 1.2.12.1 snj error = gttwsi_wait(sc, 0, STAT_MTDB_AR, 0, flags);
346 1.1 matt if (flags & I2C_F_STOP)
347 1.1 matt gttwsi_send_stop(sc, flags);
348 1.1 matt return error;
349 1.1 matt }
350 1.1 matt
351 1.1 matt static int
352 1.1 matt gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect,
353 1.2.12.1 snj uint32_t alt, int flags)
354 1.1 matt {
355 1.1 matt uint32_t status;
356 1.1 matt int timo, error = 0;
357 1.1 matt
358 1.2.12.1 snj KASSERT(sc->sc_inuse);
359 1.2.12.1 snj
360 1.1 matt DELAY(5);
361 1.1 matt if (!(flags & I2C_F_POLL))
362 1.1 matt control |= CONTROL_INTEN;
363 1.2 jmcneill if (sc->sc_iflg_rwc)
364 1.2 jmcneill control |= CONTROL_IFLG;
365 1.2.12.1 snj mutex_enter(&sc->sc_mtx);
366 1.1 matt gttwsi_write_4(sc, TWSI_CONTROL, control | CONTROL_TWSIEN);
367 1.1 matt
368 1.1 matt timo = 0;
369 1.1 matt for (;;) {
370 1.1 matt control = gttwsi_read_4(sc, TWSI_CONTROL);
371 1.1 matt if (control & CONTROL_IFLG)
372 1.1 matt break;
373 1.1 matt if (!(flags & I2C_F_POLL)) {
374 1.1 matt error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz);
375 1.1 matt if (error)
376 1.2.12.1 snj break;
377 1.2.12.1 snj } else {
378 1.2.12.1 snj DELAY(TWSI_RETRY_DELAY);
379 1.2.12.1 snj if (timo++ > 1000000) /* 1sec */
380 1.2.12.1 snj break;
381 1.1 matt }
382 1.1 matt }
383 1.2.12.1 snj if ((control & CONTROL_IFLG) == 0) {
384 1.2.12.1 snj aprint_error_dev(sc->sc_dev,
385 1.2.12.1 snj "gttwsi_wait(): timeout, control=0x%x\n", control);
386 1.2.12.1 snj error = EWOULDBLOCK;
387 1.2.12.1 snj goto end;
388 1.2.12.1 snj }
389 1.1 matt status = gttwsi_read_4(sc, TWSI_STATUS);
390 1.1 matt if (status != expect) {
391 1.2.12.1 snj /*
392 1.2.12.1 snj * In the case of probing for a device, we are expecting
393 1.2.12.1 snj * 2 different status codes: the ACK case (device exists),
394 1.2.12.1 snj * or the NACK case (device does not exist). We don't
395 1.2.12.1 snj * need to report an error in the later case.
396 1.2.12.1 snj */
397 1.2.12.1 snj if (alt != 0 && status != alt)
398 1.2.12.1 snj aprint_error_dev(sc->sc_dev,
399 1.2.12.1 snj "unexpected status 0x%x: expect 0x%x\n", status,
400 1.2.12.1 snj expect);
401 1.2.12.1 snj error = EIO;
402 1.1 matt }
403 1.2.12.1 snj end:
404 1.2.12.1 snj mutex_exit(&sc->sc_mtx);
405 1.1 matt return error;
406 1.1 matt }
407