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gttwsi_core.c revision 1.3.2.3
      1  1.3.2.3  pgoyette /*	$NetBSD: gttwsi_core.c,v 1.3.2.3 2018/10/20 06:58:31 pgoyette Exp $	*/
      2      1.1      matt /*
      3      1.1      matt  * Copyright (c) 2008 Eiji Kawauchi.
      4      1.1      matt  * All rights reserved.
      5      1.1      matt  *
      6      1.1      matt  * Redistribution and use in source and binary forms, with or without
      7      1.1      matt  * modification, are permitted provided that the following conditions
      8      1.1      matt  * are met:
      9      1.1      matt  * 1. Redistributions of source code must retain the above copyright
     10      1.1      matt  *    notice, this list of conditions and the following disclaimer.
     11      1.1      matt  * 2. Redistributions in binary form must reproduce the above copyright
     12      1.1      matt  *    notice, this list of conditions and the following disclaimer in the
     13      1.1      matt  *    documentation and/or other materials provided with the distribution.
     14      1.1      matt  * 3. All advertising materials mentioning features or use of this software
     15      1.1      matt  *    must display the following acknowledgement:
     16      1.1      matt  *      This product includes software developed for the NetBSD Project by
     17      1.1      matt  *      Eiji Kawauchi.
     18      1.1      matt  * 4. The name of the author may not be used to endorse or promote products
     19      1.1      matt  *    derived from this software without specific prior written permission
     20      1.1      matt  *
     21      1.1      matt  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22      1.1      matt  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23      1.1      matt  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24      1.1      matt  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25      1.1      matt  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26      1.1      matt  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27      1.1      matt  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28      1.1      matt  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29      1.1      matt  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30      1.1      matt  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31      1.1      matt  */
     32      1.1      matt /*
     33      1.1      matt  * Copyright (c) 2005 Brocade Communcations, inc.
     34      1.1      matt  * All rights reserved.
     35      1.1      matt  *
     36      1.1      matt  * Written by Matt Thomas for Brocade Communcations, Inc.
     37      1.1      matt  *
     38      1.1      matt  * Redistribution and use in source and binary forms, with or without
     39      1.1      matt  * modification, are permitted provided that the following conditions
     40      1.1      matt  * are met:
     41      1.1      matt  * 1. Redistributions of source code must retain the above copyright
     42      1.1      matt  *    notice, this list of conditions and the following disclaimer.
     43      1.1      matt  * 2. Redistributions in binary form must reproduce the above copyright
     44      1.1      matt  *    notice, this list of conditions and the following disclaimer in the
     45      1.1      matt  *    documentation and/or other materials provided with the distribution.
     46      1.1      matt  * 3. The name of Brocade Communications, Inc. may not be used to endorse
     47      1.1      matt  *    or promote products derived from this software without specific prior
     48      1.1      matt  *    written permission.
     49      1.1      matt  *
     50      1.1      matt  * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
     51      1.1      matt  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     52      1.1      matt  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     53      1.1      matt  * ARE DISCLAIMED.  IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
     54      1.1      matt  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     55      1.1      matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     56      1.1      matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     57      1.1      matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     58      1.1      matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     59      1.1      matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
     60      1.1      matt  * OF THE POSSIBILITY OF SUCH DAMAGE.
     61      1.1      matt  */
     62      1.1      matt //#define TWSI_DEBUG
     63      1.1      matt 
     64      1.1      matt /*
     65      1.1      matt  * Marvell Two-Wire Serial Interface (aka I2C) master driver
     66      1.1      matt  */
     67      1.1      matt 
     68      1.1      matt #include <sys/cdefs.h>
     69  1.3.2.3  pgoyette __KERNEL_RCSID(0, "$NetBSD: gttwsi_core.c,v 1.3.2.3 2018/10/20 06:58:31 pgoyette Exp $");
     70      1.1      matt #include "locators.h"
     71      1.1      matt 
     72      1.1      matt #include <sys/param.h>
     73      1.1      matt #include <sys/bus.h>
     74      1.1      matt #include <sys/condvar.h>
     75      1.1      matt #include <sys/device.h>
     76      1.1      matt #include <sys/errno.h>
     77      1.1      matt #include <sys/kernel.h>
     78      1.1      matt #include <sys/mutex.h>
     79      1.1      matt #include <sys/systm.h>
     80      1.1      matt 
     81      1.1      matt #include <dev/i2c/i2cvar.h>
     82      1.1      matt 
     83      1.1      matt #include <dev/i2c/gttwsireg.h>
     84      1.1      matt #include <dev/i2c/gttwsivar.h>
     85      1.1      matt 
     86      1.1      matt static int	gttwsi_acquire_bus(void *, int);
     87      1.1      matt static void	gttwsi_release_bus(void *, int);
     88      1.1      matt static int	gttwsi_send_start(void *v, int flags);
     89      1.1      matt static int	gttwsi_send_stop(void *v, int flags);
     90      1.1      matt static int	gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags);
     91      1.1      matt static int	gttwsi_read_byte(void *v, uint8_t *valp, int flags);
     92      1.1      matt static int	gttwsi_write_byte(void *v, uint8_t val, int flags);
     93      1.1      matt 
     94  1.3.2.2  pgoyette static int	gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t,
     95  1.3.2.2  pgoyette 			    uint32_t, int);
     96      1.1      matt 
     97      1.1      matt static inline uint32_t
     98      1.3  jmcneill gttwsi_default_read_4(struct gttwsi_softc *sc, uint32_t reg)
     99      1.1      matt {
    100      1.1      matt 	uint32_t val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
    101      1.1      matt #ifdef TWSI_DEBUG
    102      1.1      matt 	printf("I2C:R:%02x:%02x\n", reg, val);
    103      1.1      matt #else
    104      1.1      matt 	DELAY(TWSI_READ_DELAY);
    105      1.1      matt #endif
    106      1.1      matt 	return val;
    107      1.1      matt }
    108      1.1      matt 
    109      1.1      matt static inline void
    110      1.3  jmcneill gttwsi_default_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
    111      1.1      matt {
    112      1.1      matt 	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
    113      1.1      matt #ifdef TWSI_DEBUG
    114      1.1      matt 	printf("I2C:W:%02x:%02x\n", reg, val);
    115      1.1      matt #else
    116      1.1      matt 	DELAY(TWSI_WRITE_DELAY);
    117      1.1      matt #endif
    118      1.1      matt 	return;
    119      1.1      matt }
    120      1.1      matt 
    121      1.3  jmcneill static inline uint32_t
    122      1.3  jmcneill gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg)
    123      1.3  jmcneill {
    124      1.3  jmcneill 	return sc->sc_reg_read(sc, reg);
    125      1.3  jmcneill }
    126      1.1      matt 
    127      1.3  jmcneill static inline void
    128      1.3  jmcneill gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
    129      1.3  jmcneill {
    130      1.3  jmcneill 	return sc->sc_reg_write(sc, reg, val);
    131      1.3  jmcneill }
    132      1.1      matt 
    133      1.1      matt /* ARGSUSED */
    134      1.1      matt void
    135      1.1      matt gttwsi_attach_subr(device_t self, bus_space_tag_t iot, bus_space_handle_t ioh)
    136      1.1      matt {
    137      1.1      matt 	struct gttwsi_softc * const sc = device_private(self);
    138      1.2  jmcneill 	prop_dictionary_t cfg = device_properties(self);
    139      1.1      matt 
    140      1.1      matt 	aprint_naive("\n");
    141      1.1      matt 	aprint_normal(": Marvell TWSI controller\n");
    142      1.1      matt 
    143      1.1      matt 	sc->sc_dev = self;
    144      1.1      matt 	sc->sc_bust = iot;
    145      1.1      matt 	sc->sc_bush = ioh;
    146      1.1      matt 
    147      1.3  jmcneill 	if (sc->sc_reg_read == NULL)
    148      1.3  jmcneill 		sc->sc_reg_read = gttwsi_default_read_4;
    149      1.3  jmcneill 	if (sc->sc_reg_write == NULL)
    150      1.3  jmcneill 		sc->sc_reg_write = gttwsi_default_write_4;
    151      1.3  jmcneill 
    152  1.3.2.1  pgoyette 	mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_VM);
    153      1.1      matt 	mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO);
    154      1.1      matt 	cv_init(&sc->sc_cv, device_xname(self));
    155      1.1      matt 
    156      1.2  jmcneill 	prop_dictionary_get_bool(cfg, "iflg-rwc", &sc->sc_iflg_rwc);
    157      1.2  jmcneill 
    158      1.1      matt 	sc->sc_started = false;
    159      1.1      matt 	sc->sc_i2c.ic_cookie = sc;
    160      1.1      matt 	sc->sc_i2c.ic_acquire_bus = gttwsi_acquire_bus;
    161      1.1      matt 	sc->sc_i2c.ic_release_bus = gttwsi_release_bus;
    162      1.1      matt 	sc->sc_i2c.ic_exec = NULL;
    163      1.1      matt 	sc->sc_i2c.ic_send_start = gttwsi_send_start;
    164      1.1      matt 	sc->sc_i2c.ic_send_stop = gttwsi_send_stop;
    165      1.1      matt 	sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer;
    166      1.1      matt 	sc->sc_i2c.ic_read_byte = gttwsi_read_byte;
    167      1.1      matt 	sc->sc_i2c.ic_write_byte = gttwsi_write_byte;
    168      1.1      matt 
    169      1.1      matt 	/*
    170      1.1      matt 	 * Put the controller into Soft Reset.
    171      1.1      matt 	 */
    172      1.1      matt 	/* reset */
    173      1.1      matt 	gttwsi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL);
    174      1.1      matt 
    175      1.1      matt }
    176      1.1      matt 
    177      1.1      matt void
    178      1.1      matt gttwsi_config_children(device_t self)
    179      1.1      matt {
    180      1.1      matt 	struct gttwsi_softc * const sc = device_private(self);
    181      1.1      matt 	struct i2cbus_attach_args iba;
    182      1.1      matt 
    183      1.1      matt 	memset(&iba, 0, sizeof(iba));
    184      1.1      matt 	iba.iba_tag = &sc->sc_i2c;
    185      1.1      matt 
    186      1.1      matt 	(void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
    187      1.1      matt }
    188      1.1      matt 
    189      1.1      matt int
    190      1.1      matt gttwsi_intr(void *arg)
    191      1.1      matt {
    192      1.1      matt 	struct gttwsi_softc *sc = arg;
    193      1.1      matt 	uint32_t val;
    194      1.1      matt 
    195  1.3.2.3  pgoyette 	mutex_enter(&sc->sc_mtx);
    196      1.1      matt 	val = gttwsi_read_4(sc, TWSI_CONTROL);
    197      1.1      matt 	if (val & CONTROL_IFLG) {
    198      1.1      matt 		gttwsi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
    199  1.3.2.1  pgoyette 		cv_broadcast(&sc->sc_cv);
    200      1.1      matt 		mutex_exit(&sc->sc_mtx);
    201      1.1      matt 		return 1;	/* handled */
    202      1.1      matt 	}
    203  1.3.2.3  pgoyette 	mutex_exit(&sc->sc_mtx);
    204      1.1      matt 	return 0;
    205      1.1      matt }
    206      1.1      matt 
    207      1.1      matt /* ARGSUSED */
    208      1.1      matt static int
    209      1.1      matt gttwsi_acquire_bus(void *arg, int flags)
    210      1.1      matt {
    211      1.1      matt 	struct gttwsi_softc *sc = arg;
    212      1.1      matt 
    213      1.1      matt 	mutex_enter(&sc->sc_buslock);
    214  1.3.2.1  pgoyette 	while (sc->sc_inuse)
    215  1.3.2.1  pgoyette 		cv_wait(&sc->sc_cv, &sc->sc_buslock);
    216  1.3.2.1  pgoyette 	sc->sc_inuse = true;
    217  1.3.2.1  pgoyette 	mutex_exit(&sc->sc_buslock);
    218  1.3.2.1  pgoyette 
    219      1.1      matt 	return 0;
    220      1.1      matt }
    221      1.1      matt 
    222      1.1      matt /* ARGSUSED */
    223      1.1      matt static void
    224      1.1      matt gttwsi_release_bus(void *arg, int flags)
    225      1.1      matt {
    226      1.1      matt 	struct gttwsi_softc *sc = arg;
    227      1.1      matt 
    228  1.3.2.1  pgoyette 	mutex_enter(&sc->sc_buslock);
    229  1.3.2.1  pgoyette 	sc->sc_inuse = false;
    230  1.3.2.1  pgoyette 	cv_broadcast(&sc->sc_cv);
    231      1.1      matt 	mutex_exit(&sc->sc_buslock);
    232      1.1      matt }
    233      1.1      matt 
    234      1.1      matt static int
    235      1.1      matt gttwsi_send_start(void *v, int flags)
    236      1.1      matt {
    237      1.1      matt 	struct gttwsi_softc *sc = v;
    238      1.1      matt 	int expect;
    239      1.1      matt 
    240  1.3.2.1  pgoyette 	KASSERT(sc->sc_inuse);
    241      1.3  jmcneill 
    242      1.1      matt 	if (sc->sc_started)
    243      1.1      matt 		expect = STAT_RSCT;
    244      1.1      matt 	else
    245      1.1      matt 		expect = STAT_SCT;
    246      1.1      matt 	sc->sc_started = true;
    247  1.3.2.2  pgoyette 	return gttwsi_wait(sc, CONTROL_START, expect, 0, flags);
    248      1.1      matt }
    249      1.1      matt 
    250      1.1      matt static int
    251      1.1      matt gttwsi_send_stop(void *v, int flags)
    252      1.1      matt {
    253      1.1      matt 	struct gttwsi_softc *sc = v;
    254      1.1      matt 	int retry = TWSI_RETRY_COUNT;
    255      1.2  jmcneill 	uint32_t control;
    256      1.1      matt 
    257  1.3.2.1  pgoyette 	KASSERT(sc->sc_inuse);
    258      1.3  jmcneill 
    259      1.1      matt 	sc->sc_started = false;
    260      1.1      matt 
    261      1.1      matt 	/* Interrupt is not generated for STAT_NRS. */
    262      1.2  jmcneill 	control = CONTROL_STOP | CONTROL_TWSIEN;
    263      1.2  jmcneill 	if (sc->sc_iflg_rwc)
    264      1.2  jmcneill 		control |= CONTROL_IFLG;
    265      1.2  jmcneill 	gttwsi_write_4(sc, TWSI_CONTROL, control);
    266      1.1      matt 	while (retry > 0) {
    267      1.1      matt 		if (gttwsi_read_4(sc, TWSI_STATUS) == STAT_NRS)
    268      1.1      matt 			return 0;
    269      1.1      matt 		retry--;
    270      1.1      matt 		DELAY(TWSI_STAT_DELAY);
    271      1.1      matt 	}
    272      1.1      matt 
    273      1.1      matt 	aprint_error_dev(sc->sc_dev, "send STOP failed\n");
    274      1.1      matt 	return -1;
    275      1.1      matt }
    276      1.1      matt 
    277      1.1      matt static int
    278      1.1      matt gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags)
    279      1.1      matt {
    280      1.1      matt 	struct gttwsi_softc *sc = v;
    281  1.3.2.2  pgoyette 	uint32_t data, expect, alt;
    282      1.1      matt 	int error, read;
    283      1.1      matt 
    284  1.3.2.1  pgoyette 	KASSERT(sc->sc_inuse);
    285      1.3  jmcneill 
    286  1.3.2.2  pgoyette 	error = gttwsi_send_start(v, flags);
    287  1.3.2.2  pgoyette 	if (error)
    288  1.3.2.2  pgoyette 		return error;
    289      1.1      matt 
    290      1.1      matt 	read = (flags & I2C_F_READ) != 0;
    291  1.3.2.2  pgoyette 	if (read) {
    292      1.1      matt 		expect = STAT_ARBT_AR;
    293  1.3.2.2  pgoyette 		alt    = STAT_ARBT_ANR;
    294  1.3.2.2  pgoyette 	} else {
    295      1.1      matt 		expect = STAT_AWBT_AR;
    296  1.3.2.2  pgoyette 		alt    = STAT_AWBT_ANR;
    297  1.3.2.2  pgoyette 	}
    298      1.1      matt 
    299      1.1      matt 	/*
    300      1.1      matt 	 * First byte contains whether this xfer is a read or write.
    301      1.1      matt 	 */
    302      1.1      matt 	data = read;
    303      1.1      matt 	if (addr > 0x7f) {
    304      1.1      matt 		/*
    305      1.1      matt 		 * If this is a 10bit request, the first address byte is
    306      1.1      matt 		 * 0b11110<b9><b8><r/w>.
    307      1.1      matt 		 */
    308      1.1      matt 		data |= 0xf0 | ((addr & 0x300) >> 7);
    309      1.1      matt 		gttwsi_write_4(sc, TWSI_DATA, data);
    310  1.3.2.2  pgoyette 		error = gttwsi_wait(sc, 0, expect, alt, flags);
    311      1.1      matt 		if (error)
    312      1.1      matt 			return error;
    313      1.1      matt 		/*
    314      1.1      matt 		 * The first address byte has been sent, now to send
    315      1.1      matt 		 * the second one.
    316      1.1      matt 		 */
    317  1.3.2.2  pgoyette 		if (read) {
    318      1.1      matt 			expect = STAT_SARBT_AR;
    319  1.3.2.2  pgoyette 			alt    = STAT_SARBT_ANR;
    320  1.3.2.2  pgoyette 		} else {
    321      1.1      matt 			expect = STAT_SAWBT_AR;
    322  1.3.2.2  pgoyette 			alt    = STAT_SAWBT_ANR;
    323  1.3.2.2  pgoyette 		}
    324      1.1      matt 		data = (uint8_t)addr;
    325      1.1      matt 	} else
    326      1.1      matt 		data |= (addr << 1);
    327      1.1      matt 
    328      1.1      matt 	gttwsi_write_4(sc, TWSI_DATA, data);
    329  1.3.2.2  pgoyette 	return gttwsi_wait(sc, 0, expect, alt, flags);
    330      1.1      matt }
    331      1.1      matt 
    332      1.1      matt static int
    333      1.1      matt gttwsi_read_byte(void *v, uint8_t *valp, int flags)
    334      1.1      matt {
    335      1.1      matt 	struct gttwsi_softc *sc = v;
    336      1.1      matt 	int error;
    337      1.1      matt 
    338  1.3.2.1  pgoyette 	KASSERT(sc->sc_inuse);
    339      1.3  jmcneill 
    340      1.1      matt 	if (flags & I2C_F_LAST)
    341  1.3.2.2  pgoyette 		error = gttwsi_wait(sc, 0, STAT_MRRD_ANT, 0, flags);
    342      1.1      matt 	else
    343  1.3.2.2  pgoyette 		error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, 0, flags);
    344      1.1      matt 	if (!error)
    345      1.1      matt 		*valp = gttwsi_read_4(sc, TWSI_DATA);
    346      1.1      matt 	if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP))
    347      1.1      matt 		error = gttwsi_send_stop(sc, flags);
    348      1.1      matt 	return error;
    349      1.1      matt }
    350      1.1      matt 
    351      1.1      matt static int
    352      1.1      matt gttwsi_write_byte(void *v, uint8_t val, int flags)
    353      1.1      matt {
    354      1.1      matt 	struct gttwsi_softc *sc = v;
    355      1.1      matt 	int error;
    356      1.1      matt 
    357  1.3.2.1  pgoyette 	KASSERT(sc->sc_inuse);
    358      1.3  jmcneill 
    359      1.1      matt 	gttwsi_write_4(sc, TWSI_DATA, val);
    360  1.3.2.2  pgoyette 	error = gttwsi_wait(sc, 0, STAT_MTDB_AR, 0, flags);
    361      1.1      matt 	if (flags & I2C_F_STOP)
    362      1.1      matt 		gttwsi_send_stop(sc, flags);
    363      1.1      matt 	return error;
    364      1.1      matt }
    365      1.1      matt 
    366      1.1      matt static int
    367      1.1      matt gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect,
    368  1.3.2.2  pgoyette 	    uint32_t alt, int flags)
    369      1.1      matt {
    370      1.1      matt 	uint32_t status;
    371      1.1      matt 	int timo, error = 0;
    372      1.1      matt 
    373  1.3.2.1  pgoyette 	KASSERT(sc->sc_inuse);
    374      1.3  jmcneill 
    375      1.1      matt 	DELAY(5);
    376      1.1      matt 	if (!(flags & I2C_F_POLL))
    377      1.1      matt 		control |= CONTROL_INTEN;
    378      1.2  jmcneill 	if (sc->sc_iflg_rwc)
    379      1.2  jmcneill 		control |= CONTROL_IFLG;
    380  1.3.2.3  pgoyette 	mutex_enter(&sc->sc_mtx);
    381      1.1      matt 	gttwsi_write_4(sc, TWSI_CONTROL, control | CONTROL_TWSIEN);
    382      1.1      matt 
    383      1.1      matt 	timo = 0;
    384      1.1      matt 	for (;;) {
    385      1.1      matt 		control = gttwsi_read_4(sc, TWSI_CONTROL);
    386      1.1      matt 		if (control & CONTROL_IFLG)
    387      1.1      matt 			break;
    388      1.1      matt 		if (!(flags & I2C_F_POLL)) {
    389      1.1      matt 			error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz);
    390      1.1      matt 			if (error)
    391  1.3.2.3  pgoyette 				break;
    392  1.3.2.3  pgoyette 		} else {
    393  1.3.2.3  pgoyette 			DELAY(TWSI_RETRY_DELAY);
    394  1.3.2.3  pgoyette 			if (timo++ > 1000000)	/* 1sec */
    395  1.3.2.3  pgoyette 				break;
    396      1.1      matt 		}
    397      1.1      matt 	}
    398  1.3.2.3  pgoyette 	if ((control & CONTROL_IFLG) == 0) {
    399  1.3.2.3  pgoyette 		aprint_error_dev(sc->sc_dev,
    400  1.3.2.3  pgoyette 		    "gttwsi_wait(): timeout, control=0x%x\n", control);
    401  1.3.2.3  pgoyette 		error = EWOULDBLOCK;
    402  1.3.2.3  pgoyette 		goto end;
    403  1.3.2.3  pgoyette 	}
    404      1.1      matt 	status = gttwsi_read_4(sc, TWSI_STATUS);
    405      1.1      matt 	if (status != expect) {
    406  1.3.2.2  pgoyette 		/*
    407  1.3.2.2  pgoyette 		 * In the case of probing for a device, we are expecting
    408  1.3.2.2  pgoyette 		 * 2 different status codes: the ACK case (device exists),
    409  1.3.2.2  pgoyette 		 * or the NACK case (device does not exist).  We don't
    410  1.3.2.2  pgoyette 		 * need to report an error in the later case.
    411  1.3.2.2  pgoyette 		 */
    412  1.3.2.2  pgoyette 		if (alt != 0 && status != alt)
    413  1.3.2.2  pgoyette 			aprint_error_dev(sc->sc_dev,
    414  1.3.2.2  pgoyette 			    "unexpected status 0x%x: expect 0x%x\n", status,
    415  1.3.2.2  pgoyette 			    expect);
    416  1.3.2.3  pgoyette 		error = EIO;
    417      1.1      matt 	}
    418  1.3.2.3  pgoyette end:
    419  1.3.2.3  pgoyette 	mutex_exit(&sc->sc_mtx);
    420      1.1      matt 	return error;
    421      1.1      matt }
    422