gttwsi_core.c revision 1.9 1 1.9 thorpej /* $NetBSD: gttwsi_core.c,v 1.9 2019/12/22 23:23:32 thorpej Exp $ */
2 1.1 matt /*
3 1.1 matt * Copyright (c) 2008 Eiji Kawauchi.
4 1.1 matt * All rights reserved.
5 1.1 matt *
6 1.1 matt * Redistribution and use in source and binary forms, with or without
7 1.1 matt * modification, are permitted provided that the following conditions
8 1.1 matt * are met:
9 1.1 matt * 1. Redistributions of source code must retain the above copyright
10 1.1 matt * notice, this list of conditions and the following disclaimer.
11 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 matt * notice, this list of conditions and the following disclaimer in the
13 1.1 matt * documentation and/or other materials provided with the distribution.
14 1.1 matt * 3. All advertising materials mentioning features or use of this software
15 1.1 matt * must display the following acknowledgement:
16 1.1 matt * This product includes software developed for the NetBSD Project by
17 1.1 matt * Eiji Kawauchi.
18 1.1 matt * 4. The name of the author may not be used to endorse or promote products
19 1.1 matt * derived from this software without specific prior written permission
20 1.1 matt *
21 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1 matt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1 matt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1 matt * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1 matt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1 matt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1 matt * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1 matt * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1 matt * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1 matt * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1 matt */
32 1.1 matt /*
33 1.1 matt * Copyright (c) 2005 Brocade Communcations, inc.
34 1.1 matt * All rights reserved.
35 1.1 matt *
36 1.1 matt * Written by Matt Thomas for Brocade Communcations, Inc.
37 1.1 matt *
38 1.1 matt * Redistribution and use in source and binary forms, with or without
39 1.1 matt * modification, are permitted provided that the following conditions
40 1.1 matt * are met:
41 1.1 matt * 1. Redistributions of source code must retain the above copyright
42 1.1 matt * notice, this list of conditions and the following disclaimer.
43 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
44 1.1 matt * notice, this list of conditions and the following disclaimer in the
45 1.1 matt * documentation and/or other materials provided with the distribution.
46 1.1 matt * 3. The name of Brocade Communications, Inc. may not be used to endorse
47 1.1 matt * or promote products derived from this software without specific prior
48 1.1 matt * written permission.
49 1.1 matt *
50 1.1 matt * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
51 1.1 matt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 1.1 matt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 1.1 matt * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
54 1.1 matt * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
60 1.1 matt * OF THE POSSIBILITY OF SUCH DAMAGE.
61 1.1 matt */
62 1.1 matt //#define TWSI_DEBUG
63 1.1 matt
64 1.1 matt /*
65 1.1 matt * Marvell Two-Wire Serial Interface (aka I2C) master driver
66 1.1 matt */
67 1.1 matt
68 1.1 matt #include <sys/cdefs.h>
69 1.9 thorpej __KERNEL_RCSID(0, "$NetBSD: gttwsi_core.c,v 1.9 2019/12/22 23:23:32 thorpej Exp $");
70 1.1 matt #include "locators.h"
71 1.1 matt
72 1.1 matt #include <sys/param.h>
73 1.1 matt #include <sys/bus.h>
74 1.1 matt #include <sys/condvar.h>
75 1.1 matt #include <sys/device.h>
76 1.1 matt #include <sys/errno.h>
77 1.1 matt #include <sys/kernel.h>
78 1.1 matt #include <sys/mutex.h>
79 1.1 matt #include <sys/systm.h>
80 1.1 matt
81 1.1 matt #include <dev/i2c/i2cvar.h>
82 1.1 matt
83 1.1 matt #include <dev/i2c/gttwsireg.h>
84 1.1 matt #include <dev/i2c/gttwsivar.h>
85 1.1 matt
86 1.1 matt static int gttwsi_send_start(void *v, int flags);
87 1.1 matt static int gttwsi_send_stop(void *v, int flags);
88 1.1 matt static int gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags);
89 1.1 matt static int gttwsi_read_byte(void *v, uint8_t *valp, int flags);
90 1.1 matt static int gttwsi_write_byte(void *v, uint8_t val, int flags);
91 1.1 matt
92 1.6 thorpej static int gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t,
93 1.6 thorpej uint32_t, int);
94 1.1 matt
95 1.1 matt static inline uint32_t
96 1.3 jmcneill gttwsi_default_read_4(struct gttwsi_softc *sc, uint32_t reg)
97 1.1 matt {
98 1.1 matt uint32_t val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
99 1.1 matt #ifdef TWSI_DEBUG
100 1.1 matt printf("I2C:R:%02x:%02x\n", reg, val);
101 1.1 matt #else
102 1.1 matt DELAY(TWSI_READ_DELAY);
103 1.1 matt #endif
104 1.1 matt return val;
105 1.1 matt }
106 1.1 matt
107 1.1 matt static inline void
108 1.3 jmcneill gttwsi_default_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
109 1.1 matt {
110 1.1 matt bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
111 1.1 matt #ifdef TWSI_DEBUG
112 1.1 matt printf("I2C:W:%02x:%02x\n", reg, val);
113 1.1 matt #else
114 1.1 matt DELAY(TWSI_WRITE_DELAY);
115 1.1 matt #endif
116 1.1 matt return;
117 1.1 matt }
118 1.1 matt
119 1.3 jmcneill static inline uint32_t
120 1.3 jmcneill gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg)
121 1.3 jmcneill {
122 1.3 jmcneill return sc->sc_reg_read(sc, reg);
123 1.3 jmcneill }
124 1.1 matt
125 1.3 jmcneill static inline void
126 1.3 jmcneill gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)
127 1.3 jmcneill {
128 1.3 jmcneill return sc->sc_reg_write(sc, reg, val);
129 1.3 jmcneill }
130 1.1 matt
131 1.1 matt /* ARGSUSED */
132 1.1 matt void
133 1.1 matt gttwsi_attach_subr(device_t self, bus_space_tag_t iot, bus_space_handle_t ioh)
134 1.1 matt {
135 1.1 matt struct gttwsi_softc * const sc = device_private(self);
136 1.2 jmcneill prop_dictionary_t cfg = device_properties(self);
137 1.1 matt
138 1.1 matt aprint_naive("\n");
139 1.1 matt aprint_normal(": Marvell TWSI controller\n");
140 1.1 matt
141 1.1 matt sc->sc_dev = self;
142 1.1 matt sc->sc_bust = iot;
143 1.1 matt sc->sc_bush = ioh;
144 1.1 matt
145 1.3 jmcneill if (sc->sc_reg_read == NULL)
146 1.3 jmcneill sc->sc_reg_read = gttwsi_default_read_4;
147 1.3 jmcneill if (sc->sc_reg_write == NULL)
148 1.3 jmcneill sc->sc_reg_write = gttwsi_default_write_4;
149 1.3 jmcneill
150 1.1 matt mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO);
151 1.1 matt cv_init(&sc->sc_cv, device_xname(self));
152 1.1 matt
153 1.2 jmcneill prop_dictionary_get_bool(cfg, "iflg-rwc", &sc->sc_iflg_rwc);
154 1.2 jmcneill
155 1.1 matt sc->sc_started = false;
156 1.9 thorpej iic_tag_init(&sc->sc_i2c);
157 1.1 matt sc->sc_i2c.ic_cookie = sc;
158 1.1 matt sc->sc_i2c.ic_send_start = gttwsi_send_start;
159 1.1 matt sc->sc_i2c.ic_send_stop = gttwsi_send_stop;
160 1.1 matt sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer;
161 1.1 matt sc->sc_i2c.ic_read_byte = gttwsi_read_byte;
162 1.1 matt sc->sc_i2c.ic_write_byte = gttwsi_write_byte;
163 1.1 matt
164 1.1 matt /*
165 1.1 matt * Put the controller into Soft Reset.
166 1.1 matt */
167 1.1 matt /* reset */
168 1.1 matt gttwsi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL);
169 1.1 matt
170 1.1 matt }
171 1.1 matt
172 1.1 matt void
173 1.1 matt gttwsi_config_children(device_t self)
174 1.1 matt {
175 1.1 matt struct gttwsi_softc * const sc = device_private(self);
176 1.1 matt struct i2cbus_attach_args iba;
177 1.1 matt
178 1.1 matt memset(&iba, 0, sizeof(iba));
179 1.1 matt iba.iba_tag = &sc->sc_i2c;
180 1.1 matt
181 1.1 matt (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
182 1.1 matt }
183 1.1 matt
184 1.1 matt int
185 1.1 matt gttwsi_intr(void *arg)
186 1.1 matt {
187 1.1 matt struct gttwsi_softc *sc = arg;
188 1.1 matt uint32_t val;
189 1.1 matt
190 1.8 bouyer mutex_enter(&sc->sc_mtx);
191 1.1 matt val = gttwsi_read_4(sc, TWSI_CONTROL);
192 1.1 matt if (val & CONTROL_IFLG) {
193 1.1 matt gttwsi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
194 1.5 jmcneill cv_broadcast(&sc->sc_cv);
195 1.1 matt mutex_exit(&sc->sc_mtx);
196 1.1 matt return 1; /* handled */
197 1.1 matt }
198 1.8 bouyer mutex_exit(&sc->sc_mtx);
199 1.1 matt return 0;
200 1.1 matt }
201 1.1 matt
202 1.1 matt static int
203 1.1 matt gttwsi_send_start(void *v, int flags)
204 1.1 matt {
205 1.1 matt struct gttwsi_softc *sc = v;
206 1.1 matt int expect;
207 1.1 matt
208 1.5 jmcneill KASSERT(sc->sc_inuse);
209 1.3 jmcneill
210 1.1 matt if (sc->sc_started)
211 1.1 matt expect = STAT_RSCT;
212 1.1 matt else
213 1.1 matt expect = STAT_SCT;
214 1.1 matt sc->sc_started = true;
215 1.6 thorpej return gttwsi_wait(sc, CONTROL_START, expect, 0, flags);
216 1.1 matt }
217 1.1 matt
218 1.1 matt static int
219 1.1 matt gttwsi_send_stop(void *v, int flags)
220 1.1 matt {
221 1.1 matt struct gttwsi_softc *sc = v;
222 1.1 matt int retry = TWSI_RETRY_COUNT;
223 1.2 jmcneill uint32_t control;
224 1.1 matt
225 1.5 jmcneill KASSERT(sc->sc_inuse);
226 1.3 jmcneill
227 1.1 matt sc->sc_started = false;
228 1.1 matt
229 1.1 matt /* Interrupt is not generated for STAT_NRS. */
230 1.2 jmcneill control = CONTROL_STOP | CONTROL_TWSIEN;
231 1.2 jmcneill if (sc->sc_iflg_rwc)
232 1.2 jmcneill control |= CONTROL_IFLG;
233 1.2 jmcneill gttwsi_write_4(sc, TWSI_CONTROL, control);
234 1.1 matt while (retry > 0) {
235 1.1 matt if (gttwsi_read_4(sc, TWSI_STATUS) == STAT_NRS)
236 1.1 matt return 0;
237 1.1 matt retry--;
238 1.1 matt DELAY(TWSI_STAT_DELAY);
239 1.1 matt }
240 1.1 matt
241 1.1 matt aprint_error_dev(sc->sc_dev, "send STOP failed\n");
242 1.1 matt return -1;
243 1.1 matt }
244 1.1 matt
245 1.1 matt static int
246 1.1 matt gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags)
247 1.1 matt {
248 1.1 matt struct gttwsi_softc *sc = v;
249 1.6 thorpej uint32_t data, expect, alt;
250 1.1 matt int error, read;
251 1.1 matt
252 1.5 jmcneill KASSERT(sc->sc_inuse);
253 1.3 jmcneill
254 1.7 jakllsch error = gttwsi_send_start(v, flags);
255 1.7 jakllsch if (error)
256 1.7 jakllsch return error;
257 1.1 matt
258 1.1 matt read = (flags & I2C_F_READ) != 0;
259 1.6 thorpej if (read) {
260 1.1 matt expect = STAT_ARBT_AR;
261 1.6 thorpej alt = STAT_ARBT_ANR;
262 1.6 thorpej } else {
263 1.1 matt expect = STAT_AWBT_AR;
264 1.6 thorpej alt = STAT_AWBT_ANR;
265 1.6 thorpej }
266 1.1 matt
267 1.1 matt /*
268 1.1 matt * First byte contains whether this xfer is a read or write.
269 1.1 matt */
270 1.1 matt data = read;
271 1.1 matt if (addr > 0x7f) {
272 1.1 matt /*
273 1.1 matt * If this is a 10bit request, the first address byte is
274 1.1 matt * 0b11110<b9><b8><r/w>.
275 1.1 matt */
276 1.1 matt data |= 0xf0 | ((addr & 0x300) >> 7);
277 1.1 matt gttwsi_write_4(sc, TWSI_DATA, data);
278 1.6 thorpej error = gttwsi_wait(sc, 0, expect, alt, flags);
279 1.1 matt if (error)
280 1.1 matt return error;
281 1.1 matt /*
282 1.1 matt * The first address byte has been sent, now to send
283 1.1 matt * the second one.
284 1.1 matt */
285 1.6 thorpej if (read) {
286 1.1 matt expect = STAT_SARBT_AR;
287 1.6 thorpej alt = STAT_SARBT_ANR;
288 1.6 thorpej } else {
289 1.1 matt expect = STAT_SAWBT_AR;
290 1.6 thorpej alt = STAT_SAWBT_ANR;
291 1.6 thorpej }
292 1.1 matt data = (uint8_t)addr;
293 1.1 matt } else
294 1.1 matt data |= (addr << 1);
295 1.1 matt
296 1.1 matt gttwsi_write_4(sc, TWSI_DATA, data);
297 1.6 thorpej return gttwsi_wait(sc, 0, expect, alt, flags);
298 1.1 matt }
299 1.1 matt
300 1.1 matt static int
301 1.1 matt gttwsi_read_byte(void *v, uint8_t *valp, int flags)
302 1.1 matt {
303 1.1 matt struct gttwsi_softc *sc = v;
304 1.1 matt int error;
305 1.1 matt
306 1.5 jmcneill KASSERT(sc->sc_inuse);
307 1.3 jmcneill
308 1.1 matt if (flags & I2C_F_LAST)
309 1.6 thorpej error = gttwsi_wait(sc, 0, STAT_MRRD_ANT, 0, flags);
310 1.1 matt else
311 1.6 thorpej error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, 0, flags);
312 1.1 matt if (!error)
313 1.1 matt *valp = gttwsi_read_4(sc, TWSI_DATA);
314 1.1 matt if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP))
315 1.1 matt error = gttwsi_send_stop(sc, flags);
316 1.1 matt return error;
317 1.1 matt }
318 1.1 matt
319 1.1 matt static int
320 1.1 matt gttwsi_write_byte(void *v, uint8_t val, int flags)
321 1.1 matt {
322 1.1 matt struct gttwsi_softc *sc = v;
323 1.1 matt int error;
324 1.1 matt
325 1.5 jmcneill KASSERT(sc->sc_inuse);
326 1.3 jmcneill
327 1.1 matt gttwsi_write_4(sc, TWSI_DATA, val);
328 1.6 thorpej error = gttwsi_wait(sc, 0, STAT_MTDB_AR, 0, flags);
329 1.1 matt if (flags & I2C_F_STOP)
330 1.1 matt gttwsi_send_stop(sc, flags);
331 1.1 matt return error;
332 1.1 matt }
333 1.1 matt
334 1.1 matt static int
335 1.1 matt gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect,
336 1.6 thorpej uint32_t alt, int flags)
337 1.1 matt {
338 1.1 matt uint32_t status;
339 1.1 matt int timo, error = 0;
340 1.1 matt
341 1.5 jmcneill KASSERT(sc->sc_inuse);
342 1.3 jmcneill
343 1.1 matt DELAY(5);
344 1.1 matt if (!(flags & I2C_F_POLL))
345 1.1 matt control |= CONTROL_INTEN;
346 1.2 jmcneill if (sc->sc_iflg_rwc)
347 1.2 jmcneill control |= CONTROL_IFLG;
348 1.8 bouyer mutex_enter(&sc->sc_mtx);
349 1.1 matt gttwsi_write_4(sc, TWSI_CONTROL, control | CONTROL_TWSIEN);
350 1.1 matt
351 1.1 matt timo = 0;
352 1.1 matt for (;;) {
353 1.1 matt control = gttwsi_read_4(sc, TWSI_CONTROL);
354 1.1 matt if (control & CONTROL_IFLG)
355 1.1 matt break;
356 1.1 matt if (!(flags & I2C_F_POLL)) {
357 1.1 matt error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz);
358 1.1 matt if (error)
359 1.8 bouyer break;
360 1.8 bouyer } else {
361 1.8 bouyer DELAY(TWSI_RETRY_DELAY);
362 1.8 bouyer if (timo++ > 1000000) /* 1sec */
363 1.8 bouyer break;
364 1.1 matt }
365 1.1 matt }
366 1.8 bouyer if ((control & CONTROL_IFLG) == 0) {
367 1.8 bouyer aprint_error_dev(sc->sc_dev,
368 1.8 bouyer "gttwsi_wait(): timeout, control=0x%x\n", control);
369 1.8 bouyer error = EWOULDBLOCK;
370 1.8 bouyer goto end;
371 1.8 bouyer }
372 1.1 matt status = gttwsi_read_4(sc, TWSI_STATUS);
373 1.1 matt if (status != expect) {
374 1.6 thorpej /*
375 1.6 thorpej * In the case of probing for a device, we are expecting
376 1.6 thorpej * 2 different status codes: the ACK case (device exists),
377 1.6 thorpej * or the NACK case (device does not exist). We don't
378 1.6 thorpej * need to report an error in the later case.
379 1.6 thorpej */
380 1.6 thorpej if (alt != 0 && status != alt)
381 1.6 thorpej aprint_error_dev(sc->sc_dev,
382 1.6 thorpej "unexpected status 0x%x: expect 0x%x\n", status,
383 1.6 thorpej expect);
384 1.8 bouyer error = EIO;
385 1.1 matt }
386 1.8 bouyer end:
387 1.8 bouyer mutex_exit(&sc->sc_mtx);
388 1.1 matt return error;
389 1.1 matt }
390