gttwsi_core.c revision 1.2.12.1
1 /* $NetBSD: gttwsi_core.c,v 1.2.12.1 2018/10/15 03:09:07 snj Exp $ */ 2 /* 3 * Copyright (c) 2008 Eiji Kawauchi. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed for the NetBSD Project by 17 * Eiji Kawauchi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Copyright (c) 2005 Brocade Communcations, inc. 34 * All rights reserved. 35 * 36 * Written by Matt Thomas for Brocade Communcations, Inc. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. The name of Brocade Communications, Inc. may not be used to endorse 47 * or promote products derived from this software without specific prior 48 * written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE 54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 60 * OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 //#define TWSI_DEBUG 63 64 /* 65 * Marvell Two-Wire Serial Interface (aka I2C) master driver 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: gttwsi_core.c,v 1.2.12.1 2018/10/15 03:09:07 snj Exp $"); 70 #include "locators.h" 71 72 #include <sys/param.h> 73 #include <sys/bus.h> 74 #include <sys/condvar.h> 75 #include <sys/device.h> 76 #include <sys/errno.h> 77 #include <sys/kernel.h> 78 #include <sys/mutex.h> 79 #include <sys/systm.h> 80 81 #include <dev/i2c/i2cvar.h> 82 83 #include <dev/i2c/gttwsireg.h> 84 #include <dev/i2c/gttwsivar.h> 85 86 static int gttwsi_acquire_bus(void *, int); 87 static void gttwsi_release_bus(void *, int); 88 static int gttwsi_send_start(void *v, int flags); 89 static int gttwsi_send_stop(void *v, int flags); 90 static int gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags); 91 static int gttwsi_read_byte(void *v, uint8_t *valp, int flags); 92 static int gttwsi_write_byte(void *v, uint8_t val, int flags); 93 94 static int gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t, 95 uint32_t, int); 96 97 static inline uint32_t 98 gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg) 99 { 100 uint32_t val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg); 101 #ifdef TWSI_DEBUG 102 printf("I2C:R:%02x:%02x\n", reg, val); 103 #else 104 DELAY(TWSI_READ_DELAY); 105 #endif 106 return val; 107 } 108 109 static inline void 110 gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val) 111 { 112 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val); 113 #ifdef TWSI_DEBUG 114 printf("I2C:W:%02x:%02x\n", reg, val); 115 #else 116 DELAY(TWSI_WRITE_DELAY); 117 #endif 118 return; 119 } 120 121 122 123 /* ARGSUSED */ 124 void 125 gttwsi_attach_subr(device_t self, bus_space_tag_t iot, bus_space_handle_t ioh) 126 { 127 struct gttwsi_softc * const sc = device_private(self); 128 prop_dictionary_t cfg = device_properties(self); 129 130 aprint_naive("\n"); 131 aprint_normal(": Marvell TWSI controller\n"); 132 133 sc->sc_dev = self; 134 sc->sc_bust = iot; 135 sc->sc_bush = ioh; 136 137 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_VM); 138 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO); 139 cv_init(&sc->sc_cv, device_xname(self)); 140 141 prop_dictionary_get_bool(cfg, "iflg-rwc", &sc->sc_iflg_rwc); 142 143 sc->sc_started = false; 144 sc->sc_i2c.ic_cookie = sc; 145 sc->sc_i2c.ic_acquire_bus = gttwsi_acquire_bus; 146 sc->sc_i2c.ic_release_bus = gttwsi_release_bus; 147 sc->sc_i2c.ic_exec = NULL; 148 sc->sc_i2c.ic_send_start = gttwsi_send_start; 149 sc->sc_i2c.ic_send_stop = gttwsi_send_stop; 150 sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer; 151 sc->sc_i2c.ic_read_byte = gttwsi_read_byte; 152 sc->sc_i2c.ic_write_byte = gttwsi_write_byte; 153 154 /* 155 * Put the controller into Soft Reset. 156 */ 157 /* reset */ 158 gttwsi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL); 159 160 } 161 162 void 163 gttwsi_config_children(device_t self) 164 { 165 struct gttwsi_softc * const sc = device_private(self); 166 struct i2cbus_attach_args iba; 167 168 memset(&iba, 0, sizeof(iba)); 169 iba.iba_tag = &sc->sc_i2c; 170 171 (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 172 } 173 174 int 175 gttwsi_intr(void *arg) 176 { 177 struct gttwsi_softc *sc = arg; 178 uint32_t val; 179 180 mutex_enter(&sc->sc_mtx); 181 val = gttwsi_read_4(sc, TWSI_CONTROL); 182 if (val & CONTROL_IFLG) { 183 gttwsi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN); 184 cv_broadcast(&sc->sc_cv); 185 mutex_exit(&sc->sc_mtx); 186 return 1; /* handled */ 187 } 188 mutex_exit(&sc->sc_mtx); 189 return 0; 190 } 191 192 /* ARGSUSED */ 193 static int 194 gttwsi_acquire_bus(void *arg, int flags) 195 { 196 struct gttwsi_softc *sc = arg; 197 198 mutex_enter(&sc->sc_buslock); 199 while (sc->sc_inuse) 200 cv_wait(&sc->sc_cv, &sc->sc_buslock); 201 sc->sc_inuse = true; 202 mutex_exit(&sc->sc_buslock); 203 204 return 0; 205 } 206 207 /* ARGSUSED */ 208 static void 209 gttwsi_release_bus(void *arg, int flags) 210 { 211 struct gttwsi_softc *sc = arg; 212 213 mutex_enter(&sc->sc_buslock); 214 sc->sc_inuse = false; 215 cv_broadcast(&sc->sc_cv); 216 mutex_exit(&sc->sc_buslock); 217 } 218 219 static int 220 gttwsi_send_start(void *v, int flags) 221 { 222 struct gttwsi_softc *sc = v; 223 int expect; 224 225 KASSERT(sc->sc_inuse); 226 227 if (sc->sc_started) 228 expect = STAT_RSCT; 229 else 230 expect = STAT_SCT; 231 sc->sc_started = true; 232 return gttwsi_wait(sc, CONTROL_START, expect, 0, flags); 233 } 234 235 static int 236 gttwsi_send_stop(void *v, int flags) 237 { 238 struct gttwsi_softc *sc = v; 239 int retry = TWSI_RETRY_COUNT; 240 uint32_t control; 241 242 KASSERT(sc->sc_inuse); 243 244 sc->sc_started = false; 245 246 /* Interrupt is not generated for STAT_NRS. */ 247 control = CONTROL_STOP | CONTROL_TWSIEN; 248 if (sc->sc_iflg_rwc) 249 control |= CONTROL_IFLG; 250 gttwsi_write_4(sc, TWSI_CONTROL, control); 251 while (retry > 0) { 252 if (gttwsi_read_4(sc, TWSI_STATUS) == STAT_NRS) 253 return 0; 254 retry--; 255 DELAY(TWSI_STAT_DELAY); 256 } 257 258 aprint_error_dev(sc->sc_dev, "send STOP failed\n"); 259 return -1; 260 } 261 262 static int 263 gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags) 264 { 265 struct gttwsi_softc *sc = v; 266 uint32_t data, expect, alt; 267 int error, read; 268 269 KASSERT(sc->sc_inuse); 270 271 error = gttwsi_send_start(v, flags); 272 if (error) 273 return error; 274 275 read = (flags & I2C_F_READ) != 0; 276 if (read) { 277 expect = STAT_ARBT_AR; 278 alt = STAT_ARBT_ANR; 279 } else { 280 expect = STAT_AWBT_AR; 281 alt = STAT_AWBT_ANR; 282 } 283 284 /* 285 * First byte contains whether this xfer is a read or write. 286 */ 287 data = read; 288 if (addr > 0x7f) { 289 /* 290 * If this is a 10bit request, the first address byte is 291 * 0b11110<b9><b8><r/w>. 292 */ 293 data |= 0xf0 | ((addr & 0x300) >> 7); 294 gttwsi_write_4(sc, TWSI_DATA, data); 295 error = gttwsi_wait(sc, 0, expect, alt, flags); 296 if (error) 297 return error; 298 /* 299 * The first address byte has been sent, now to send 300 * the second one. 301 */ 302 if (read) { 303 expect = STAT_SARBT_AR; 304 alt = STAT_SARBT_ANR; 305 } else { 306 expect = STAT_SAWBT_AR; 307 alt = STAT_SAWBT_ANR; 308 } 309 data = (uint8_t)addr; 310 } else 311 data |= (addr << 1); 312 313 gttwsi_write_4(sc, TWSI_DATA, data); 314 return gttwsi_wait(sc, 0, expect, alt, flags); 315 } 316 317 static int 318 gttwsi_read_byte(void *v, uint8_t *valp, int flags) 319 { 320 struct gttwsi_softc *sc = v; 321 int error; 322 323 KASSERT(sc->sc_inuse); 324 325 if (flags & I2C_F_LAST) 326 error = gttwsi_wait(sc, 0, STAT_MRRD_ANT, 0, flags); 327 else 328 error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, 0, flags); 329 if (!error) 330 *valp = gttwsi_read_4(sc, TWSI_DATA); 331 if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP)) 332 error = gttwsi_send_stop(sc, flags); 333 return error; 334 } 335 336 static int 337 gttwsi_write_byte(void *v, uint8_t val, int flags) 338 { 339 struct gttwsi_softc *sc = v; 340 int error; 341 342 KASSERT(sc->sc_inuse); 343 344 gttwsi_write_4(sc, TWSI_DATA, val); 345 error = gttwsi_wait(sc, 0, STAT_MTDB_AR, 0, flags); 346 if (flags & I2C_F_STOP) 347 gttwsi_send_stop(sc, flags); 348 return error; 349 } 350 351 static int 352 gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect, 353 uint32_t alt, int flags) 354 { 355 uint32_t status; 356 int timo, error = 0; 357 358 KASSERT(sc->sc_inuse); 359 360 DELAY(5); 361 if (!(flags & I2C_F_POLL)) 362 control |= CONTROL_INTEN; 363 if (sc->sc_iflg_rwc) 364 control |= CONTROL_IFLG; 365 mutex_enter(&sc->sc_mtx); 366 gttwsi_write_4(sc, TWSI_CONTROL, control | CONTROL_TWSIEN); 367 368 timo = 0; 369 for (;;) { 370 control = gttwsi_read_4(sc, TWSI_CONTROL); 371 if (control & CONTROL_IFLG) 372 break; 373 if (!(flags & I2C_F_POLL)) { 374 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz); 375 if (error) 376 break; 377 } else { 378 DELAY(TWSI_RETRY_DELAY); 379 if (timo++ > 1000000) /* 1sec */ 380 break; 381 } 382 } 383 if ((control & CONTROL_IFLG) == 0) { 384 aprint_error_dev(sc->sc_dev, 385 "gttwsi_wait(): timeout, control=0x%x\n", control); 386 error = EWOULDBLOCK; 387 goto end; 388 } 389 status = gttwsi_read_4(sc, TWSI_STATUS); 390 if (status != expect) { 391 /* 392 * In the case of probing for a device, we are expecting 393 * 2 different status codes: the ACK case (device exists), 394 * or the NACK case (device does not exist). We don't 395 * need to report an error in the later case. 396 */ 397 if (alt != 0 && status != alt) 398 aprint_error_dev(sc->sc_dev, 399 "unexpected status 0x%x: expect 0x%x\n", status, 400 expect); 401 error = EIO; 402 } 403 end: 404 mutex_exit(&sc->sc_mtx); 405 return error; 406 } 407
Indexes created Sun Oct 12 05:10:08 GMT 2025