i2c_bitbang.c revision 1.1.4.3 1 1.1.4.3 skrll /* $NetBSD: i2c_bitbang.c,v 1.1.4.3 2004/09/18 14:45:47 skrll Exp $ */
2 1.1.4.2 skrll
3 1.1.4.2 skrll /*
4 1.1.4.2 skrll * Copyright (c) 2003 Wasabi Systems, Inc.
5 1.1.4.2 skrll * All rights reserved.
6 1.1.4.2 skrll *
7 1.1.4.2 skrll * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 1.1.4.2 skrll *
9 1.1.4.2 skrll * Redistribution and use in source and binary forms, with or without
10 1.1.4.2 skrll * modification, are permitted provided that the following conditions
11 1.1.4.2 skrll * are met:
12 1.1.4.2 skrll * 1. Redistributions of source code must retain the above copyright
13 1.1.4.2 skrll * notice, this list of conditions and the following disclaimer.
14 1.1.4.2 skrll * 2. Redistributions in binary form must reproduce the above copyright
15 1.1.4.2 skrll * notice, this list of conditions and the following disclaimer in the
16 1.1.4.2 skrll * documentation and/or other materials provided with the distribution.
17 1.1.4.2 skrll * 3. All advertising materials mentioning features or use of this software
18 1.1.4.2 skrll * must display the following acknowledgement:
19 1.1.4.2 skrll * This product includes software developed for the NetBSD Project by
20 1.1.4.2 skrll * Wasabi Systems, Inc.
21 1.1.4.2 skrll * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1.4.2 skrll * or promote products derived from this software without specific prior
23 1.1.4.2 skrll * written permission.
24 1.1.4.2 skrll *
25 1.1.4.2 skrll * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1.4.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1.4.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1.4.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1.4.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1.4.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1.4.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1.4.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1.4.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1.4.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1.4.2 skrll * POSSIBILITY OF SUCH DAMAGE.
36 1.1.4.2 skrll */
37 1.1.4.2 skrll
38 1.1.4.2 skrll /*
39 1.1.4.2 skrll * Common module for bit-bang'ing an I2C bus.
40 1.1.4.2 skrll */
41 1.1.4.2 skrll
42 1.1.4.2 skrll #include <sys/param.h>
43 1.1.4.2 skrll
44 1.1.4.2 skrll #include <dev/i2c/i2cvar.h>
45 1.1.4.2 skrll #include <dev/i2c/i2c_bitbang.h>
46 1.1.4.2 skrll
47 1.1.4.2 skrll #define SET(x) ops->ibo_set_bits(v, (x))
48 1.1.4.2 skrll #define DIR(x) ops->ibo_set_dir(v, (x))
49 1.1.4.2 skrll #define READ ops->ibo_read_bits(v)
50 1.1.4.2 skrll
51 1.1.4.2 skrll #define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */
52 1.1.4.2 skrll #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */
53 1.1.4.2 skrll #define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */
54 1.1.4.2 skrll #define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */
55 1.1.4.2 skrll
56 1.1.4.2 skrll /*ARGSUSED*/
57 1.1.4.2 skrll int
58 1.1.4.2 skrll i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops)
59 1.1.4.2 skrll {
60 1.1.4.2 skrll
61 1.1.4.2 skrll DIR(OUTPUT);
62 1.1.4.2 skrll
63 1.1.4.2 skrll SET(SDA | SCL);
64 1.1.4.2 skrll delay(5); /* bus free time (4.7 uS) */
65 1.1.4.2 skrll SET( SCL);
66 1.1.4.2 skrll delay(4); /* start hold time (4.0 uS) */
67 1.1.4.2 skrll SET( 0);
68 1.1.4.2 skrll delay(5); /* clock low time (4.7 uS) */
69 1.1.4.2 skrll
70 1.1.4.2 skrll return (0);
71 1.1.4.2 skrll }
72 1.1.4.2 skrll
73 1.1.4.2 skrll /*ARGSUSED*/
74 1.1.4.2 skrll int
75 1.1.4.2 skrll i2c_bitbang_send_stop(void *v, int flags, i2c_bitbang_ops_t ops)
76 1.1.4.2 skrll {
77 1.1.4.2 skrll
78 1.1.4.2 skrll DIR(OUTPUT);
79 1.1.4.2 skrll
80 1.1.4.2 skrll SET( SCL);
81 1.1.4.2 skrll delay(4); /* stop setup time (4.0 uS) */
82 1.1.4.2 skrll SET(SDA | SCL);
83 1.1.4.2 skrll
84 1.1.4.2 skrll return (0);
85 1.1.4.2 skrll }
86 1.1.4.2 skrll
87 1.1.4.2 skrll int
88 1.1.4.2 skrll i2c_bitbang_initiate_xfer(void *v, i2c_addr_t addr, int flags,
89 1.1.4.2 skrll i2c_bitbang_ops_t ops)
90 1.1.4.2 skrll {
91 1.1.4.2 skrll int i2caddr;
92 1.1.4.2 skrll
93 1.1.4.2 skrll /* XXX Only support 7-bit addressing for now. */
94 1.1.4.2 skrll if ((addr & 0x78) == 0x78)
95 1.1.4.2 skrll return (EINVAL);
96 1.1.4.2 skrll
97 1.1.4.2 skrll i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0);
98 1.1.4.2 skrll
99 1.1.4.2 skrll (void) i2c_bitbang_send_start(v, flags, ops);
100 1.1.4.2 skrll return (i2c_bitbang_write_byte(v, i2caddr, flags & ~I2C_F_STOP, ops));
101 1.1.4.2 skrll }
102 1.1.4.2 skrll
103 1.1.4.2 skrll int
104 1.1.4.2 skrll i2c_bitbang_read_byte(void *v, uint8_t *valp, int flags,
105 1.1.4.2 skrll i2c_bitbang_ops_t ops)
106 1.1.4.2 skrll {
107 1.1.4.2 skrll int i;
108 1.1.4.2 skrll uint8_t val = 0;
109 1.1.4.2 skrll uint32_t bit;
110 1.1.4.2 skrll
111 1.1.4.2 skrll DIR(INPUT);
112 1.1.4.2 skrll SET(SDA );
113 1.1.4.2 skrll
114 1.1.4.2 skrll for (i = 0; i < 8; i++) {
115 1.1.4.2 skrll val <<= 1;
116 1.1.4.2 skrll SET(SDA | SCL);
117 1.1.4.2 skrll delay(4); /* clock high time (4.0 uS) */
118 1.1.4.2 skrll if (READ & SDA)
119 1.1.4.2 skrll val |= 1;
120 1.1.4.2 skrll SET(SDA );
121 1.1.4.2 skrll delay(5); /* clock low time (4.7 uS) */
122 1.1.4.2 skrll }
123 1.1.4.2 skrll
124 1.1.4.2 skrll bit = (flags & I2C_F_LAST) ? SDA : 0;
125 1.1.4.2 skrll DIR(OUTPUT);
126 1.1.4.2 skrll SET(bit );
127 1.1.4.2 skrll delay(1); /* data setup time (250 nS) */
128 1.1.4.2 skrll SET(bit | SCL);
129 1.1.4.2 skrll delay(4); /* clock high time (4.0 uS) */
130 1.1.4.2 skrll SET(bit );
131 1.1.4.2 skrll delay(5); /* clock low time (4.7 uS) */
132 1.1.4.2 skrll
133 1.1.4.2 skrll DIR(INPUT);
134 1.1.4.2 skrll SET(SDA );
135 1.1.4.2 skrll delay(5);
136 1.1.4.2 skrll
137 1.1.4.2 skrll if ((flags & (I2C_F_STOP | I2C_F_LAST)) == (I2C_F_STOP | I2C_F_LAST))
138 1.1.4.2 skrll (void) i2c_bitbang_send_stop(v, flags, ops);
139 1.1.4.2 skrll
140 1.1.4.2 skrll *valp = val;
141 1.1.4.2 skrll return (0);
142 1.1.4.2 skrll }
143 1.1.4.2 skrll
144 1.1.4.2 skrll int
145 1.1.4.2 skrll i2c_bitbang_write_byte(void *v, uint8_t val, int flags,
146 1.1.4.2 skrll i2c_bitbang_ops_t ops)
147 1.1.4.2 skrll {
148 1.1.4.2 skrll uint32_t bit;
149 1.1.4.2 skrll uint8_t mask;
150 1.1.4.2 skrll int error;
151 1.1.4.2 skrll
152 1.1.4.2 skrll DIR(OUTPUT);
153 1.1.4.2 skrll
154 1.1.4.2 skrll for (mask = 0x80; mask != 0; mask >>= 1) {
155 1.1.4.2 skrll bit = (val & mask) ? SDA : 0;
156 1.1.4.2 skrll SET(bit );
157 1.1.4.2 skrll delay(1); /* data setup time (250 nS) */
158 1.1.4.2 skrll SET(bit | SCL);
159 1.1.4.2 skrll delay(4); /* clock high time (4.0 uS) */
160 1.1.4.2 skrll SET(bit );
161 1.1.4.2 skrll delay(5); /* clock low time (4.7 uS) */
162 1.1.4.2 skrll }
163 1.1.4.2 skrll
164 1.1.4.2 skrll DIR(INPUT);
165 1.1.4.2 skrll
166 1.1.4.2 skrll SET(SDA );
167 1.1.4.2 skrll delay(5);
168 1.1.4.2 skrll SET(SDA | SCL);
169 1.1.4.2 skrll delay(4);
170 1.1.4.2 skrll error = (READ & SDA) ? EIO : 0;
171 1.1.4.2 skrll SET(SDA );
172 1.1.4.2 skrll delay(5);
173 1.1.4.2 skrll
174 1.1.4.2 skrll if (flags & I2C_F_STOP)
175 1.1.4.2 skrll (void) i2c_bitbang_send_stop(v, flags, ops);
176 1.1.4.2 skrll
177 1.1.4.2 skrll return (error);
178 1.1.4.2 skrll }
179