i2c_bitbang.c revision 1.10
1 /* $NetBSD: i2c_bitbang.c,v 1.10 2008/05/31 18:26:43 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Common module for bit-bang'ing an I2C bus. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i2c_bitbang.c,v 1.10 2008/05/31 18:26:43 tsutsui Exp $"); 44 45 #include <sys/param.h> 46 47 #include <dev/i2c/i2cvar.h> 48 #include <dev/i2c/i2c_bitbang.h> 49 50 #define SETBITS(x) ops->ibo_set_bits(v, (x)) 51 #define DIR(x) ops->ibo_set_dir(v, (x)) 52 #define READ ops->ibo_read_bits(v) 53 54 #define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */ 55 #define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */ 56 #define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */ 57 #define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */ 58 59 #ifndef SCL_BAIL_COUNT 60 #define SCL_BAIL_COUNT 1000 61 #endif 62 63 static inline int i2c_wait_for_scl(void *, i2c_bitbang_ops_t); 64 65 static inline int 66 i2c_wait_for_scl(void *v, i2c_bitbang_ops_t ops) 67 { 68 int bail = 0; 69 70 DIR(INPUT); 71 72 while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) { 73 delay(1); 74 bail++; 75 } 76 if (bail == SCL_BAIL_COUNT) { 77 i2c_bitbang_send_stop(v, 0, ops); 78 return EIO; 79 } 80 return 0; 81 } 82 83 /*ARGSUSED*/ 84 int 85 i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops) 86 { 87 88 DIR(OUTPUT); 89 SETBITS(SDA | SCL); 90 delay(5); /* bus free time (4.7 us) */ 91 SETBITS( SCL); 92 93 if (i2c_wait_for_scl(v, ops) != 0) 94 return EIO; 95 delay(4); /* start hold time (4.0 us) */ 96 97 DIR(OUTPUT); 98 SETBITS( 0); 99 delay(5); /* clock low time (4.7 us) */ 100 101 return 0; 102 } 103 104 /*ARGSUSED*/ 105 int 106 i2c_bitbang_send_stop(void *v, int flags, i2c_bitbang_ops_t ops) 107 { 108 109 DIR(OUTPUT); 110 SETBITS( SCL); 111 delay(4); /* stop setup time (4.0 us) */ 112 SETBITS(SDA | SCL); 113 114 return 0; 115 } 116 117 int 118 i2c_bitbang_initiate_xfer(void *v, i2c_addr_t addr, int flags, 119 i2c_bitbang_ops_t ops) 120 { 121 122 if (addr < 0x80) { 123 uint8_t i2caddr; 124 125 /* disallow the 10-bit address prefix */ 126 if ((addr & 0x78) == 0x78) 127 return EINVAL; 128 i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0); 129 (void) i2c_bitbang_send_start(v, flags, ops); 130 131 return (i2c_bitbang_write_byte(v, i2caddr, 132 flags & ~I2C_F_STOP, ops)); 133 134 } else if (addr < 0x400) { 135 uint16_t i2caddr; 136 int rv; 137 138 i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0) | 139 0xf000; 140 141 (void) i2c_bitbang_send_start(v, flags, ops); 142 rv = i2c_bitbang_write_byte(v, i2caddr >> 8, 143 flags & ~I2C_F_STOP, ops); 144 /* did a slave ack the 10-bit prefix? */ 145 if (rv != 0) 146 return rv; 147 148 /* send the lower 7-bits (+ read/write mode) */ 149 return (i2c_bitbang_write_byte(v, i2caddr & 0xff, 150 flags & ~I2C_F_STOP, ops)); 151 152 } else 153 return EINVAL; 154 } 155 156 int 157 i2c_bitbang_read_byte(void *v, uint8_t *valp, int flags, i2c_bitbang_ops_t ops) 158 { 159 int i; 160 uint8_t val = 0; 161 uint32_t bit; 162 163 DIR(OUTPUT); 164 SETBITS(SDA ); 165 166 for (i = 0; i < 8; i++) { 167 val <<= 1; 168 169 DIR(OUTPUT); 170 SETBITS(SDA | SCL); 171 172 if (i2c_wait_for_scl(v, ops) != 0) 173 return EIO; 174 delay(4); /* clock high time (4.0 us) */ 175 176 DIR(INPUT); 177 if (READ & SDA) 178 val |= 1; 179 180 DIR(OUTPUT); 181 SETBITS(SDA ); 182 delay(5); /* clock low time (4.7 us) */ 183 } 184 185 bit = (flags & I2C_F_LAST) ? SDA : 0; 186 187 DIR(OUTPUT); 188 SETBITS(bit ); 189 delay(1); /* data setup time (250 ns) */ 190 SETBITS(bit | SCL); 191 192 if (i2c_wait_for_scl(v, ops) != 0) 193 return EIO; 194 delay(4); /* clock high time (4.0 us) */ 195 196 DIR(OUTPUT); 197 SETBITS(bit ); 198 delay(5); /* clock low time (4.7 us) */ 199 200 DIR(INPUT); 201 SETBITS(SDA ); 202 delay(5); 203 204 if ((flags & (I2C_F_STOP | I2C_F_LAST)) == (I2C_F_STOP | I2C_F_LAST)) 205 (void) i2c_bitbang_send_stop(v, flags, ops); 206 207 *valp = val; 208 return 0; 209 } 210 211 int 212 i2c_bitbang_write_byte(void *v, uint8_t val, int flags, i2c_bitbang_ops_t ops) 213 { 214 uint32_t bit; 215 uint8_t mask; 216 int error; 217 218 for (mask = 0x80; mask != 0; mask >>= 1) { 219 bit = (val & mask) ? SDA : 0; 220 221 DIR(OUTPUT); 222 SETBITS(bit ); 223 delay(1); /* data setup time (250 ns) */ 224 SETBITS(bit | SCL); 225 226 if (i2c_wait_for_scl(v, ops)) 227 return EIO; 228 delay(4); /* clock high time (4.0 us) */ 229 230 DIR(OUTPUT); 231 SETBITS(bit ); 232 delay(5); /* clock low time (4.7 us) */ 233 } 234 235 DIR(OUTPUT); 236 SETBITS(SDA ); 237 delay(5); 238 SETBITS(SDA | SCL); 239 240 if (i2c_wait_for_scl(v, ops) != 0) 241 return EIO; 242 delay(4); 243 244 DIR(INPUT); 245 error = (READ & SDA) ? EIO : 0; 246 247 DIR(OUTPUT); 248 SETBITS(SDA ); 249 delay(5); 250 251 if (flags & I2C_F_STOP) 252 (void) i2c_bitbang_send_stop(v, flags, ops); 253 254 return error; 255 } 256
Indexes created Tue Sep 23 07:09:52 GMT 2025