m41st84.c revision 1.11
1 /* $NetBSD: m41st84.c,v 1.11 2008/04/06 20:25:59 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.11 2008/04/06 20:25:59 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/m41st84reg.h> 54 55 struct strtc_softc { 56 struct device sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void strtc_attach(struct device *, struct device *, void *); 64 static int strtc_match(struct device *, struct cfdata *, void *); 65 66 CFATTACH_DECL(strtc, sizeof(struct strtc_softc), 67 strtc_match, strtc_attach, NULL, NULL); 68 extern struct cfdriver strtc_cd; 69 70 dev_type_open(strtc_open); 71 dev_type_close(strtc_close); 72 dev_type_read(strtc_read); 73 dev_type_write(strtc_write); 74 75 const struct cdevsw strtc_cdevsw = { 76 strtc_open, strtc_close, strtc_read, strtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int strtc_clock_read(struct strtc_softc *, struct clock_ymdhms *); 81 static int strtc_clock_write(struct strtc_softc *, struct clock_ymdhms *); 82 static int strtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 83 static int strtc_settime(struct todr_chip_handle *, volatile struct timeval *); 84 85 static int 86 strtc_match(struct device *parent, struct cfdata *cf, void *arg) 87 { 88 struct i2c_attach_args *ia = arg; 89 90 if (ia->ia_addr == M41ST84_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 static void 97 strtc_attach(struct device *parent, struct device *self, void *arg) 98 { 99 struct strtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = arg; 101 102 aprint_naive(": Real-time Clock/NVRAM\n"); 103 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 104 105 sc->sc_tag = ia->ia_tag; 106 sc->sc_address = ia->ia_addr; 107 sc->sc_open = 0; 108 sc->sc_todr.cookie = sc; 109 sc->sc_todr.todr_gettime = strtc_gettime; 110 sc->sc_todr.todr_settime = strtc_settime; 111 sc->sc_todr.todr_setwen = NULL; 112 113 todr_attach(&sc->sc_todr); 114 } 115 116 /*ARGSUSED*/ 117 int 118 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 119 { 120 struct strtc_softc *sc; 121 122 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 123 return (ENXIO); 124 125 /* XXX: Locking */ 126 127 if (sc->sc_open) 128 return (EBUSY); 129 130 sc->sc_open = 1; 131 return (0); 132 } 133 134 /*ARGSUSED*/ 135 int 136 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 137 { 138 struct strtc_softc *sc; 139 140 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 141 return (ENXIO); 142 143 sc->sc_open = 0; 144 return (0); 145 } 146 147 /*ARGSUSED*/ 148 int 149 strtc_read(dev_t dev, struct uio *uio, int flags) 150 { 151 struct strtc_softc *sc; 152 u_int8_t ch, cmdbuf[1]; 153 int a, error; 154 155 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 156 return (ENXIO); 157 158 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 159 return (EINVAL); 160 161 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 162 return (error); 163 164 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 165 a = (int)uio->uio_offset; 166 cmdbuf[0] = a + M41ST84_USER_RAM; 167 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 168 sc->sc_address, cmdbuf, 1, 169 &ch, 1, 0)) != 0) { 170 iic_release_bus(sc->sc_tag, 0); 171 aprint_error_dev(&sc->sc_dev, "strtc_read: read failed at 0x%x\n", a); 172 return (error); 173 } 174 if ((error = uiomove(&ch, 1, uio)) != 0) { 175 iic_release_bus(sc->sc_tag, 0); 176 return (error); 177 } 178 } 179 180 iic_release_bus(sc->sc_tag, 0); 181 182 return (0); 183 } 184 185 /*ARGSUSED*/ 186 int 187 strtc_write(dev_t dev, struct uio *uio, int flags) 188 { 189 struct strtc_softc *sc; 190 u_int8_t cmdbuf[2]; 191 int a, error; 192 193 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 194 return (ENXIO); 195 196 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 197 return (EINVAL); 198 199 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 200 return (error); 201 202 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 203 a = (int)uio->uio_offset; 204 cmdbuf[0] = a + M41ST84_USER_RAM; 205 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 206 break; 207 208 if ((error = iic_exec(sc->sc_tag, 209 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 210 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 211 aprint_error_dev(&sc->sc_dev, "strtc_write: write failed at 0x%x\n", a); 212 break; 213 } 214 } 215 216 iic_release_bus(sc->sc_tag, 0); 217 218 return (error); 219 } 220 221 static int 222 strtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 223 { 224 struct strtc_softc *sc = ch->cookie; 225 struct clock_ymdhms dt, check; 226 int retries; 227 228 memset(&dt, 0, sizeof(dt)); 229 memset(&check, 0, sizeof(check)); 230 231 /* 232 * Since we don't support Burst Read, we have to read the clock twice 233 * until we get two consecutive identical results. 234 */ 235 retries = 5; 236 do { 237 strtc_clock_read(sc, &dt); 238 strtc_clock_read(sc, &check); 239 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 240 241 tv->tv_sec = clock_ymdhms_to_secs(&dt); 242 tv->tv_usec = 0; 243 244 return (0); 245 } 246 247 static int 248 strtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 249 { 250 struct strtc_softc *sc = ch->cookie; 251 struct clock_ymdhms dt; 252 253 clock_secs_to_ymdhms(tv->tv_sec, &dt); 254 255 if (strtc_clock_write(sc, &dt) == 0) 256 return (-1); 257 258 return (0); 259 } 260 261 static int 262 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 263 { 264 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[1]; 265 int i; 266 267 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 268 aprint_error_dev(&sc->sc_dev, "strtc_clock_read: failed to acquire I2C bus\n"); 269 return (0); 270 } 271 272 /* 273 * Check for the HT bit -- if set, then clock lost power & stopped 274 * If that happened, then clear the bit so that the clock will have 275 * a chance to run again. 276 */ 277 cmdbuf[0] = M41ST84_REG_AL_HOUR; 278 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 279 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 280 iic_release_bus(sc->sc_tag, I2C_F_POLL); 281 aprint_error_dev(&sc->sc_dev, "strtc_clock_read: failed to read HT\n"); 282 return (0); 283 } 284 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 285 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 286 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 287 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 288 iic_release_bus(sc->sc_tag, I2C_F_POLL); 289 aprint_error_dev(&sc->sc_dev, "strtc_clock_read: failed to reset HT\n"); 290 return (0); 291 } 292 } 293 294 /* Read each RTC register in order. */ 295 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 296 cmdbuf[0] = i; 297 298 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 299 sc->sc_address, cmdbuf, 1, 300 &bcd[i], 1, I2C_F_POLL)) { 301 iic_release_bus(sc->sc_tag, I2C_F_POLL); 302 aprint_error_dev(&sc->sc_dev, "strtc_clock_read: failed to read rtc " 303 "at 0x%x\n", i); 304 return (0); 305 } 306 } 307 308 /* Done with I2C */ 309 iic_release_bus(sc->sc_tag, I2C_F_POLL); 310 311 /* 312 * Convert the M41ST84's register values into something useable 313 */ 314 dt->dt_sec = FROMBCD(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 315 dt->dt_min = FROMBCD(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 316 dt->dt_hour = FROMBCD(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 317 dt->dt_day = FROMBCD(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 318 dt->dt_mon = FROMBCD(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 319 320 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 321 dt->dt_year = FROMBCD(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 322 323 return (1); 324 } 325 326 static int 327 strtc_clock_write(struct strtc_softc *sc, struct clock_ymdhms *dt) 328 { 329 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 330 int i; 331 332 /* 333 * Convert our time representation into something the M41ST84 334 * can understand. 335 */ 336 bcd[M41ST84_REG_CSEC] = TOBCD(0); /* must always write as 0 */ 337 bcd[M41ST84_REG_SEC] = TOBCD(dt->dt_sec); 338 bcd[M41ST84_REG_MIN] = TOBCD(dt->dt_min); 339 bcd[M41ST84_REG_CENHR] = TOBCD(dt->dt_hour); 340 bcd[M41ST84_REG_DATE] = TOBCD(dt->dt_day); 341 bcd[M41ST84_REG_DAY] = TOBCD(dt->dt_wday); 342 bcd[M41ST84_REG_MONTH] = TOBCD(dt->dt_mon); 343 bcd[M41ST84_REG_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 344 345 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 346 aprint_error_dev(&sc->sc_dev, "strtc_clock_write: failed to acquire I2C bus\n"); 347 return (0); 348 } 349 350 /* Stop the clock */ 351 cmdbuf[0] = M41ST84_REG_SEC; 352 cmdbuf[1] = M41ST84_SEC_ST; 353 354 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 355 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 356 iic_release_bus(sc->sc_tag, I2C_F_POLL); 357 aprint_error_dev(&sc->sc_dev, "strtc_clock_write: failed to Hold Clock\n"); 358 return (0); 359 } 360 361 /* 362 * Check for the HT bit -- if set, then clock lost power & stopped 363 * If that happened, then clear the bit so that the clock will have 364 * a chance to run again. 365 */ 366 cmdbuf[0] = M41ST84_REG_AL_HOUR; 367 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 368 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 369 iic_release_bus(sc->sc_tag, I2C_F_POLL); 370 aprint_error_dev(&sc->sc_dev, "strtc_clock_write: failed to read HT\n"); 371 return (0); 372 } 373 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 374 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 375 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 376 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 377 iic_release_bus(sc->sc_tag, I2C_F_POLL); 378 aprint_error_dev(&sc->sc_dev, "strtc_clock_write: failed to reset HT\n"); 379 return (0); 380 } 381 } 382 383 /* 384 * Write registers in reverse order. The last write (to the Seconds 385 * register) will undo the Clock Hold, above. 386 */ 387 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 388 cmdbuf[0] = i; 389 if (iic_exec(sc->sc_tag, 390 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 391 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 392 I2C_F_POLL)) { 393 iic_release_bus(sc->sc_tag, I2C_F_POLL); 394 aprint_error_dev(&sc->sc_dev, "strtc_clock_write: failed to write rtc " 395 " at 0x%x\n", i); 396 /* XXX: Clock Hold is likely still asserted! */ 397 return (0); 398 } 399 } 400 401 iic_release_bus(sc->sc_tag, I2C_F_POLL); 402 403 return (1); 404 } 405
Indexes created Thu Sep 25 16:09:42 GMT 2025