m41st84.c revision 1.12
1 /* $NetBSD: m41st84.c,v 1.12 2008/05/04 15:26:29 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.12 2008/05/04 15:26:29 xtraeme Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/m41st84reg.h> 54 55 struct strtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static void strtc_attach(device_t, device_t, void *); 64 static int strtc_match(device_t, cfdata_t, void *); 65 66 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 67 strtc_match, strtc_attach, NULL, NULL); 68 extern struct cfdriver strtc_cd; 69 70 dev_type_open(strtc_open); 71 dev_type_close(strtc_close); 72 dev_type_read(strtc_read); 73 dev_type_write(strtc_write); 74 75 const struct cdevsw strtc_cdevsw = { 76 strtc_open, strtc_close, strtc_read, strtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int strtc_clock_read(struct strtc_softc *, struct clock_ymdhms *); 81 static int strtc_clock_write(struct strtc_softc *, struct clock_ymdhms *); 82 static int strtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 83 static int strtc_settime(struct todr_chip_handle *, volatile struct timeval *); 84 85 static int 86 strtc_match(device_t parent, cfdata_t cf, void *arg) 87 { 88 struct i2c_attach_args *ia = arg; 89 90 if (ia->ia_addr == M41ST84_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 static void 97 strtc_attach(device_t parent, device_t self, void *arg) 98 { 99 struct strtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = arg; 101 102 aprint_naive(": Real-time Clock/NVRAM\n"); 103 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 104 105 sc->sc_tag = ia->ia_tag; 106 sc->sc_address = ia->ia_addr; 107 sc->sc_dev = self; 108 sc->sc_open = 0; 109 sc->sc_todr.cookie = sc; 110 sc->sc_todr.todr_gettime = strtc_gettime; 111 sc->sc_todr.todr_settime = strtc_settime; 112 sc->sc_todr.todr_setwen = NULL; 113 114 todr_attach(&sc->sc_todr); 115 } 116 117 /*ARGSUSED*/ 118 int 119 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 120 { 121 struct strtc_softc *sc; 122 123 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 124 return (ENXIO); 125 126 /* XXX: Locking */ 127 128 if (sc->sc_open) 129 return (EBUSY); 130 131 sc->sc_open = 1; 132 return (0); 133 } 134 135 /*ARGSUSED*/ 136 int 137 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 138 { 139 struct strtc_softc *sc; 140 141 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 142 return (ENXIO); 143 144 sc->sc_open = 0; 145 return (0); 146 } 147 148 /*ARGSUSED*/ 149 int 150 strtc_read(dev_t dev, struct uio *uio, int flags) 151 { 152 struct strtc_softc *sc; 153 u_int8_t ch, cmdbuf[1]; 154 int a, error; 155 156 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 157 return (ENXIO); 158 159 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 160 return (EINVAL); 161 162 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 163 return (error); 164 165 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 166 a = (int)uio->uio_offset; 167 cmdbuf[0] = a + M41ST84_USER_RAM; 168 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 169 sc->sc_address, cmdbuf, 1, 170 &ch, 1, 0)) != 0) { 171 iic_release_bus(sc->sc_tag, 0); 172 aprint_error_dev(sc->sc_dev, 173 "strtc_read: read failed at 0x%x\n", a); 174 return (error); 175 } 176 if ((error = uiomove(&ch, 1, uio)) != 0) { 177 iic_release_bus(sc->sc_tag, 0); 178 return (error); 179 } 180 } 181 182 iic_release_bus(sc->sc_tag, 0); 183 184 return (0); 185 } 186 187 /*ARGSUSED*/ 188 int 189 strtc_write(dev_t dev, struct uio *uio, int flags) 190 { 191 struct strtc_softc *sc; 192 u_int8_t cmdbuf[2]; 193 int a, error; 194 195 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 196 return (ENXIO); 197 198 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 199 return (EINVAL); 200 201 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 202 return (error); 203 204 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 205 a = (int)uio->uio_offset; 206 cmdbuf[0] = a + M41ST84_USER_RAM; 207 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 208 break; 209 210 if ((error = iic_exec(sc->sc_tag, 211 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 212 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 213 aprint_error_dev(sc->sc_dev, 214 "strtc_write: write failed at 0x%x\n", a); 215 break; 216 } 217 } 218 219 iic_release_bus(sc->sc_tag, 0); 220 221 return (error); 222 } 223 224 static int 225 strtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 226 { 227 struct strtc_softc *sc = ch->cookie; 228 struct clock_ymdhms dt, check; 229 int retries; 230 231 memset(&dt, 0, sizeof(dt)); 232 memset(&check, 0, sizeof(check)); 233 234 /* 235 * Since we don't support Burst Read, we have to read the clock twice 236 * until we get two consecutive identical results. 237 */ 238 retries = 5; 239 do { 240 strtc_clock_read(sc, &dt); 241 strtc_clock_read(sc, &check); 242 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 243 244 tv->tv_sec = clock_ymdhms_to_secs(&dt); 245 tv->tv_usec = 0; 246 247 return (0); 248 } 249 250 static int 251 strtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 252 { 253 struct strtc_softc *sc = ch->cookie; 254 struct clock_ymdhms dt; 255 256 clock_secs_to_ymdhms(tv->tv_sec, &dt); 257 258 if (strtc_clock_write(sc, &dt) == 0) 259 return (-1); 260 261 return (0); 262 } 263 264 static int 265 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 266 { 267 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[1]; 268 int i; 269 270 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 271 aprint_error_dev(sc->sc_dev, 272 "strtc_clock_read: failed to acquire I2C bus\n"); 273 return (0); 274 } 275 276 /* 277 * Check for the HT bit -- if set, then clock lost power & stopped 278 * If that happened, then clear the bit so that the clock will have 279 * a chance to run again. 280 */ 281 cmdbuf[0] = M41ST84_REG_AL_HOUR; 282 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 283 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 284 iic_release_bus(sc->sc_tag, I2C_F_POLL); 285 aprint_error_dev(sc->sc_dev, 286 "strtc_clock_read: failed to read HT\n"); 287 return (0); 288 } 289 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 290 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 291 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 292 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 293 iic_release_bus(sc->sc_tag, I2C_F_POLL); 294 aprint_error_dev(sc->sc_dev, 295 "strtc_clock_read: failed to reset HT\n"); 296 return (0); 297 } 298 } 299 300 /* Read each RTC register in order. */ 301 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 302 cmdbuf[0] = i; 303 304 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 305 sc->sc_address, cmdbuf, 1, 306 &bcd[i], 1, I2C_F_POLL)) { 307 iic_release_bus(sc->sc_tag, I2C_F_POLL); 308 aprint_error_dev(sc->sc_dev, 309 "strtc_clock_read: failed to read rtc " 310 "at 0x%x\n", i); 311 return (0); 312 } 313 } 314 315 /* Done with I2C */ 316 iic_release_bus(sc->sc_tag, I2C_F_POLL); 317 318 /* 319 * Convert the M41ST84's register values into something useable 320 */ 321 dt->dt_sec = FROMBCD(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 322 dt->dt_min = FROMBCD(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 323 dt->dt_hour = FROMBCD(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 324 dt->dt_day = FROMBCD(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 325 dt->dt_mon = FROMBCD(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 326 327 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 328 dt->dt_year = FROMBCD(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 329 330 return (1); 331 } 332 333 static int 334 strtc_clock_write(struct strtc_softc *sc, struct clock_ymdhms *dt) 335 { 336 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 337 int i; 338 339 /* 340 * Convert our time representation into something the M41ST84 341 * can understand. 342 */ 343 bcd[M41ST84_REG_CSEC] = TOBCD(0); /* must always write as 0 */ 344 bcd[M41ST84_REG_SEC] = TOBCD(dt->dt_sec); 345 bcd[M41ST84_REG_MIN] = TOBCD(dt->dt_min); 346 bcd[M41ST84_REG_CENHR] = TOBCD(dt->dt_hour); 347 bcd[M41ST84_REG_DATE] = TOBCD(dt->dt_day); 348 bcd[M41ST84_REG_DAY] = TOBCD(dt->dt_wday); 349 bcd[M41ST84_REG_MONTH] = TOBCD(dt->dt_mon); 350 bcd[M41ST84_REG_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 351 352 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 353 aprint_error_dev(sc->sc_dev, 354 "strtc_clock_write: failed to acquire I2C bus\n"); 355 return (0); 356 } 357 358 /* Stop the clock */ 359 cmdbuf[0] = M41ST84_REG_SEC; 360 cmdbuf[1] = M41ST84_SEC_ST; 361 362 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 363 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 364 iic_release_bus(sc->sc_tag, I2C_F_POLL); 365 aprint_error_dev(sc->sc_dev, 366 "strtc_clock_write: failed to Hold Clock\n"); 367 return (0); 368 } 369 370 /* 371 * Check for the HT bit -- if set, then clock lost power & stopped 372 * If that happened, then clear the bit so that the clock will have 373 * a chance to run again. 374 */ 375 cmdbuf[0] = M41ST84_REG_AL_HOUR; 376 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 377 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 378 iic_release_bus(sc->sc_tag, I2C_F_POLL); 379 aprint_error_dev(sc->sc_dev, 380 "strtc_clock_write: failed to read HT\n"); 381 return (0); 382 } 383 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 384 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 385 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 386 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 387 iic_release_bus(sc->sc_tag, I2C_F_POLL); 388 aprint_error_dev(sc->sc_dev, 389 "strtc_clock_write: failed to reset HT\n"); 390 return (0); 391 } 392 } 393 394 /* 395 * Write registers in reverse order. The last write (to the Seconds 396 * register) will undo the Clock Hold, above. 397 */ 398 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 399 cmdbuf[0] = i; 400 if (iic_exec(sc->sc_tag, 401 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 402 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 403 I2C_F_POLL)) { 404 iic_release_bus(sc->sc_tag, I2C_F_POLL); 405 aprint_error_dev(sc->sc_dev, 406 "strtc_clock_write: failed to write rtc " 407 " at 0x%x\n", i); 408 /* XXX: Clock Hold is likely still asserted! */ 409 return (0); 410 } 411 } 412 413 iic_release_bus(sc->sc_tag, I2C_F_POLL); 414 415 return (1); 416 } 417
Indexes created Fri Sep 26 20:09:58 GMT 2025