m41st84.c revision 1.16
1 /* $NetBSD: m41st84.c,v 1.16 2010/10/10 05:17:44 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.16 2010/10/10 05:17:44 kiyohara Exp $"); 40 41 #include "opt_strtc.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/fcntl.h> 48 #include <sys/uio.h> 49 #include <sys/conf.h> 50 #include <sys/event.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 #include <dev/i2c/m41st84reg.h> 56 #include <dev/i2c/m41st84var.h> 57 58 struct strtc_softc { 59 device_t sc_dev; 60 i2c_tag_t sc_tag; 61 int sc_address; 62 int sc_open; 63 struct todr_chip_handle sc_todr; 64 }; 65 66 static void strtc_attach(device_t, device_t, void *); 67 static int strtc_match(device_t, cfdata_t, void *); 68 69 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 70 strtc_match, strtc_attach, NULL, NULL); 71 72 #ifndef STRTC_NO_USERRAM 73 extern struct cfdriver strtc_cd; 74 75 dev_type_open(strtc_open); 76 dev_type_close(strtc_close); 77 dev_type_read(strtc_read); 78 dev_type_write(strtc_write); 79 80 const struct cdevsw strtc_cdevsw = { 81 strtc_open, strtc_close, strtc_read, strtc_write, noioctl, 82 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 83 }; 84 #endif 85 86 static int strtc_clock_read(struct strtc_softc *, struct clock_ymdhms *); 87 static int strtc_clock_write(struct strtc_softc *, struct clock_ymdhms *); 88 static int strtc_gettime(struct todr_chip_handle *, struct timeval *); 89 static int strtc_settime(struct todr_chip_handle *, struct timeval *); 90 91 static int 92 strtc_match(device_t parent, cfdata_t cf, void *arg) 93 { 94 struct i2c_attach_args *ia = arg; 95 96 if (ia->ia_addr == M41ST84_ADDR) 97 return (1); 98 99 return (0); 100 } 101 102 static void 103 strtc_attach(device_t parent, device_t self, void *arg) 104 { 105 struct strtc_softc *sc = device_private(self); 106 struct i2c_attach_args *ia = arg; 107 108 aprint_naive(": Real-time Clock/NVRAM\n"); 109 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 110 111 sc->sc_tag = ia->ia_tag; 112 sc->sc_address = ia->ia_addr; 113 sc->sc_dev = self; 114 sc->sc_open = 0; 115 sc->sc_todr.cookie = sc; 116 sc->sc_todr.todr_gettime = strtc_gettime; 117 sc->sc_todr.todr_settime = strtc_settime; 118 sc->sc_todr.todr_setwen = NULL; 119 120 todr_attach(&sc->sc_todr); 121 } 122 123 #ifndef STRTC_NO_USERRAM 124 /*ARGSUSED*/ 125 int 126 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 127 { 128 struct strtc_softc *sc; 129 130 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 131 return (ENXIO); 132 133 /* XXX: Locking */ 134 135 if (sc->sc_open) 136 return (EBUSY); 137 138 sc->sc_open = 1; 139 return (0); 140 } 141 142 /*ARGSUSED*/ 143 int 144 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 145 { 146 struct strtc_softc *sc; 147 148 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 149 return (ENXIO); 150 151 sc->sc_open = 0; 152 return (0); 153 } 154 155 /*ARGSUSED*/ 156 int 157 strtc_read(dev_t dev, struct uio *uio, int flags) 158 { 159 struct strtc_softc *sc; 160 u_int8_t ch, cmdbuf[1]; 161 int a, error; 162 163 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 164 return (ENXIO); 165 166 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 167 return (EINVAL); 168 169 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 170 return (error); 171 172 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 173 a = (int)uio->uio_offset; 174 cmdbuf[0] = a + M41ST84_USER_RAM; 175 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 176 sc->sc_address, cmdbuf, 1, 177 &ch, 1, 0)) != 0) { 178 iic_release_bus(sc->sc_tag, 0); 179 aprint_error_dev(sc->sc_dev, 180 "strtc_read: read failed at 0x%x\n", a); 181 return (error); 182 } 183 if ((error = uiomove(&ch, 1, uio)) != 0) { 184 iic_release_bus(sc->sc_tag, 0); 185 return (error); 186 } 187 } 188 189 iic_release_bus(sc->sc_tag, 0); 190 191 return (0); 192 } 193 194 /*ARGSUSED*/ 195 int 196 strtc_write(dev_t dev, struct uio *uio, int flags) 197 { 198 struct strtc_softc *sc; 199 u_int8_t cmdbuf[2]; 200 int a, error; 201 202 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 203 return (ENXIO); 204 205 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 206 return (EINVAL); 207 208 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 209 return (error); 210 211 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 212 a = (int)uio->uio_offset; 213 cmdbuf[0] = a + M41ST84_USER_RAM; 214 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 215 break; 216 217 if ((error = iic_exec(sc->sc_tag, 218 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 219 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 220 aprint_error_dev(sc->sc_dev, 221 "strtc_write: write failed at 0x%x\n", a); 222 break; 223 } 224 } 225 226 iic_release_bus(sc->sc_tag, 0); 227 228 return (error); 229 } 230 #endif /* STRTC_NO_USERRAM */ 231 232 static int 233 strtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 234 { 235 struct strtc_softc *sc = ch->cookie; 236 struct clock_ymdhms dt, check; 237 int retries; 238 239 memset(&dt, 0, sizeof(dt)); 240 memset(&check, 0, sizeof(check)); 241 242 /* 243 * Since we don't support Burst Read, we have to read the clock twice 244 * until we get two consecutive identical results. 245 */ 246 retries = 5; 247 do { 248 strtc_clock_read(sc, &dt); 249 strtc_clock_read(sc, &check); 250 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 251 252 tv->tv_sec = clock_ymdhms_to_secs(&dt); 253 tv->tv_usec = 0; 254 255 return (0); 256 } 257 258 static int 259 strtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 260 { 261 struct strtc_softc *sc = ch->cookie; 262 struct clock_ymdhms dt; 263 264 clock_secs_to_ymdhms(tv->tv_sec, &dt); 265 266 if (strtc_clock_write(sc, &dt) == 0) 267 return (-1); 268 269 return (0); 270 } 271 272 static int 273 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 274 { 275 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[1]; 276 int i; 277 278 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 279 aprint_error_dev(sc->sc_dev, 280 "strtc_clock_read: failed to acquire I2C bus\n"); 281 return (0); 282 } 283 284 /* 285 * Check for the HT bit -- if set, then clock lost power & stopped 286 * If that happened, then clear the bit so that the clock will have 287 * a chance to run again. 288 */ 289 cmdbuf[0] = M41ST84_REG_AL_HOUR; 290 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 291 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 292 iic_release_bus(sc->sc_tag, I2C_F_POLL); 293 aprint_error_dev(sc->sc_dev, 294 "strtc_clock_read: failed to read HT\n"); 295 return (0); 296 } 297 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 298 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 299 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 300 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 301 iic_release_bus(sc->sc_tag, I2C_F_POLL); 302 aprint_error_dev(sc->sc_dev, 303 "strtc_clock_read: failed to reset HT\n"); 304 return (0); 305 } 306 } 307 308 /* Read each RTC register in order. */ 309 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 310 cmdbuf[0] = i; 311 312 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 313 sc->sc_address, cmdbuf, 1, 314 &bcd[i], 1, I2C_F_POLL)) { 315 iic_release_bus(sc->sc_tag, I2C_F_POLL); 316 aprint_error_dev(sc->sc_dev, 317 "strtc_clock_read: failed to read rtc " 318 "at 0x%x\n", i); 319 return (0); 320 } 321 } 322 323 /* Done with I2C */ 324 iic_release_bus(sc->sc_tag, I2C_F_POLL); 325 326 /* 327 * Convert the M41ST84's register values into something useable 328 */ 329 dt->dt_sec = FROMBCD(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 330 dt->dt_min = FROMBCD(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 331 dt->dt_hour = FROMBCD(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 332 dt->dt_day = FROMBCD(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 333 dt->dt_mon = FROMBCD(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 334 335 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 336 dt->dt_year = FROMBCD(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 337 338 return (1); 339 } 340 341 static int 342 strtc_clock_write(struct strtc_softc *sc, struct clock_ymdhms *dt) 343 { 344 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 345 int i; 346 347 /* 348 * Convert our time representation into something the M41ST84 349 * can understand. 350 */ 351 bcd[M41ST84_REG_CSEC] = TOBCD(0); /* must always write as 0 */ 352 bcd[M41ST84_REG_SEC] = TOBCD(dt->dt_sec); 353 bcd[M41ST84_REG_MIN] = TOBCD(dt->dt_min); 354 bcd[M41ST84_REG_CENHR] = TOBCD(dt->dt_hour); 355 bcd[M41ST84_REG_DATE] = TOBCD(dt->dt_day); 356 bcd[M41ST84_REG_DAY] = TOBCD(dt->dt_wday); 357 bcd[M41ST84_REG_MONTH] = TOBCD(dt->dt_mon); 358 bcd[M41ST84_REG_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 359 360 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 361 aprint_error_dev(sc->sc_dev, 362 "strtc_clock_write: failed to acquire I2C bus\n"); 363 return (0); 364 } 365 366 /* Stop the clock */ 367 cmdbuf[0] = M41ST84_REG_SEC; 368 cmdbuf[1] = M41ST84_SEC_ST; 369 370 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 371 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 372 iic_release_bus(sc->sc_tag, I2C_F_POLL); 373 aprint_error_dev(sc->sc_dev, 374 "strtc_clock_write: failed to Hold Clock\n"); 375 return (0); 376 } 377 378 /* 379 * Check for the HT bit -- if set, then clock lost power & stopped 380 * If that happened, then clear the bit so that the clock will have 381 * a chance to run again. 382 */ 383 cmdbuf[0] = M41ST84_REG_AL_HOUR; 384 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 385 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 386 iic_release_bus(sc->sc_tag, I2C_F_POLL); 387 aprint_error_dev(sc->sc_dev, 388 "strtc_clock_write: failed to read HT\n"); 389 return (0); 390 } 391 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 392 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 393 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 394 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 395 iic_release_bus(sc->sc_tag, I2C_F_POLL); 396 aprint_error_dev(sc->sc_dev, 397 "strtc_clock_write: failed to reset HT\n"); 398 return (0); 399 } 400 } 401 402 /* 403 * Write registers in reverse order. The last write (to the Seconds 404 * register) will undo the Clock Hold, above. 405 */ 406 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 407 cmdbuf[0] = i; 408 if (iic_exec(sc->sc_tag, 409 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 410 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 411 I2C_F_POLL)) { 412 iic_release_bus(sc->sc_tag, I2C_F_POLL); 413 aprint_error_dev(sc->sc_dev, 414 "strtc_clock_write: failed to write rtc " 415 " at 0x%x\n", i); 416 /* XXX: Clock Hold is likely still asserted! */ 417 return (0); 418 } 419 } 420 421 iic_release_bus(sc->sc_tag, I2C_F_POLL); 422 423 return (1); 424 } 425 426 #ifndef STRTC_NO_WATCHDOG 427 void 428 strtc_wdog_config(void *arg, uint8_t wd) 429 { 430 struct strtc_softc *sc = arg; 431 uint8_t cmdbuf[2]; 432 433 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 434 aprint_error_dev(sc->sc_dev, 435 "strtc_wdog_config: failed to acquire I2C bus\n"); 436 return; 437 } 438 439 cmdbuf[0] = M41ST84_REG_WATCHDOG; 440 cmdbuf[1] = wd; 441 442 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 443 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 444 aprint_error_dev(sc->sc_dev, 445 "strtc_wdog_config: failed to write watchdog\n"); 446 return; 447 } 448 449 iic_release_bus(sc->sc_tag, I2C_F_POLL); 450 } 451 #endif /* STRTC_NO_WATCHDOG */ 452
Indexes created Wed Sep 24 05:09:52 GMT 2025