m41st84.c revision 1.17
1 /* $NetBSD: m41st84.c,v 1.17 2011/04/17 14:58:26 phx Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.17 2011/04/17 14:58:26 phx Exp $"); 40 41 #include "opt_strtc.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/fcntl.h> 48 #include <sys/uio.h> 49 #include <sys/conf.h> 50 #include <sys/event.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 #include <dev/i2c/m41st84reg.h> 56 #include <dev/i2c/m41st84var.h> 57 58 struct strtc_softc { 59 device_t sc_dev; 60 i2c_tag_t sc_tag; 61 int sc_address; 62 int sc_open; 63 struct todr_chip_handle sc_todr; 64 }; 65 66 static void strtc_attach(device_t, device_t, void *); 67 static int strtc_match(device_t, cfdata_t, void *); 68 69 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 70 strtc_match, strtc_attach, NULL, NULL); 71 72 #ifndef STRTC_NO_USERRAM 73 extern struct cfdriver strtc_cd; 74 75 dev_type_open(strtc_open); 76 dev_type_close(strtc_close); 77 dev_type_read(strtc_read); 78 dev_type_write(strtc_write); 79 80 const struct cdevsw strtc_cdevsw = { 81 strtc_open, strtc_close, strtc_read, strtc_write, noioctl, 82 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 83 }; 84 #endif 85 86 static int strtc_clock_read(struct strtc_softc *, struct clock_ymdhms *); 87 static int strtc_clock_write(struct strtc_softc *, struct clock_ymdhms *); 88 static int strtc_gettime(struct todr_chip_handle *, struct timeval *); 89 static int strtc_settime(struct todr_chip_handle *, struct timeval *); 90 91 static int 92 strtc_match(device_t parent, cfdata_t cf, void *arg) 93 { 94 struct i2c_attach_args *ia = arg; 95 96 if (ia->ia_addr == M41ST84_ADDR) 97 return (1); 98 99 return (0); 100 } 101 102 static void 103 strtc_attach(device_t parent, device_t self, void *arg) 104 { 105 struct strtc_softc *sc = device_private(self); 106 struct i2c_attach_args *ia = arg; 107 108 #ifndef STRTC_NO_USERRAM 109 aprint_naive(": Real-time Clock/NVRAM\n"); 110 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 111 #else 112 aprint_naive(": Real-time Clock\n"); 113 aprint_normal(": M41T8x Real-time Clock\n"); 114 #endif 115 sc->sc_tag = ia->ia_tag; 116 sc->sc_address = ia->ia_addr; 117 sc->sc_dev = self; 118 sc->sc_open = 0; 119 sc->sc_todr.cookie = sc; 120 sc->sc_todr.todr_gettime = strtc_gettime; 121 sc->sc_todr.todr_settime = strtc_settime; 122 sc->sc_todr.todr_setwen = NULL; 123 124 todr_attach(&sc->sc_todr); 125 } 126 127 #ifndef STRTC_NO_USERRAM 128 /*ARGSUSED*/ 129 int 130 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 131 { 132 struct strtc_softc *sc; 133 134 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 135 return (ENXIO); 136 137 /* XXX: Locking */ 138 139 if (sc->sc_open) 140 return (EBUSY); 141 142 sc->sc_open = 1; 143 return (0); 144 } 145 146 /*ARGSUSED*/ 147 int 148 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 149 { 150 struct strtc_softc *sc; 151 152 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 153 return (ENXIO); 154 155 sc->sc_open = 0; 156 return (0); 157 } 158 159 /*ARGSUSED*/ 160 int 161 strtc_read(dev_t dev, struct uio *uio, int flags) 162 { 163 struct strtc_softc *sc; 164 u_int8_t ch, cmdbuf[1]; 165 int a, error; 166 167 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 168 return (ENXIO); 169 170 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 171 return (EINVAL); 172 173 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 174 return (error); 175 176 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 177 a = (int)uio->uio_offset; 178 cmdbuf[0] = a + M41ST84_USER_RAM; 179 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 180 sc->sc_address, cmdbuf, 1, 181 &ch, 1, 0)) != 0) { 182 iic_release_bus(sc->sc_tag, 0); 183 aprint_error_dev(sc->sc_dev, 184 "strtc_read: read failed at 0x%x\n", a); 185 return (error); 186 } 187 if ((error = uiomove(&ch, 1, uio)) != 0) { 188 iic_release_bus(sc->sc_tag, 0); 189 return (error); 190 } 191 } 192 193 iic_release_bus(sc->sc_tag, 0); 194 195 return (0); 196 } 197 198 /*ARGSUSED*/ 199 int 200 strtc_write(dev_t dev, struct uio *uio, int flags) 201 { 202 struct strtc_softc *sc; 203 u_int8_t cmdbuf[2]; 204 int a, error; 205 206 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 207 return (ENXIO); 208 209 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 210 return (EINVAL); 211 212 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 213 return (error); 214 215 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 216 a = (int)uio->uio_offset; 217 cmdbuf[0] = a + M41ST84_USER_RAM; 218 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 219 break; 220 221 if ((error = iic_exec(sc->sc_tag, 222 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 223 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 224 aprint_error_dev(sc->sc_dev, 225 "strtc_write: write failed at 0x%x\n", a); 226 break; 227 } 228 } 229 230 iic_release_bus(sc->sc_tag, 0); 231 232 return (error); 233 } 234 #endif /* STRTC_NO_USERRAM */ 235 236 static int 237 strtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 238 { 239 struct strtc_softc *sc = ch->cookie; 240 struct clock_ymdhms dt, check; 241 int retries; 242 243 memset(&dt, 0, sizeof(dt)); 244 memset(&check, 0, sizeof(check)); 245 246 /* 247 * Since we don't support Burst Read, we have to read the clock twice 248 * until we get two consecutive identical results. 249 */ 250 retries = 5; 251 do { 252 strtc_clock_read(sc, &dt); 253 strtc_clock_read(sc, &check); 254 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 255 256 tv->tv_sec = clock_ymdhms_to_secs(&dt); 257 tv->tv_usec = 0; 258 259 return (0); 260 } 261 262 static int 263 strtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 264 { 265 struct strtc_softc *sc = ch->cookie; 266 struct clock_ymdhms dt; 267 268 clock_secs_to_ymdhms(tv->tv_sec, &dt); 269 270 if (strtc_clock_write(sc, &dt) == 0) 271 return (-1); 272 273 return (0); 274 } 275 276 static int 277 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 278 { 279 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[1]; 280 int i; 281 282 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 283 aprint_error_dev(sc->sc_dev, 284 "strtc_clock_read: failed to acquire I2C bus\n"); 285 return (0); 286 } 287 288 /* 289 * Check for the HT bit -- if set, then clock lost power & stopped 290 * If that happened, then clear the bit so that the clock will have 291 * a chance to run again. 292 */ 293 cmdbuf[0] = M41ST84_REG_AL_HOUR; 294 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 295 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 296 iic_release_bus(sc->sc_tag, I2C_F_POLL); 297 aprint_error_dev(sc->sc_dev, 298 "strtc_clock_read: failed to read HT\n"); 299 return (0); 300 } 301 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 302 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 303 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 304 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 305 iic_release_bus(sc->sc_tag, I2C_F_POLL); 306 aprint_error_dev(sc->sc_dev, 307 "strtc_clock_read: failed to reset HT\n"); 308 return (0); 309 } 310 } 311 312 /* Read each RTC register in order. */ 313 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 314 cmdbuf[0] = i; 315 316 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 317 sc->sc_address, cmdbuf, 1, 318 &bcd[i], 1, I2C_F_POLL)) { 319 iic_release_bus(sc->sc_tag, I2C_F_POLL); 320 aprint_error_dev(sc->sc_dev, 321 "strtc_clock_read: failed to read rtc " 322 "at 0x%x\n", i); 323 return (0); 324 } 325 } 326 327 /* Done with I2C */ 328 iic_release_bus(sc->sc_tag, I2C_F_POLL); 329 330 /* 331 * Convert the M41ST84's register values into something useable 332 */ 333 dt->dt_sec = FROMBCD(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 334 dt->dt_min = FROMBCD(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 335 dt->dt_hour = FROMBCD(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 336 dt->dt_day = FROMBCD(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 337 dt->dt_mon = FROMBCD(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 338 339 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 340 dt->dt_year = FROMBCD(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 341 342 return (1); 343 } 344 345 static int 346 strtc_clock_write(struct strtc_softc *sc, struct clock_ymdhms *dt) 347 { 348 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 349 int i; 350 351 /* 352 * Convert our time representation into something the M41ST84 353 * can understand. 354 */ 355 bcd[M41ST84_REG_CSEC] = TOBCD(0); /* must always write as 0 */ 356 bcd[M41ST84_REG_SEC] = TOBCD(dt->dt_sec); 357 bcd[M41ST84_REG_MIN] = TOBCD(dt->dt_min); 358 bcd[M41ST84_REG_CENHR] = TOBCD(dt->dt_hour); 359 bcd[M41ST84_REG_DATE] = TOBCD(dt->dt_day); 360 bcd[M41ST84_REG_DAY] = TOBCD(dt->dt_wday); 361 bcd[M41ST84_REG_MONTH] = TOBCD(dt->dt_mon); 362 bcd[M41ST84_REG_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 363 364 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 365 aprint_error_dev(sc->sc_dev, 366 "strtc_clock_write: failed to acquire I2C bus\n"); 367 return (0); 368 } 369 370 /* Stop the clock */ 371 cmdbuf[0] = M41ST84_REG_SEC; 372 cmdbuf[1] = M41ST84_SEC_ST; 373 374 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 375 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 376 iic_release_bus(sc->sc_tag, I2C_F_POLL); 377 aprint_error_dev(sc->sc_dev, 378 "strtc_clock_write: failed to Hold Clock\n"); 379 return (0); 380 } 381 382 /* 383 * Check for the HT bit -- if set, then clock lost power & stopped 384 * If that happened, then clear the bit so that the clock will have 385 * a chance to run again. 386 */ 387 cmdbuf[0] = M41ST84_REG_AL_HOUR; 388 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 389 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 390 iic_release_bus(sc->sc_tag, I2C_F_POLL); 391 aprint_error_dev(sc->sc_dev, 392 "strtc_clock_write: failed to read HT\n"); 393 return (0); 394 } 395 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 396 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 397 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 398 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 399 iic_release_bus(sc->sc_tag, I2C_F_POLL); 400 aprint_error_dev(sc->sc_dev, 401 "strtc_clock_write: failed to reset HT\n"); 402 return (0); 403 } 404 } 405 406 /* 407 * Write registers in reverse order. The last write (to the Seconds 408 * register) will undo the Clock Hold, above. 409 */ 410 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 411 cmdbuf[0] = i; 412 if (iic_exec(sc->sc_tag, 413 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 414 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 415 I2C_F_POLL)) { 416 iic_release_bus(sc->sc_tag, I2C_F_POLL); 417 aprint_error_dev(sc->sc_dev, 418 "strtc_clock_write: failed to write rtc " 419 " at 0x%x\n", i); 420 /* XXX: Clock Hold is likely still asserted! */ 421 return (0); 422 } 423 } 424 425 iic_release_bus(sc->sc_tag, I2C_F_POLL); 426 427 return (1); 428 } 429 430 #ifndef STRTC_NO_WATCHDOG 431 void 432 strtc_wdog_config(void *arg, uint8_t wd) 433 { 434 struct strtc_softc *sc = arg; 435 uint8_t cmdbuf[2]; 436 437 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 438 aprint_error_dev(sc->sc_dev, 439 "strtc_wdog_config: failed to acquire I2C bus\n"); 440 return; 441 } 442 443 cmdbuf[0] = M41ST84_REG_WATCHDOG; 444 cmdbuf[1] = wd; 445 446 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 447 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 448 aprint_error_dev(sc->sc_dev, 449 "strtc_wdog_config: failed to write watchdog\n"); 450 return; 451 } 452 453 iic_release_bus(sc->sc_tag, I2C_F_POLL); 454 } 455 #endif /* STRTC_NO_WATCHDOG */ 456
Indexes created Fri Sep 26 20:09:58 GMT 2025