m41st84.c revision 1.20
1 /* $NetBSD: m41st84.c,v 1.20 2014/03/16 05:20:27 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.20 2014/03/16 05:20:27 dholland Exp $"); 40 41 #include "opt_strtc.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/fcntl.h> 48 #include <sys/uio.h> 49 #include <sys/conf.h> 50 #include <sys/event.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 #include <dev/i2c/m41st84reg.h> 56 #include <dev/i2c/m41st84var.h> 57 58 struct strtc_softc { 59 device_t sc_dev; 60 i2c_tag_t sc_tag; 61 int sc_address; 62 int sc_open; 63 struct todr_chip_handle sc_todr; 64 }; 65 66 static void strtc_attach(device_t, device_t, void *); 67 static int strtc_match(device_t, cfdata_t, void *); 68 69 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 70 strtc_match, strtc_attach, NULL, NULL); 71 72 #ifndef STRTC_NO_USERRAM 73 extern struct cfdriver strtc_cd; 74 75 dev_type_open(strtc_open); 76 dev_type_close(strtc_close); 77 dev_type_read(strtc_read); 78 dev_type_write(strtc_write); 79 80 const struct cdevsw strtc_cdevsw = { 81 .d_open = strtc_open, 82 .d_close = strtc_close, 83 .d_read = strtc_read, 84 .d_write = strtc_write, 85 .d_ioctl = noioctl, 86 .d_stop = nostop, 87 .d_tty = notty, 88 .d_poll = nopoll, 89 .d_mmap = nommap, 90 .d_kqfilter = nokqfilter, 91 .d_flag = D_OTHER 92 }; 93 #endif 94 95 static int strtc_clock_read(struct strtc_softc *, struct clock_ymdhms *); 96 static int strtc_clock_write(struct strtc_softc *, struct clock_ymdhms *); 97 static int strtc_gettime(struct todr_chip_handle *, struct timeval *); 98 static int strtc_settime(struct todr_chip_handle *, struct timeval *); 99 100 static int 101 strtc_match(device_t parent, cfdata_t cf, void *arg) 102 { 103 struct i2c_attach_args *ia = arg; 104 105 if (ia->ia_name) { 106 /* direct config - check name */ 107 if (strcmp(ia->ia_name, "strtc") == 0) 108 return 1; 109 } else { 110 /* indirect config - check typical address */ 111 if (ia->ia_addr == M41ST84_ADDR) 112 return 1; 113 } 114 return 0; 115 } 116 117 static void 118 strtc_attach(device_t parent, device_t self, void *arg) 119 { 120 struct strtc_softc *sc = device_private(self); 121 struct i2c_attach_args *ia = arg; 122 123 #ifndef STRTC_NO_USERRAM 124 aprint_naive(": Real-time Clock/NVRAM\n"); 125 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 126 #else 127 aprint_naive(": Real-time Clock\n"); 128 aprint_normal(": M41T8x Real-time Clock\n"); 129 #endif 130 sc->sc_tag = ia->ia_tag; 131 sc->sc_address = ia->ia_addr; 132 sc->sc_dev = self; 133 sc->sc_open = 0; 134 sc->sc_todr.cookie = sc; 135 sc->sc_todr.todr_gettime = strtc_gettime; 136 sc->sc_todr.todr_settime = strtc_settime; 137 sc->sc_todr.todr_setwen = NULL; 138 139 todr_attach(&sc->sc_todr); 140 } 141 142 #ifndef STRTC_NO_USERRAM 143 /*ARGSUSED*/ 144 int 145 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 146 { 147 struct strtc_softc *sc; 148 149 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 150 return (ENXIO); 151 152 /* XXX: Locking */ 153 154 if (sc->sc_open) 155 return (EBUSY); 156 157 sc->sc_open = 1; 158 return (0); 159 } 160 161 /*ARGSUSED*/ 162 int 163 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 164 { 165 struct strtc_softc *sc; 166 167 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 168 return (ENXIO); 169 170 sc->sc_open = 0; 171 return (0); 172 } 173 174 /*ARGSUSED*/ 175 int 176 strtc_read(dev_t dev, struct uio *uio, int flags) 177 { 178 struct strtc_softc *sc; 179 u_int8_t ch, cmdbuf[1]; 180 int a, error; 181 182 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 183 return (ENXIO); 184 185 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 186 return (EINVAL); 187 188 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 189 return (error); 190 191 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 192 a = (int)uio->uio_offset; 193 cmdbuf[0] = a + M41ST84_USER_RAM; 194 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 195 sc->sc_address, cmdbuf, 1, 196 &ch, 1, 0)) != 0) { 197 iic_release_bus(sc->sc_tag, 0); 198 aprint_error_dev(sc->sc_dev, 199 "strtc_read: read failed at 0x%x\n", a); 200 return (error); 201 } 202 if ((error = uiomove(&ch, 1, uio)) != 0) { 203 iic_release_bus(sc->sc_tag, 0); 204 return (error); 205 } 206 } 207 208 iic_release_bus(sc->sc_tag, 0); 209 210 return (0); 211 } 212 213 /*ARGSUSED*/ 214 int 215 strtc_write(dev_t dev, struct uio *uio, int flags) 216 { 217 struct strtc_softc *sc; 218 u_int8_t cmdbuf[2]; 219 int a, error; 220 221 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 222 return (ENXIO); 223 224 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 225 return (EINVAL); 226 227 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 228 return (error); 229 230 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 231 a = (int)uio->uio_offset; 232 cmdbuf[0] = a + M41ST84_USER_RAM; 233 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 234 break; 235 236 if ((error = iic_exec(sc->sc_tag, 237 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 238 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 239 aprint_error_dev(sc->sc_dev, 240 "strtc_write: write failed at 0x%x\n", a); 241 break; 242 } 243 } 244 245 iic_release_bus(sc->sc_tag, 0); 246 247 return (error); 248 } 249 #endif /* STRTC_NO_USERRAM */ 250 251 static int 252 strtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 253 { 254 struct strtc_softc *sc = ch->cookie; 255 struct clock_ymdhms dt, check; 256 int retries; 257 258 memset(&dt, 0, sizeof(dt)); 259 memset(&check, 0, sizeof(check)); 260 261 /* 262 * Since we don't support Burst Read, we have to read the clock twice 263 * until we get two consecutive identical results. 264 */ 265 retries = 5; 266 do { 267 strtc_clock_read(sc, &dt); 268 strtc_clock_read(sc, &check); 269 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 270 271 tv->tv_sec = clock_ymdhms_to_secs(&dt); 272 tv->tv_usec = 0; 273 274 return (0); 275 } 276 277 static int 278 strtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 279 { 280 struct strtc_softc *sc = ch->cookie; 281 struct clock_ymdhms dt; 282 283 clock_secs_to_ymdhms(tv->tv_sec, &dt); 284 285 if (strtc_clock_write(sc, &dt) == 0) 286 return (-1); 287 288 return (0); 289 } 290 291 static int 292 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 293 { 294 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 295 int i; 296 297 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 298 aprint_error_dev(sc->sc_dev, 299 "strtc_clock_read: failed to acquire I2C bus\n"); 300 return (0); 301 } 302 303 /* 304 * Check for the HT bit -- if set, then clock lost power & stopped 305 * If that happened, then clear the bit so that the clock will have 306 * a chance to run again. 307 */ 308 cmdbuf[0] = M41ST84_REG_AL_HOUR; 309 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 310 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 311 iic_release_bus(sc->sc_tag, I2C_F_POLL); 312 aprint_error_dev(sc->sc_dev, 313 "strtc_clock_read: failed to read HT\n"); 314 return (0); 315 } 316 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 317 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 318 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 319 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 320 iic_release_bus(sc->sc_tag, I2C_F_POLL); 321 aprint_error_dev(sc->sc_dev, 322 "strtc_clock_read: failed to reset HT\n"); 323 return (0); 324 } 325 } 326 327 /* Read each RTC register in order. */ 328 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 329 cmdbuf[0] = i; 330 331 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 332 sc->sc_address, cmdbuf, 1, 333 &bcd[i], 1, I2C_F_POLL)) { 334 iic_release_bus(sc->sc_tag, I2C_F_POLL); 335 aprint_error_dev(sc->sc_dev, 336 "strtc_clock_read: failed to read rtc " 337 "at 0x%x\n", i); 338 return (0); 339 } 340 } 341 342 /* Done with I2C */ 343 iic_release_bus(sc->sc_tag, I2C_F_POLL); 344 345 /* 346 * Convert the M41ST84's register values into something useable 347 */ 348 dt->dt_sec = FROMBCD(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 349 dt->dt_min = FROMBCD(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 350 dt->dt_hour = FROMBCD(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 351 dt->dt_day = FROMBCD(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 352 dt->dt_mon = FROMBCD(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 353 354 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 355 dt->dt_year = FROMBCD(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 356 357 return (1); 358 } 359 360 static int 361 strtc_clock_write(struct strtc_softc *sc, struct clock_ymdhms *dt) 362 { 363 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 364 int i; 365 366 /* 367 * Convert our time representation into something the M41ST84 368 * can understand. 369 */ 370 bcd[M41ST84_REG_CSEC] = TOBCD(0); /* must always write as 0 */ 371 bcd[M41ST84_REG_SEC] = TOBCD(dt->dt_sec); 372 bcd[M41ST84_REG_MIN] = TOBCD(dt->dt_min); 373 bcd[M41ST84_REG_CENHR] = TOBCD(dt->dt_hour); 374 bcd[M41ST84_REG_DATE] = TOBCD(dt->dt_day); 375 bcd[M41ST84_REG_DAY] = TOBCD(dt->dt_wday); 376 bcd[M41ST84_REG_MONTH] = TOBCD(dt->dt_mon); 377 bcd[M41ST84_REG_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 378 379 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 380 aprint_error_dev(sc->sc_dev, 381 "strtc_clock_write: failed to acquire I2C bus\n"); 382 return (0); 383 } 384 385 /* Stop the clock */ 386 cmdbuf[0] = M41ST84_REG_SEC; 387 cmdbuf[1] = M41ST84_SEC_ST; 388 389 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 390 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 391 iic_release_bus(sc->sc_tag, I2C_F_POLL); 392 aprint_error_dev(sc->sc_dev, 393 "strtc_clock_write: failed to Hold Clock\n"); 394 return (0); 395 } 396 397 /* 398 * Check for the HT bit -- if set, then clock lost power & stopped 399 * If that happened, then clear the bit so that the clock will have 400 * a chance to run again. 401 */ 402 cmdbuf[0] = M41ST84_REG_AL_HOUR; 403 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 404 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 405 iic_release_bus(sc->sc_tag, I2C_F_POLL); 406 aprint_error_dev(sc->sc_dev, 407 "strtc_clock_write: failed to read HT\n"); 408 return (0); 409 } 410 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 411 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 412 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 413 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 414 iic_release_bus(sc->sc_tag, I2C_F_POLL); 415 aprint_error_dev(sc->sc_dev, 416 "strtc_clock_write: failed to reset HT\n"); 417 return (0); 418 } 419 } 420 421 /* 422 * Write registers in reverse order. The last write (to the Seconds 423 * register) will undo the Clock Hold, above. 424 */ 425 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 426 cmdbuf[0] = i; 427 if (iic_exec(sc->sc_tag, 428 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 429 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 430 I2C_F_POLL)) { 431 iic_release_bus(sc->sc_tag, I2C_F_POLL); 432 aprint_error_dev(sc->sc_dev, 433 "strtc_clock_write: failed to write rtc " 434 " at 0x%x\n", i); 435 /* XXX: Clock Hold is likely still asserted! */ 436 return (0); 437 } 438 } 439 440 iic_release_bus(sc->sc_tag, I2C_F_POLL); 441 442 return (1); 443 } 444 445 #ifndef STRTC_NO_WATCHDOG 446 void 447 strtc_wdog_config(void *arg, uint8_t wd) 448 { 449 struct strtc_softc *sc = arg; 450 uint8_t cmdbuf[2]; 451 452 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 453 aprint_error_dev(sc->sc_dev, 454 "strtc_wdog_config: failed to acquire I2C bus\n"); 455 return; 456 } 457 458 cmdbuf[0] = M41ST84_REG_WATCHDOG; 459 cmdbuf[1] = wd; 460 461 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 462 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 463 aprint_error_dev(sc->sc_dev, 464 "strtc_wdog_config: failed to write watchdog\n"); 465 return; 466 } 467 468 iic_release_bus(sc->sc_tag, I2C_F_POLL); 469 } 470 #endif /* STRTC_NO_WATCHDOG */ 471
Indexes created Thu Sep 25 06:09:39 GMT 2025