m41st84.c revision 1.26
1 /* $NetBSD: m41st84.c,v 1.26 2020/01/02 19:24:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.26 2020/01/02 19:24:48 thorpej Exp $"); 40 41 #include "opt_strtc.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/kernel.h> 47 #include <sys/fcntl.h> 48 #include <sys/uio.h> 49 #include <sys/conf.h> 50 #include <sys/event.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <dev/i2c/i2cvar.h> 55 #include <dev/i2c/m41st84reg.h> 56 #include <dev/i2c/m41st84var.h> 57 58 #include "ioconf.h" 59 60 struct strtc_softc { 61 device_t sc_dev; 62 i2c_tag_t sc_tag; 63 int sc_address; 64 int sc_open; 65 struct todr_chip_handle sc_todr; 66 }; 67 68 static void strtc_attach(device_t, device_t, void *); 69 static int strtc_match(device_t, cfdata_t, void *); 70 71 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 72 strtc_match, strtc_attach, NULL, NULL); 73 74 #ifndef STRTC_NO_USERRAM 75 dev_type_open(strtc_open); 76 dev_type_close(strtc_close); 77 dev_type_read(strtc_read); 78 dev_type_write(strtc_write); 79 80 const struct cdevsw strtc_cdevsw = { 81 .d_open = strtc_open, 82 .d_close = strtc_close, 83 .d_read = strtc_read, 84 .d_write = strtc_write, 85 .d_ioctl = noioctl, 86 .d_stop = nostop, 87 .d_tty = notty, 88 .d_poll = nopoll, 89 .d_mmap = nommap, 90 .d_kqfilter = nokqfilter, 91 .d_discard = nodiscard, 92 .d_flag = D_OTHER 93 }; 94 #endif 95 96 static int strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *); 97 static int strtc_gettime_ymdhms(struct todr_chip_handle *, 98 struct clock_ymdhms *); 99 static int strtc_settime_ymdhms(struct todr_chip_handle *, 100 struct clock_ymdhms *); 101 102 static int 103 strtc_match(device_t parent, cfdata_t cf, void *arg) 104 { 105 struct i2c_attach_args *ia = arg; 106 int match_result; 107 108 if (iic_use_direct_match(ia, cf, NULL, &match_result)) 109 return match_result; 110 111 /* indirect config - check typical address */ 112 if (ia->ia_addr == M41ST84_ADDR) 113 return I2C_MATCH_ADDRESS_ONLY; 114 115 return 0; 116 } 117 118 static void 119 strtc_attach(device_t parent, device_t self, void *arg) 120 { 121 struct strtc_softc *sc = device_private(self); 122 struct i2c_attach_args *ia = arg; 123 124 #ifndef STRTC_NO_USERRAM 125 aprint_naive(": Real-time Clock/NVRAM\n"); 126 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 127 #else 128 aprint_naive(": Real-time Clock\n"); 129 aprint_normal(": M41T8x Real-time Clock\n"); 130 #endif 131 sc->sc_tag = ia->ia_tag; 132 sc->sc_address = ia->ia_addr; 133 sc->sc_dev = self; 134 sc->sc_open = 0; 135 sc->sc_todr.cookie = sc; 136 sc->sc_todr.todr_gettime = NULL; 137 sc->sc_todr.todr_settime = NULL; 138 sc->sc_todr.todr_gettime_ymdhms = strtc_gettime_ymdhms; 139 sc->sc_todr.todr_settime_ymdhms = strtc_settime_ymdhms; 140 sc->sc_todr.todr_setwen = NULL; 141 142 todr_attach(&sc->sc_todr); 143 } 144 145 #ifndef STRTC_NO_USERRAM 146 /*ARGSUSED*/ 147 int 148 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 149 { 150 struct strtc_softc *sc; 151 152 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 153 return (ENXIO); 154 155 /* XXX: Locking */ 156 157 if (sc->sc_open) 158 return (EBUSY); 159 160 sc->sc_open = 1; 161 return (0); 162 } 163 164 /*ARGSUSED*/ 165 int 166 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 167 { 168 struct strtc_softc *sc; 169 170 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 171 return (ENXIO); 172 173 sc->sc_open = 0; 174 return (0); 175 } 176 177 /*ARGSUSED*/ 178 int 179 strtc_read(dev_t dev, struct uio *uio, int flags) 180 { 181 struct strtc_softc *sc; 182 u_int8_t ch, cmdbuf[1]; 183 int a, error; 184 185 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 186 return (ENXIO); 187 188 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 189 return (EINVAL); 190 191 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 192 return (error); 193 194 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 195 a = (int)uio->uio_offset; 196 cmdbuf[0] = a + M41ST84_USER_RAM; 197 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 198 sc->sc_address, cmdbuf, 1, 199 &ch, 1, 0)) != 0) { 200 iic_release_bus(sc->sc_tag, 0); 201 aprint_error_dev(sc->sc_dev, 202 "strtc_read: read failed at 0x%x\n", a); 203 return (error); 204 } 205 if ((error = uiomove(&ch, 1, uio)) != 0) { 206 iic_release_bus(sc->sc_tag, 0); 207 return (error); 208 } 209 } 210 211 iic_release_bus(sc->sc_tag, 0); 212 213 return (0); 214 } 215 216 /*ARGSUSED*/ 217 int 218 strtc_write(dev_t dev, struct uio *uio, int flags) 219 { 220 struct strtc_softc *sc; 221 u_int8_t cmdbuf[2]; 222 int a, error; 223 224 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 225 return (ENXIO); 226 227 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 228 return (EINVAL); 229 230 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 231 return (error); 232 233 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 234 a = (int)uio->uio_offset; 235 cmdbuf[0] = a + M41ST84_USER_RAM; 236 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 237 break; 238 239 if ((error = iic_exec(sc->sc_tag, 240 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 241 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 242 aprint_error_dev(sc->sc_dev, 243 "strtc_write: write failed at 0x%x\n", a); 244 break; 245 } 246 } 247 248 iic_release_bus(sc->sc_tag, 0); 249 250 return (error); 251 } 252 #endif /* STRTC_NO_USERRAM */ 253 254 static int 255 strtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 256 { 257 struct strtc_softc *sc = ch->cookie; 258 struct clock_ymdhms check; 259 int retries, error; 260 261 memset(dt, 0, sizeof(*dt)); 262 memset(&check, 0, sizeof(check)); 263 264 /* 265 * Since we don't support Burst Read, we have to read the clock twice 266 * until we get two consecutive identical results. 267 */ 268 retries = 5; 269 do { 270 if ((error = strtc_clock_read(sc, dt)) == 0) 271 error = strtc_clock_read(sc, &check); 272 if (error) 273 return error; 274 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 275 276 return (0); 277 } 278 279 static int 280 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 281 { 282 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 283 int i, error; 284 285 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 286 aprint_error_dev(sc->sc_dev, 287 "strtc_clock_read: failed to acquire I2C bus\n"); 288 return (error); 289 } 290 291 /* 292 * Check for the HT bit -- if set, then clock lost power & stopped 293 * If that happened, then clear the bit so that the clock will have 294 * a chance to run again. 295 */ 296 cmdbuf[0] = M41ST84_REG_AL_HOUR; 297 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 298 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 299 iic_release_bus(sc->sc_tag, 0); 300 aprint_error_dev(sc->sc_dev, 301 "strtc_clock_read: failed to read HT\n"); 302 return (error); 303 } 304 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 305 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 306 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 307 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 308 iic_release_bus(sc->sc_tag, 0); 309 aprint_error_dev(sc->sc_dev, 310 "strtc_clock_read: failed to reset HT\n"); 311 return (error); 312 } 313 } 314 315 /* Read each RTC register in order. */ 316 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 317 cmdbuf[0] = i; 318 319 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 320 sc->sc_address, cmdbuf, 1, 321 &bcd[i], 1, 0)) != 0) { 322 iic_release_bus(sc->sc_tag, 0); 323 aprint_error_dev(sc->sc_dev, 324 "strtc_clock_read: failed to read rtc " 325 "at 0x%x\n", i); 326 return (error); 327 } 328 } 329 330 /* Done with I2C */ 331 iic_release_bus(sc->sc_tag, 0); 332 333 /* 334 * Convert the M41ST84's register values into something useable 335 */ 336 dt->dt_sec = bcdtobin(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 337 dt->dt_min = bcdtobin(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 338 dt->dt_hour = bcdtobin(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 339 dt->dt_day = bcdtobin(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 340 dt->dt_mon = bcdtobin(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 341 342 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 343 /* XXX: Wait, isn't that what rtc_offset in todr_gettime() is for? */ 344 dt->dt_year = bcdtobin(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 345 346 return (0); 347 } 348 349 static int 350 strtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 351 { 352 struct strtc_softc *sc = ch->cookie; 353 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 354 int i, error; 355 356 /* 357 * Convert our time representation into something the M41ST84 358 * can understand. 359 */ 360 bcd[M41ST84_REG_CSEC] = bintobcd(0); /* must always write as 0 */ 361 bcd[M41ST84_REG_SEC] = bintobcd(dt->dt_sec); 362 bcd[M41ST84_REG_MIN] = bintobcd(dt->dt_min); 363 bcd[M41ST84_REG_CENHR] = bintobcd(dt->dt_hour); 364 bcd[M41ST84_REG_DATE] = bintobcd(dt->dt_day); 365 bcd[M41ST84_REG_DAY] = bintobcd(dt->dt_wday); 366 bcd[M41ST84_REG_MONTH] = bintobcd(dt->dt_mon); 367 bcd[M41ST84_REG_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 368 369 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 370 aprint_error_dev(sc->sc_dev, 371 "strtc_clock_write: failed to acquire I2C bus\n"); 372 return (error); 373 } 374 375 /* Stop the clock */ 376 cmdbuf[0] = M41ST84_REG_SEC; 377 cmdbuf[1] = M41ST84_SEC_ST; 378 379 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 380 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 381 iic_release_bus(sc->sc_tag, 0); 382 aprint_error_dev(sc->sc_dev, 383 "strtc_clock_write: failed to Hold Clock\n"); 384 return (error); 385 } 386 387 /* 388 * Check for the HT bit -- if set, then clock lost power & stopped 389 * If that happened, then clear the bit so that the clock will have 390 * a chance to run again. 391 */ 392 cmdbuf[0] = M41ST84_REG_AL_HOUR; 393 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 394 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 395 iic_release_bus(sc->sc_tag, 0); 396 aprint_error_dev(sc->sc_dev, 397 "strtc_clock_write: failed to read HT\n"); 398 return (error); 399 } 400 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 401 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 402 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 403 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 404 iic_release_bus(sc->sc_tag, 0); 405 aprint_error_dev(sc->sc_dev, 406 "strtc_clock_write: failed to reset HT\n"); 407 return (error); 408 } 409 } 410 411 /* 412 * Write registers in reverse order. The last write (to the Seconds 413 * register) will undo the Clock Hold, above. 414 */ 415 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 416 cmdbuf[0] = i; 417 if ((error = iic_exec(sc->sc_tag, 418 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 419 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 420 iic_release_bus(sc->sc_tag, 0); 421 aprint_error_dev(sc->sc_dev, 422 "strtc_clock_write: failed to write rtc " 423 " at 0x%x\n", i); 424 /* XXX: Clock Hold is likely still asserted! */ 425 return (error); 426 } 427 } 428 429 iic_release_bus(sc->sc_tag, 0); 430 431 return (0); 432 } 433 434 #ifndef STRTC_NO_WATCHDOG 435 void 436 strtc_wdog_config(void *arg, uint8_t wd) 437 { 438 struct strtc_softc *sc = arg; 439 uint8_t cmdbuf[2]; 440 441 if (iic_acquire_bus(sc->sc_tag, 0)) { 442 aprint_error_dev(sc->sc_dev, 443 "strtc_wdog_config: failed to acquire I2C bus\n"); 444 return; 445 } 446 447 cmdbuf[0] = M41ST84_REG_WATCHDOG; 448 cmdbuf[1] = wd; 449 450 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 451 cmdbuf, 1, &cmdbuf[1], 1, 0)) { 452 aprint_error_dev(sc->sc_dev, 453 "strtc_wdog_config: failed to write watchdog\n"); 454 return; 455 } 456 457 iic_release_bus(sc->sc_tag, 0); 458 } 459 #endif /* STRTC_NO_WATCHDOG */ 460
Indexes created Thu Sep 25 16:09:42 GMT 2025