m41st84.c revision 1.29
1 /* $NetBSD: m41st84.c,v 1.29 2021/01/18 15:28:21 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.29 2021/01/18 15:28:21 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/m41st84reg.h> 54 #include <dev/i2c/m41st84var.h> 55 56 #include "ioconf.h" 57 58 struct strtc_model { 59 uint16_t sm_model; 60 uint8_t sm_nvram_start; 61 uint8_t sm_nvram_size; 62 uint32_t sm_flags; 63 }; 64 65 #define STRTC_F_HAS_WDOG __BIT(0) 66 67 static const struct strtc_model m41t80_model = { 68 .sm_model = 80, 69 }; 70 71 static const struct strtc_model m41t81_model = { 72 .sm_model = 81, 73 .sm_flags = STRTC_F_HAS_WDOG, 74 }; 75 76 static const struct strtc_model m48t84_model = { 77 .sm_model = 84, 78 .sm_nvram_start = M41ST84_USER_RAM, 79 .sm_nvram_size = M41ST84_USER_RAM_SIZE, 80 .sm_flags = STRTC_F_HAS_WDOG, 81 }; 82 83 static const struct device_compatible_entry compat_data[] = { 84 { .compat = "st,m41t80", .data = &m41t80_model }, 85 { .compat = "st,m41t81", .data = &m41t81_model }, 86 { .compat = "st,m41t84", .data = &m48t84_model }, 87 88 { 0 } 89 }; 90 91 struct strtc_softc { 92 device_t sc_dev; 93 i2c_tag_t sc_tag; 94 int sc_address; 95 int sc_open; 96 const struct strtc_model *sc_model; 97 struct todr_chip_handle sc_todr; 98 }; 99 100 static void strtc_attach(device_t, device_t, void *); 101 static int strtc_match(device_t, cfdata_t, void *); 102 103 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 104 strtc_match, strtc_attach, NULL, NULL); 105 106 dev_type_open(strtc_open); 107 dev_type_close(strtc_close); 108 dev_type_read(strtc_read); 109 dev_type_write(strtc_write); 110 111 const struct cdevsw strtc_cdevsw = { 112 .d_open = strtc_open, 113 .d_close = strtc_close, 114 .d_read = strtc_read, 115 .d_write = strtc_write, 116 .d_ioctl = noioctl, 117 .d_stop = nostop, 118 .d_tty = notty, 119 .d_poll = nopoll, 120 .d_mmap = nommap, 121 .d_kqfilter = nokqfilter, 122 .d_discard = nodiscard, 123 .d_flag = D_OTHER 124 }; 125 126 static int strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *); 127 static int strtc_gettime_ymdhms(struct todr_chip_handle *, 128 struct clock_ymdhms *); 129 static int strtc_settime_ymdhms(struct todr_chip_handle *, 130 struct clock_ymdhms *); 131 132 static const struct strtc_model * 133 strtc_model_by_number(u_int model) 134 { 135 const struct device_compatible_entry *dce; 136 const struct strtc_model *sm; 137 138 /* no model given; assume it's a 41T80 */ 139 if (model == 0) 140 return &m41t80_model; 141 142 for (dce = compat_data; dce->compat != NULL; dce++) { 143 sm = dce->data; 144 if (sm->sm_model == model) 145 return sm; 146 } 147 return NULL; 148 } 149 150 static const struct strtc_model * 151 strtc_model_by_compat(const struct i2c_attach_args *ia) 152 { 153 const struct device_compatible_entry *dce; 154 const struct strtc_model *sm = NULL; 155 156 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL) 157 sm = dce->data; 158 159 return sm; 160 } 161 162 static int 163 strtc_match(device_t parent, cfdata_t cf, void *arg) 164 { 165 struct i2c_attach_args *ia = arg; 166 int match_result; 167 168 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 169 return match_result; 170 171 if (strtc_model_by_number(cf->cf_flags & 0xffff) == NULL) 172 return 0; 173 174 /* indirect config - check typical address */ 175 if (ia->ia_addr == M41ST84_ADDR) 176 return I2C_MATCH_ADDRESS_ONLY; 177 178 return 0; 179 } 180 181 static void 182 strtc_attach(device_t parent, device_t self, void *arg) 183 { 184 struct strtc_softc *sc = device_private(self); 185 struct i2c_attach_args *ia = arg; 186 const struct strtc_model *sm; 187 188 if ((sm = strtc_model_by_compat(ia)) == NULL) 189 sm = strtc_model_by_number(device_cfdata(self)->cf_flags); 190 191 if (sm == NULL) { 192 aprint_error(": unable to determine model!\n"); 193 return; 194 } 195 196 aprint_naive(": Real-time Clock%s\n", 197 sm->sm_nvram_size ? "/NVRAM" : ""); 198 aprint_normal(": M41T%d Real-time Clock%s", sm->sm_model, 199 sm->sm_nvram_size ? "/NVRAM" : ""); 200 201 sc->sc_tag = ia->ia_tag; 202 sc->sc_address = ia->ia_addr; 203 sc->sc_model = sm; 204 sc->sc_dev = self; 205 sc->sc_open = 0; 206 sc->sc_todr.cookie = sc; 207 sc->sc_todr.todr_gettime = NULL; 208 sc->sc_todr.todr_settime = NULL; 209 sc->sc_todr.todr_gettime_ymdhms = strtc_gettime_ymdhms; 210 sc->sc_todr.todr_settime_ymdhms = strtc_settime_ymdhms; 211 sc->sc_todr.todr_setwen = NULL; 212 213 todr_attach(&sc->sc_todr); 214 } 215 216 /*ARGSUSED*/ 217 int 218 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 219 { 220 struct strtc_softc *sc; 221 222 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 223 return (ENXIO); 224 225 /* XXX: Locking */ 226 227 if (sc->sc_open) 228 return (EBUSY); 229 230 sc->sc_open = 1; 231 return (0); 232 } 233 234 /*ARGSUSED*/ 235 int 236 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 237 { 238 struct strtc_softc *sc; 239 240 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 241 return (ENXIO); 242 243 sc->sc_open = 0; 244 return (0); 245 } 246 247 /*ARGSUSED*/ 248 int 249 strtc_read(dev_t dev, struct uio *uio, int flags) 250 { 251 struct strtc_softc *sc; 252 u_int8_t ch, cmdbuf[1]; 253 int a, error; 254 255 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 256 return (ENXIO); 257 258 const struct strtc_model * const sm = sc->sc_model; 259 260 if (uio->uio_offset >= sm->sm_nvram_size) 261 return (EINVAL); 262 263 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 264 return (error); 265 266 while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) { 267 a = (int)uio->uio_offset; 268 cmdbuf[0] = a + sm->sm_nvram_start; 269 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 270 sc->sc_address, cmdbuf, 1, 271 &ch, 1, 0)) != 0) { 272 iic_release_bus(sc->sc_tag, 0); 273 aprint_error_dev(sc->sc_dev, 274 "strtc_read: read failed at 0x%x\n", a); 275 return (error); 276 } 277 if ((error = uiomove(&ch, 1, uio)) != 0) { 278 iic_release_bus(sc->sc_tag, 0); 279 return (error); 280 } 281 } 282 283 iic_release_bus(sc->sc_tag, 0); 284 285 return (0); 286 } 287 288 /*ARGSUSED*/ 289 int 290 strtc_write(dev_t dev, struct uio *uio, int flags) 291 { 292 struct strtc_softc *sc; 293 u_int8_t cmdbuf[2]; 294 int a, error; 295 296 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 297 return (ENXIO); 298 299 const struct strtc_model * const sm = sc->sc_model; 300 301 if (uio->uio_offset >= sm->sm_nvram_size) 302 return (EINVAL); 303 304 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 305 return (error); 306 307 while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) { 308 a = (int)uio->uio_offset; 309 cmdbuf[0] = a + sm->sm_nvram_start; 310 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 311 break; 312 313 if ((error = iic_exec(sc->sc_tag, 314 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 315 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 316 aprint_error_dev(sc->sc_dev, 317 "strtc_write: write failed at 0x%x\n", a); 318 break; 319 } 320 } 321 322 iic_release_bus(sc->sc_tag, 0); 323 324 return (error); 325 } 326 327 static int 328 strtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 329 { 330 struct strtc_softc *sc = ch->cookie; 331 struct clock_ymdhms check; 332 int retries, error; 333 334 memset(dt, 0, sizeof(*dt)); 335 memset(&check, 0, sizeof(check)); 336 337 /* 338 * Since we don't support Burst Read, we have to read the clock twice 339 * until we get two consecutive identical results. 340 */ 341 retries = 5; 342 do { 343 if ((error = strtc_clock_read(sc, dt)) == 0) 344 error = strtc_clock_read(sc, &check); 345 if (error) 346 return error; 347 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 348 349 return (0); 350 } 351 352 static int 353 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 354 { 355 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 356 int i, error; 357 358 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "strtc_clock_read: failed to acquire I2C bus\n"); 361 return (error); 362 } 363 364 /* 365 * Check for the HT bit -- if set, then clock lost power & stopped 366 * If that happened, then clear the bit so that the clock will have 367 * a chance to run again. 368 */ 369 cmdbuf[0] = M41ST84_REG_AL_HOUR; 370 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 371 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 372 iic_release_bus(sc->sc_tag, 0); 373 aprint_error_dev(sc->sc_dev, 374 "strtc_clock_read: failed to read HT\n"); 375 return (error); 376 } 377 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 378 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 379 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 380 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 381 iic_release_bus(sc->sc_tag, 0); 382 aprint_error_dev(sc->sc_dev, 383 "strtc_clock_read: failed to reset HT\n"); 384 return (error); 385 } 386 } 387 388 /* Read each RTC register in order. */ 389 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 390 cmdbuf[0] = i; 391 392 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 393 sc->sc_address, cmdbuf, 1, 394 &bcd[i], 1, 0)) != 0) { 395 iic_release_bus(sc->sc_tag, 0); 396 aprint_error_dev(sc->sc_dev, 397 "strtc_clock_read: failed to read rtc " 398 "at 0x%x\n", i); 399 return (error); 400 } 401 } 402 403 /* Done with I2C */ 404 iic_release_bus(sc->sc_tag, 0); 405 406 /* 407 * Convert the M41ST84's register values into something useable 408 */ 409 dt->dt_sec = bcdtobin(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 410 dt->dt_min = bcdtobin(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 411 dt->dt_hour = bcdtobin(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 412 dt->dt_day = bcdtobin(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 413 dt->dt_mon = bcdtobin(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 414 415 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 416 /* XXX: Wait, isn't that what rtc_offset in todr_gettime() is for? */ 417 dt->dt_year = bcdtobin(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 418 419 return (0); 420 } 421 422 static int 423 strtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 424 { 425 struct strtc_softc *sc = ch->cookie; 426 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 427 int i, error; 428 429 /* 430 * Convert our time representation into something the M41ST84 431 * can understand. 432 */ 433 bcd[M41ST84_REG_CSEC] = bintobcd(0); /* must always write as 0 */ 434 bcd[M41ST84_REG_SEC] = bintobcd(dt->dt_sec); 435 bcd[M41ST84_REG_MIN] = bintobcd(dt->dt_min); 436 bcd[M41ST84_REG_CENHR] = bintobcd(dt->dt_hour); 437 bcd[M41ST84_REG_DATE] = bintobcd(dt->dt_day); 438 bcd[M41ST84_REG_DAY] = bintobcd(dt->dt_wday); 439 bcd[M41ST84_REG_MONTH] = bintobcd(dt->dt_mon); 440 bcd[M41ST84_REG_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 441 442 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 443 aprint_error_dev(sc->sc_dev, 444 "strtc_clock_write: failed to acquire I2C bus\n"); 445 return (error); 446 } 447 448 /* Stop the clock */ 449 cmdbuf[0] = M41ST84_REG_SEC; 450 cmdbuf[1] = M41ST84_SEC_ST; 451 452 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 453 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 454 iic_release_bus(sc->sc_tag, 0); 455 aprint_error_dev(sc->sc_dev, 456 "strtc_clock_write: failed to Hold Clock\n"); 457 return (error); 458 } 459 460 /* 461 * Check for the HT bit -- if set, then clock lost power & stopped 462 * If that happened, then clear the bit so that the clock will have 463 * a chance to run again. 464 */ 465 cmdbuf[0] = M41ST84_REG_AL_HOUR; 466 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 467 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 468 iic_release_bus(sc->sc_tag, 0); 469 aprint_error_dev(sc->sc_dev, 470 "strtc_clock_write: failed to read HT\n"); 471 return (error); 472 } 473 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 474 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 475 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 476 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 477 iic_release_bus(sc->sc_tag, 0); 478 aprint_error_dev(sc->sc_dev, 479 "strtc_clock_write: failed to reset HT\n"); 480 return (error); 481 } 482 } 483 484 /* 485 * Write registers in reverse order. The last write (to the Seconds 486 * register) will undo the Clock Hold, above. 487 */ 488 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 489 cmdbuf[0] = i; 490 if ((error = iic_exec(sc->sc_tag, 491 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 492 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 493 iic_release_bus(sc->sc_tag, 0); 494 aprint_error_dev(sc->sc_dev, 495 "strtc_clock_write: failed to write rtc " 496 " at 0x%x\n", i); 497 /* XXX: Clock Hold is likely still asserted! */ 498 return (error); 499 } 500 } 501 502 iic_release_bus(sc->sc_tag, 0); 503 504 return (0); 505 } 506 507 void 508 strtc_wdog_config(void *arg, uint8_t wd) 509 { 510 struct strtc_softc *sc = arg; 511 uint8_t cmdbuf[2]; 512 513 if ((sc->sc_model->sm_flags & STRTC_F_HAS_WDOG) == 0) { 514 aprint_error_dev(sc->sc_dev, 515 "strtc_wdog_config: watchdog timer not present\n"); 516 return; 517 } 518 519 if (iic_acquire_bus(sc->sc_tag, 0)) { 520 aprint_error_dev(sc->sc_dev, 521 "strtc_wdog_config: failed to acquire I2C bus\n"); 522 return; 523 } 524 525 cmdbuf[0] = M41ST84_REG_WATCHDOG; 526 cmdbuf[1] = wd; 527 528 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 529 cmdbuf, 1, &cmdbuf[1], 1, 0)) { 530 aprint_error_dev(sc->sc_dev, 531 "strtc_wdog_config: failed to write watchdog\n"); 532 return; 533 } 534 535 iic_release_bus(sc->sc_tag, 0); 536 } 537
Indexes created Tue Sep 23 23:09:58 GMT 2025