m41st84.c revision 1.34
1 /* $NetBSD: m41st84.c,v 1.34 2025/09/07 21:45:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.34 2025/09/07 21:45:15 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/m41st84reg.h> 54 #include <dev/i2c/m41st84var.h> 55 56 #include "ioconf.h" 57 58 struct strtc_model { 59 uint16_t sm_model; 60 uint8_t sm_nvram_start; 61 uint8_t sm_nvram_size; 62 uint32_t sm_flags; 63 }; 64 65 #define STRTC_F_HAS_WDOG __BIT(0) 66 67 static const struct strtc_model m41t80_model = { 68 .sm_model = 80, 69 }; 70 71 static const struct strtc_model m41t81_model = { 72 .sm_model = 81, 73 .sm_flags = STRTC_F_HAS_WDOG, 74 }; 75 76 static const struct strtc_model m48t84_model = { 77 .sm_model = 84, 78 .sm_nvram_start = M41ST84_USER_RAM, 79 .sm_nvram_size = M41ST84_USER_RAM_SIZE, 80 .sm_flags = STRTC_F_HAS_WDOG, 81 }; 82 83 static const struct device_compatible_entry compat_data[] = { 84 { .compat = "st,m41t80", .data = &m41t80_model }, 85 { .compat = "st,m41t81", .data = &m41t81_model }, 86 { .compat = "st,m41t84", .data = &m48t84_model }, 87 DEVICE_COMPAT_EOL 88 }; 89 90 struct strtc_softc { 91 device_t sc_dev; 92 i2c_tag_t sc_tag; 93 int sc_address; 94 int sc_open; 95 const struct strtc_model *sc_model; 96 struct todr_chip_handle sc_todr; 97 }; 98 99 static void strtc_attach(device_t, device_t, void *); 100 static int strtc_match(device_t, cfdata_t, void *); 101 102 CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc), 103 strtc_match, strtc_attach, NULL, NULL); 104 105 dev_type_open(strtc_open); 106 dev_type_close(strtc_close); 107 dev_type_read(strtc_read); 108 dev_type_write(strtc_write); 109 110 const struct cdevsw strtc_cdevsw = { 111 .d_open = strtc_open, 112 .d_close = strtc_close, 113 .d_read = strtc_read, 114 .d_write = strtc_write, 115 .d_ioctl = noioctl, 116 .d_stop = nostop, 117 .d_tty = notty, 118 .d_poll = nopoll, 119 .d_mmap = nommap, 120 .d_kqfilter = nokqfilter, 121 .d_discard = nodiscard, 122 .d_flag = D_OTHER 123 }; 124 125 static int strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *); 126 static int strtc_gettime_ymdhms(struct todr_chip_handle *, 127 struct clock_ymdhms *); 128 static int strtc_settime_ymdhms(struct todr_chip_handle *, 129 struct clock_ymdhms *); 130 131 static const struct strtc_model * 132 strtc_model_by_number(u_int model) 133 { 134 const struct device_compatible_entry *dce; 135 const struct strtc_model *sm; 136 137 /* no model given; assume it's a 41T80 */ 138 if (model == 0) 139 return &m41t80_model; 140 141 for (dce = compat_data; dce->compat != NULL; dce++) { 142 sm = dce->data; 143 if (sm->sm_model == model) 144 return sm; 145 } 146 return NULL; 147 } 148 149 static const struct strtc_model * 150 strtc_model_by_compat(const struct i2c_attach_args *ia) 151 { 152 const struct device_compatible_entry *dce; 153 const struct strtc_model *sm = NULL; 154 155 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL) 156 sm = dce->data; 157 158 return sm; 159 } 160 161 static int 162 strtc_match(device_t parent, cfdata_t cf, void *arg) 163 { 164 struct i2c_attach_args *ia = arg; 165 int match_result; 166 167 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 168 return match_result; 169 170 if (strtc_model_by_number(cf->cf_flags & 0xffff) == NULL) 171 return 0; 172 173 /* indirect config - check typical address */ 174 if (ia->ia_addr == M41ST84_ADDR) 175 return I2C_MATCH_ADDRESS_ONLY; 176 177 return 0; 178 } 179 180 static void 181 strtc_attach(device_t parent, device_t self, void *arg) 182 { 183 struct strtc_softc *sc = device_private(self); 184 struct i2c_attach_args *ia = arg; 185 const struct strtc_model *sm; 186 187 if ((sm = strtc_model_by_compat(ia)) == NULL) 188 sm = strtc_model_by_number(device_cfdata(self)->cf_flags); 189 190 if (sm == NULL) { 191 aprint_error(": unable to determine model!\n"); 192 return; 193 } 194 195 aprint_naive(": Real-time Clock%s\n", 196 sm->sm_nvram_size ? "/NVRAM" : ""); 197 aprint_normal(": M41T%d Real-time Clock%s\n", sm->sm_model, 198 sm->sm_nvram_size ? "/NVRAM" : ""); 199 200 sc->sc_tag = ia->ia_tag; 201 sc->sc_address = ia->ia_addr; 202 sc->sc_model = sm; 203 sc->sc_dev = self; 204 sc->sc_open = 0; 205 sc->sc_todr.todr_dev = self; 206 sc->sc_todr.todr_gettime_ymdhms = strtc_gettime_ymdhms; 207 sc->sc_todr.todr_settime_ymdhms = strtc_settime_ymdhms; 208 209 todr_attach(&sc->sc_todr); 210 } 211 212 /*ARGSUSED*/ 213 int 214 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 215 { 216 struct strtc_softc *sc; 217 218 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 219 return (ENXIO); 220 221 /* XXX: Locking */ 222 223 if (sc->sc_open) 224 return (EBUSY); 225 226 sc->sc_open = 1; 227 return (0); 228 } 229 230 /*ARGSUSED*/ 231 int 232 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 233 { 234 struct strtc_softc *sc; 235 236 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 237 return (ENXIO); 238 239 sc->sc_open = 0; 240 return (0); 241 } 242 243 /*ARGSUSED*/ 244 int 245 strtc_read(dev_t dev, struct uio *uio, int flags) 246 { 247 struct strtc_softc *sc; 248 u_int8_t ch, cmdbuf[1]; 249 int a, error; 250 251 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 252 return (ENXIO); 253 254 const struct strtc_model * const sm = sc->sc_model; 255 256 if (uio->uio_offset >= sm->sm_nvram_size) 257 return (EINVAL); 258 259 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 260 return (error); 261 262 while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) { 263 a = (int)uio->uio_offset; 264 cmdbuf[0] = a + sm->sm_nvram_start; 265 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 266 sc->sc_address, cmdbuf, 1, 267 &ch, 1, 0)) != 0) { 268 iic_release_bus(sc->sc_tag, 0); 269 aprint_error_dev(sc->sc_dev, 270 "strtc_read: read failed at 0x%x\n", a); 271 return (error); 272 } 273 if ((error = uiomove(&ch, 1, uio)) != 0) { 274 iic_release_bus(sc->sc_tag, 0); 275 return (error); 276 } 277 } 278 279 iic_release_bus(sc->sc_tag, 0); 280 281 return (0); 282 } 283 284 /*ARGSUSED*/ 285 int 286 strtc_write(dev_t dev, struct uio *uio, int flags) 287 { 288 struct strtc_softc *sc; 289 u_int8_t cmdbuf[2]; 290 int a, error; 291 292 if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL) 293 return (ENXIO); 294 295 const struct strtc_model * const sm = sc->sc_model; 296 297 if (uio->uio_offset >= sm->sm_nvram_size) 298 return (EINVAL); 299 300 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 301 return (error); 302 303 while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) { 304 a = (int)uio->uio_offset; 305 cmdbuf[0] = a + sm->sm_nvram_start; 306 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 307 break; 308 309 if ((error = iic_exec(sc->sc_tag, 310 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 311 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 312 aprint_error_dev(sc->sc_dev, 313 "strtc_write: write failed at 0x%x\n", a); 314 break; 315 } 316 } 317 318 iic_release_bus(sc->sc_tag, 0); 319 320 return (error); 321 } 322 323 static int 324 strtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 325 { 326 struct strtc_softc *sc = device_private(ch->todr_dev); 327 struct clock_ymdhms check; 328 int retries, error; 329 330 memset(dt, 0, sizeof(*dt)); 331 memset(&check, 0, sizeof(check)); 332 333 /* 334 * Since we don't support Burst Read, we have to read the clock twice 335 * until we get two consecutive identical results. 336 */ 337 retries = 5; 338 do { 339 if ((error = strtc_clock_read(sc, dt)) == 0) 340 error = strtc_clock_read(sc, &check); 341 if (error) 342 return error; 343 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 344 345 return (0); 346 } 347 348 static int 349 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 350 { 351 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 352 int i, error; 353 354 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 355 aprint_error_dev(sc->sc_dev, 356 "strtc_clock_read: failed to acquire I2C bus\n"); 357 return (error); 358 } 359 360 /* 361 * Check for the HT bit -- if set, then clock lost power & stopped 362 * If that happened, then clear the bit so that the clock will have 363 * a chance to run again. 364 */ 365 cmdbuf[0] = M41ST84_REG_AL_HOUR; 366 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 367 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 368 iic_release_bus(sc->sc_tag, 0); 369 aprint_error_dev(sc->sc_dev, 370 "strtc_clock_read: failed to read HT\n"); 371 return (error); 372 } 373 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 374 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 375 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 376 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 377 iic_release_bus(sc->sc_tag, 0); 378 aprint_error_dev(sc->sc_dev, 379 "strtc_clock_read: failed to reset HT\n"); 380 return (error); 381 } 382 } 383 384 /* Read each RTC register in order. */ 385 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 386 cmdbuf[0] = i; 387 388 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 389 sc->sc_address, cmdbuf, 1, 390 &bcd[i], 1, 0)) != 0) { 391 iic_release_bus(sc->sc_tag, 0); 392 aprint_error_dev(sc->sc_dev, 393 "strtc_clock_read: failed to read rtc " 394 "at 0x%x\n", i); 395 return (error); 396 } 397 } 398 399 /* Done with I2C */ 400 iic_release_bus(sc->sc_tag, 0); 401 402 /* 403 * Convert the M41ST84's register values into something useable 404 */ 405 dt->dt_sec = bcdtobin(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 406 dt->dt_min = bcdtobin(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 407 dt->dt_hour = bcdtobin(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 408 dt->dt_day = bcdtobin(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 409 dt->dt_mon = bcdtobin(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 410 411 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 412 /* XXX: Wait, isn't that what rtc_offset in todr_gettime() is for? */ 413 dt->dt_year = bcdtobin(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 414 415 return (0); 416 } 417 418 static int 419 strtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 420 { 421 struct strtc_softc *sc = device_private(ch->todr_dev); 422 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 423 int i, error; 424 425 /* 426 * Convert our time representation into something the M41ST84 427 * can understand. 428 */ 429 bcd[M41ST84_REG_CSEC] = bintobcd(0); /* must always write as 0 */ 430 bcd[M41ST84_REG_SEC] = bintobcd(dt->dt_sec); 431 bcd[M41ST84_REG_MIN] = bintobcd(dt->dt_min); 432 bcd[M41ST84_REG_CENHR] = bintobcd(dt->dt_hour); 433 bcd[M41ST84_REG_DATE] = bintobcd(dt->dt_day); 434 bcd[M41ST84_REG_DAY] = bintobcd(dt->dt_wday); 435 bcd[M41ST84_REG_MONTH] = bintobcd(dt->dt_mon); 436 bcd[M41ST84_REG_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100); 437 438 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 439 aprint_error_dev(sc->sc_dev, 440 "strtc_clock_write: failed to acquire I2C bus\n"); 441 return (error); 442 } 443 444 /* Stop the clock */ 445 cmdbuf[0] = M41ST84_REG_SEC; 446 cmdbuf[1] = M41ST84_SEC_ST; 447 448 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 449 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 450 iic_release_bus(sc->sc_tag, 0); 451 aprint_error_dev(sc->sc_dev, 452 "strtc_clock_write: failed to Hold Clock\n"); 453 return (error); 454 } 455 456 /* 457 * Check for the HT bit -- if set, then clock lost power & stopped 458 * If that happened, then clear the bit so that the clock will have 459 * a chance to run again. 460 */ 461 cmdbuf[0] = M41ST84_REG_AL_HOUR; 462 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 463 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 464 iic_release_bus(sc->sc_tag, 0); 465 aprint_error_dev(sc->sc_dev, 466 "strtc_clock_write: failed to read HT\n"); 467 return (error); 468 } 469 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 470 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 471 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 472 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 473 iic_release_bus(sc->sc_tag, 0); 474 aprint_error_dev(sc->sc_dev, 475 "strtc_clock_write: failed to reset HT\n"); 476 return (error); 477 } 478 } 479 480 /* 481 * Write registers in reverse order. The last write (to the Seconds 482 * register) will undo the Clock Hold, above. 483 */ 484 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 485 cmdbuf[0] = i; 486 if ((error = iic_exec(sc->sc_tag, 487 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 488 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 489 iic_release_bus(sc->sc_tag, 0); 490 aprint_error_dev(sc->sc_dev, 491 "strtc_clock_write: failed to write rtc " 492 " at 0x%x\n", i); 493 /* XXX: Clock Hold is likely still asserted! */ 494 return (error); 495 } 496 } 497 498 iic_release_bus(sc->sc_tag, 0); 499 500 return (0); 501 } 502 503 void 504 strtc_wdog_config(void *arg, uint8_t wd) 505 { 506 struct strtc_softc *sc = arg; 507 uint8_t cmdbuf[2]; 508 509 if ((sc->sc_model->sm_flags & STRTC_F_HAS_WDOG) == 0) { 510 aprint_error_dev(sc->sc_dev, 511 "strtc_wdog_config: watchdog timer not present\n"); 512 return; 513 } 514 515 if (iic_acquire_bus(sc->sc_tag, 0)) { 516 aprint_error_dev(sc->sc_dev, 517 "strtc_wdog_config: failed to acquire I2C bus\n"); 518 return; 519 } 520 521 cmdbuf[0] = M41ST84_REG_WATCHDOG; 522 cmdbuf[1] = wd; 523 524 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 525 cmdbuf, 1, &cmdbuf[1], 1, 0)) { 526 aprint_error_dev(sc->sc_dev, 527 "strtc_wdog_config: failed to write watchdog\n"); 528 return; 529 } 530 531 iic_release_bus(sc->sc_tag, 0); 532 } 533
Indexes created Mon Sep 29 21:09:56 GMT 2025