m41st84.c revision 1.9
1 /* $NetBSD: m41st84.c,v 1.9 2007/01/12 19:33:21 cube Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/fcntl.h> 43 #include <sys/uio.h> 44 #include <sys/conf.h> 45 #include <sys/event.h> 46 47 #include <dev/clock_subr.h> 48 49 #include <dev/i2c/i2cvar.h> 50 #include <dev/i2c/m41st84reg.h> 51 52 struct strtc_softc { 53 struct device sc_dev; 54 i2c_tag_t sc_tag; 55 int sc_address; 56 int sc_open; 57 struct todr_chip_handle sc_todr; 58 }; 59 60 static void strtc_attach(struct device *, struct device *, void *); 61 static int strtc_match(struct device *, struct cfdata *, void *); 62 63 CFATTACH_DECL(strtc, sizeof(struct strtc_softc), 64 strtc_match, strtc_attach, NULL, NULL); 65 extern struct cfdriver strtc_cd; 66 67 dev_type_open(strtc_open); 68 dev_type_close(strtc_close); 69 dev_type_read(strtc_read); 70 dev_type_write(strtc_write); 71 72 const struct cdevsw strtc_cdevsw = { 73 strtc_open, strtc_close, strtc_read, strtc_write, noioctl, 74 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 75 }; 76 77 static int strtc_clock_read(struct strtc_softc *, struct clock_ymdhms *); 78 static int strtc_clock_write(struct strtc_softc *, struct clock_ymdhms *); 79 static int strtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 80 static int strtc_settime(struct todr_chip_handle *, volatile struct timeval *); 81 82 static int 83 strtc_match(struct device *parent, struct cfdata *cf, void *arg) 84 { 85 struct i2c_attach_args *ia = arg; 86 87 if (ia->ia_addr == M41ST84_ADDR) 88 return (1); 89 90 return (0); 91 } 92 93 static void 94 strtc_attach(struct device *parent, struct device *self, void *arg) 95 { 96 struct strtc_softc *sc = device_private(self); 97 struct i2c_attach_args *ia = arg; 98 99 aprint_naive(": Real-time Clock/NVRAM\n"); 100 aprint_normal(": M41ST84 Real-time Clock/NVRAM\n"); 101 102 sc->sc_tag = ia->ia_tag; 103 sc->sc_address = ia->ia_addr; 104 sc->sc_open = 0; 105 sc->sc_todr.cookie = sc; 106 sc->sc_todr.todr_gettime = strtc_gettime; 107 sc->sc_todr.todr_settime = strtc_settime; 108 sc->sc_todr.todr_setwen = NULL; 109 110 todr_attach(&sc->sc_todr); 111 } 112 113 /*ARGSUSED*/ 114 int 115 strtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 116 { 117 struct strtc_softc *sc; 118 119 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 120 return (ENXIO); 121 122 /* XXX: Locking */ 123 124 if (sc->sc_open) 125 return (EBUSY); 126 127 sc->sc_open = 1; 128 return (0); 129 } 130 131 /*ARGSUSED*/ 132 int 133 strtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 134 { 135 struct strtc_softc *sc; 136 137 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 138 return (ENXIO); 139 140 sc->sc_open = 0; 141 return (0); 142 } 143 144 /*ARGSUSED*/ 145 int 146 strtc_read(dev_t dev, struct uio *uio, int flags) 147 { 148 struct strtc_softc *sc; 149 u_int8_t ch, cmdbuf[1]; 150 int a, error; 151 152 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 153 return (ENXIO); 154 155 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 156 return (EINVAL); 157 158 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 159 return (error); 160 161 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 162 a = (int)uio->uio_offset; 163 cmdbuf[0] = a + M41ST84_USER_RAM; 164 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 165 sc->sc_address, cmdbuf, 1, 166 &ch, 1, 0)) != 0) { 167 iic_release_bus(sc->sc_tag, 0); 168 printf("%s: strtc_read: read failed at 0x%x\n", 169 sc->sc_dev.dv_xname, a); 170 return (error); 171 } 172 if ((error = uiomove(&ch, 1, uio)) != 0) { 173 iic_release_bus(sc->sc_tag, 0); 174 return (error); 175 } 176 } 177 178 iic_release_bus(sc->sc_tag, 0); 179 180 return (0); 181 } 182 183 /*ARGSUSED*/ 184 int 185 strtc_write(dev_t dev, struct uio *uio, int flags) 186 { 187 struct strtc_softc *sc; 188 u_int8_t cmdbuf[2]; 189 int a, error; 190 191 if ((sc = device_lookup(&strtc_cd, minor(dev))) == NULL) 192 return (ENXIO); 193 194 if (uio->uio_offset >= M41ST84_USER_RAM_SIZE) 195 return (EINVAL); 196 197 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 198 return (error); 199 200 while (uio->uio_resid && uio->uio_offset < M41ST84_USER_RAM_SIZE) { 201 a = (int)uio->uio_offset; 202 cmdbuf[0] = a + M41ST84_USER_RAM; 203 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 204 break; 205 206 if ((error = iic_exec(sc->sc_tag, 207 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 208 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 209 printf("%s: strtc_write: write failed at 0x%x\n", 210 sc->sc_dev.dv_xname, a); 211 break; 212 } 213 } 214 215 iic_release_bus(sc->sc_tag, 0); 216 217 return (error); 218 } 219 220 static int 221 strtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 222 { 223 struct strtc_softc *sc = ch->cookie; 224 struct clock_ymdhms dt, check; 225 int retries; 226 227 memset(&dt, 0, sizeof(dt)); 228 memset(&check, 0, sizeof(check)); 229 230 /* 231 * Since we don't support Burst Read, we have to read the clock twice 232 * until we get two consecutive identical results. 233 */ 234 retries = 5; 235 do { 236 strtc_clock_read(sc, &dt); 237 strtc_clock_read(sc, &check); 238 } while (memcmp(&dt, &check, sizeof(check)) != 0 && --retries); 239 240 tv->tv_sec = clock_ymdhms_to_secs(&dt); 241 tv->tv_usec = 0; 242 243 return (0); 244 } 245 246 static int 247 strtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 248 { 249 struct strtc_softc *sc = ch->cookie; 250 struct clock_ymdhms dt; 251 252 clock_secs_to_ymdhms(tv->tv_sec, &dt); 253 254 if (strtc_clock_write(sc, &dt) == 0) 255 return (-1); 256 257 return (0); 258 } 259 260 static int 261 strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt) 262 { 263 u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[1]; 264 int i; 265 266 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 267 printf("%s: strtc_clock_read: failed to acquire I2C bus\n", 268 sc->sc_dev.dv_xname); 269 return (0); 270 } 271 272 /* 273 * Check for the HT bit -- if set, then clock lost power & stopped 274 * If that happened, then clear the bit so that the clock will have 275 * a chance to run again. 276 */ 277 cmdbuf[0] = M41ST84_REG_AL_HOUR; 278 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 279 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 280 iic_release_bus(sc->sc_tag, I2C_F_POLL); 281 printf("%s: strtc_clock_read: failed to read HT\n", 282 sc->sc_dev.dv_xname); 283 return (0); 284 } 285 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 286 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 287 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 288 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 289 iic_release_bus(sc->sc_tag, I2C_F_POLL); 290 printf("%s: strtc_clock_read: failed to reset HT\n", 291 sc->sc_dev.dv_xname); 292 return (0); 293 } 294 } 295 296 /* Read each RTC register in order. */ 297 for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) { 298 cmdbuf[0] = i; 299 300 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 301 sc->sc_address, cmdbuf, 1, 302 &bcd[i], 1, I2C_F_POLL)) { 303 iic_release_bus(sc->sc_tag, I2C_F_POLL); 304 printf("%s: strtc_clock_read: failed to read rtc " 305 "at 0x%x\n", sc->sc_dev.dv_xname, i); 306 return (0); 307 } 308 } 309 310 /* Done with I2C */ 311 iic_release_bus(sc->sc_tag, I2C_F_POLL); 312 313 /* 314 * Convert the M41ST84's register values into something useable 315 */ 316 dt->dt_sec = FROMBCD(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK); 317 dt->dt_min = FROMBCD(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK); 318 dt->dt_hour = FROMBCD(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK); 319 dt->dt_day = FROMBCD(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK); 320 dt->dt_mon = FROMBCD(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK); 321 322 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 323 dt->dt_year = FROMBCD(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR; 324 325 return (1); 326 } 327 328 static int 329 strtc_clock_write(struct strtc_softc *sc, struct clock_ymdhms *dt) 330 { 331 uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2]; 332 int i; 333 334 /* 335 * Convert our time representation into something the M41ST84 336 * can understand. 337 */ 338 bcd[M41ST84_REG_CSEC] = TOBCD(0); /* must always write as 0 */ 339 bcd[M41ST84_REG_SEC] = TOBCD(dt->dt_sec); 340 bcd[M41ST84_REG_MIN] = TOBCD(dt->dt_min); 341 bcd[M41ST84_REG_CENHR] = TOBCD(dt->dt_hour); 342 bcd[M41ST84_REG_DATE] = TOBCD(dt->dt_day); 343 bcd[M41ST84_REG_DAY] = TOBCD(dt->dt_wday); 344 bcd[M41ST84_REG_MONTH] = TOBCD(dt->dt_mon); 345 bcd[M41ST84_REG_YEAR] = TOBCD((dt->dt_year - POSIX_BASE_YEAR) % 100); 346 347 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 348 printf("%s: strtc_clock_write: failed to acquire I2C bus\n", 349 sc->sc_dev.dv_xname); 350 return (0); 351 } 352 353 /* Stop the clock */ 354 cmdbuf[0] = M41ST84_REG_SEC; 355 cmdbuf[1] = M41ST84_SEC_ST; 356 357 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 358 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 359 iic_release_bus(sc->sc_tag, I2C_F_POLL); 360 printf("%s: strtc_clock_write: failed to Hold Clock\n", 361 sc->sc_dev.dv_xname); 362 return (0); 363 } 364 365 /* 366 * Check for the HT bit -- if set, then clock lost power & stopped 367 * If that happened, then clear the bit so that the clock will have 368 * a chance to run again. 369 */ 370 cmdbuf[0] = M41ST84_REG_AL_HOUR; 371 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 372 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 373 iic_release_bus(sc->sc_tag, I2C_F_POLL); 374 printf("%s: strtc_clock_write: failed to read HT\n", 375 sc->sc_dev.dv_xname); 376 return (0); 377 } 378 if (cmdbuf[1] & M41ST84_AL_HOUR_HT) { 379 cmdbuf[1] &= ~M41ST84_AL_HOUR_HT; 380 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 381 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 382 iic_release_bus(sc->sc_tag, I2C_F_POLL); 383 printf("%s: strtc_clock_write: failed to reset HT\n", 384 sc->sc_dev.dv_xname); 385 return (0); 386 } 387 } 388 389 /* 390 * Write registers in reverse order. The last write (to the Seconds 391 * register) will undo the Clock Hold, above. 392 */ 393 for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) { 394 cmdbuf[0] = i; 395 if (iic_exec(sc->sc_tag, 396 i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 397 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 398 I2C_F_POLL)) { 399 iic_release_bus(sc->sc_tag, I2C_F_POLL); 400 printf("%s: strtc_clock_write: failed to write rtc " 401 " at 0x%x\n", sc->sc_dev.dv_xname, i); 402 /* XXX: Clock Hold is likely still asserted! */ 403 return (0); 404 } 405 } 406 407 iic_release_bus(sc->sc_tag, I2C_F_POLL); 408 409 return (1); 410 } 411
Indexes created Fri Sep 26 20:09:58 GMT 2025