m41t00.c revision 1.11
1 /* $NetBSD: m41t00.c,v 1.11 2008/04/06 20:25:59 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41t00.c,v 1.11 2008/04/06 20:25:59 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <dev/i2c/i2cvar.h> 56 #include <dev/i2c/m41t00reg.h> 57 58 struct m41t00_softc { 59 struct device sc_dev; 60 i2c_tag_t sc_tag; 61 int sc_address; 62 int sc_open; 63 struct todr_chip_handle sc_todr; 64 }; 65 66 static int m41t00_match(struct device *, struct cfdata *, void *); 67 static void m41t00_attach(struct device *, struct device *, void *); 68 69 CFATTACH_DECL(m41trtc, sizeof(struct m41t00_softc), 70 m41t00_match, m41t00_attach, NULL, NULL); 71 extern struct cfdriver m41trtc_cd; 72 73 dev_type_open(m41t00_open); 74 dev_type_close(m41t00_close); 75 dev_type_read(m41t00_read); 76 dev_type_write(m41t00_write); 77 78 const struct cdevsw m41t00_cdevsw = { 79 m41t00_open, m41t00_close, m41t00_read, m41t00_write, noioctl, 80 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 81 }; 82 83 static int m41t00_clock_read(struct m41t00_softc *, struct clock_ymdhms *); 84 static int m41t00_clock_write(struct m41t00_softc *, struct clock_ymdhms *); 85 static int m41t00_gettime(struct todr_chip_handle *, volatile struct timeval *); 86 static int m41t00_settime(struct todr_chip_handle *, volatile struct timeval *); 87 88 int 89 m41t00_match(struct device *parent, struct cfdata *cf, void *aux) 90 { 91 struct i2c_attach_args *ia = aux; 92 93 if (ia->ia_addr == M41T00_ADDR) { 94 return 1; 95 } 96 97 return 0; 98 } 99 100 void 101 m41t00_attach(struct device *parent, struct device *self, void *aux) 102 { 103 struct m41t00_softc *sc = device_private(self); 104 struct i2c_attach_args *ia = aux; 105 106 sc->sc_tag = ia->ia_tag; 107 sc->sc_address = ia->ia_addr; 108 109 aprint_naive(": Real-time Clock\n"); 110 aprint_normal(": M41T00 Real-time Clock\n"); 111 112 sc->sc_open = 0; 113 sc->sc_todr.cookie = sc; 114 sc->sc_todr.todr_gettime = m41t00_gettime; 115 sc->sc_todr.todr_settime = m41t00_settime; 116 sc->sc_todr.todr_setwen = NULL; 117 118 todr_attach(&sc->sc_todr); 119 } 120 121 /*ARGSUSED*/ 122 int 123 m41t00_open(dev_t dev, int flag, int fmt, struct lwp *l) 124 { 125 struct m41t00_softc *sc; 126 127 if ((sc = device_lookup(&m41trtc_cd, minor(dev))) == NULL) 128 return ENXIO; 129 130 /* XXX: Locking */ 131 132 if (sc->sc_open) 133 return EBUSY; 134 135 sc->sc_open = 1; 136 return 0; 137 } 138 139 /*ARGSUSED*/ 140 int 141 m41t00_close(dev_t dev, int flag, int fmt, struct lwp *l) 142 { 143 struct m41t00_softc *sc; 144 145 if ((sc = device_lookup(&m41trtc_cd, minor(dev))) == NULL) 146 return ENXIO; 147 148 sc->sc_open = 0; 149 return 0; 150 } 151 152 /*ARGSUSED*/ 153 int 154 m41t00_read(dev_t dev, struct uio *uio, int flags) 155 { 156 struct m41t00_softc *sc; 157 u_int8_t ch, cmdbuf[1]; 158 int a, error; 159 160 if ((sc = device_lookup(&m41trtc_cd, minor(dev))) == NULL) 161 return (ENXIO); 162 163 if (uio->uio_offset >= M41T00_NBYTES) 164 return (EINVAL); 165 166 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 167 return (error); 168 169 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 170 a = (int)uio->uio_offset; 171 cmdbuf[0] = a; 172 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 173 sc->sc_address, cmdbuf, 1, 174 &ch, 1, 0)) != 0) { 175 iic_release_bus(sc->sc_tag, 0); 176 aprint_error_dev(&sc->sc_dev, "m41t00_read: read failed at 0x%x\n", a); 177 return (error); 178 } 179 if ((error = uiomove(&ch, 1, uio)) != 0) { 180 iic_release_bus(sc->sc_tag, 0); 181 return (error); 182 } 183 } 184 185 iic_release_bus(sc->sc_tag, 0); 186 187 return (0); 188 } 189 190 /*ARGSUSED*/ 191 int 192 m41t00_write(dev_t dev, struct uio *uio, int flags) 193 { 194 struct m41t00_softc *sc; 195 u_int8_t cmdbuf[2]; 196 int a, error; 197 198 if ((sc = device_lookup(&m41trtc_cd, minor(dev))) == NULL) 199 return (ENXIO); 200 201 if (uio->uio_offset >= M41T00_NBYTES) 202 return (EINVAL); 203 204 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 205 return (error); 206 207 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 208 a = (int)uio->uio_offset; 209 210 cmdbuf[0] = a; 211 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 212 break; 213 214 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 215 sc->sc_address, 216 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 217 aprint_error_dev(&sc->sc_dev, "m41t00_write: write failed at 0x%x\n", a); 218 break; 219 } 220 } 221 222 iic_release_bus(sc->sc_tag, 0); 223 224 return (error); 225 } 226 227 static int 228 m41t00_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 229 { 230 struct m41t00_softc *sc = ch->cookie; 231 struct clock_ymdhms dt; 232 233 if (m41t00_clock_read(sc, &dt) == 0) 234 return (-1); 235 236 tv->tv_sec = clock_ymdhms_to_secs(&dt); 237 tv->tv_usec = 0; 238 239 return (0); 240 } 241 242 static int 243 m41t00_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 244 { 245 struct m41t00_softc *sc = ch->cookie; 246 struct clock_ymdhms dt; 247 248 clock_secs_to_ymdhms(tv->tv_sec, &dt); 249 250 if (m41t00_clock_write(sc, &dt) == 0) 251 return (-1); 252 253 return (0); 254 } 255 256 static int m41t00_rtc_offset[] = { 257 M41T00_SEC, 258 M41T00_MIN, 259 M41T00_CENHR, 260 M41T00_DAY, 261 M41T00_DATE, 262 M41T00_MONTH, 263 M41T00_YEAR, 264 }; 265 266 static int 267 m41t00_clock_read(struct m41t00_softc *sc, struct clock_ymdhms *dt) 268 { 269 u_int8_t bcd[M41T00_NBYTES], cmdbuf[1]; 270 int i, n; 271 272 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 273 aprint_error_dev(&sc->sc_dev, "m41t00_clock_read: failed to acquire I2C bus\n"); 274 return (0); 275 } 276 277 /* Read each timekeeping register in order. */ 278 n = sizeof(m41t00_rtc_offset) / sizeof(m41t00_rtc_offset[0]); 279 for (i = 0; i < n ; i++) { 280 cmdbuf[0] = m41t00_rtc_offset[i]; 281 282 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 283 sc->sc_address, cmdbuf, 1, 284 &bcd[i], 1, I2C_F_POLL)) { 285 iic_release_bus(sc->sc_tag, I2C_F_POLL); 286 aprint_error_dev(&sc->sc_dev, "m41t00_clock_read: failed to read rtc " 287 "at 0x%x\n", 288 m41t00_rtc_offset[i]); 289 return (0); 290 } 291 } 292 293 /* Done with I2C */ 294 iic_release_bus(sc->sc_tag, I2C_F_POLL); 295 296 /* 297 * Convert the M41T00's register values into something useable 298 */ 299 dt->dt_sec = FROMBCD(bcd[M41T00_SEC] & M41T00_SEC_MASK); 300 dt->dt_min = FROMBCD(bcd[M41T00_MIN] & M41T00_MIN_MASK); 301 dt->dt_hour = FROMBCD(bcd[M41T00_CENHR] & M41T00_HOUR_MASK); 302 dt->dt_day = FROMBCD(bcd[M41T00_DATE] & M41T00_DATE_MASK); 303 dt->dt_wday = FROMBCD(bcd[M41T00_DAY] & M41T00_DAY_MASK); 304 dt->dt_mon = FROMBCD(bcd[M41T00_MONTH] & M41T00_MONTH_MASK); 305 dt->dt_year = FROMBCD(bcd[M41T00_YEAR] & M41T00_YEAR_MASK); 306 307 /* 308 * Since the m41t00 just stores 00-99, and this is 2003 as I write 309 * this comment, use 2000 as a base year 310 */ 311 dt->dt_year += 2000; 312 313 return (1); 314 } 315 316 static int 317 m41t00_clock_write(struct m41t00_softc *sc, struct clock_ymdhms *dt) 318 { 319 uint8_t bcd[M41T00_DATE_BYTES], cmdbuf[2]; 320 uint8_t init_seconds, final_seconds; 321 int i; 322 323 /* 324 * Convert our time representation into something the MAX6900 325 * can understand. 326 */ 327 bcd[M41T00_SEC] = TOBCD(dt->dt_sec); 328 bcd[M41T00_MIN] = TOBCD(dt->dt_min); 329 bcd[M41T00_CENHR] = TOBCD(dt->dt_hour); 330 bcd[M41T00_DATE] = TOBCD(dt->dt_day); 331 bcd[M41T00_DAY] = TOBCD(dt->dt_wday); 332 bcd[M41T00_MONTH] = TOBCD(dt->dt_mon); 333 bcd[M41T00_YEAR] = TOBCD(dt->dt_year % 100); 334 335 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 336 aprint_error_dev(&sc->sc_dev, "m41t00_clock_write: failed to acquire I2C bus\n"); 337 return (0); 338 } 339 340 /* 341 * The MAX6900 RTC manual recommends ensuring "atomicity" of 342 * a non-burst write by: 343 * 344 * - writing SECONDS 345 * - reading back SECONDS, remembering it as "initial seconds" 346 * - write the remaing RTC registers 347 * - read back SECONDS as "final seconds" 348 * - if "initial seconds" == 59, ensure "final seconds" == 59 349 * - else, ensure "final seconds" is no more than one second 350 * beyond "initial seconds". 351 * 352 * This sounds reasonable for the M41T00, too. 353 */ 354 again: 355 cmdbuf[0] = M41T00_SEC; 356 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 357 cmdbuf, 1, &bcd[M41T00_SEC], 1, I2C_F_POLL)) { 358 iic_release_bus(sc->sc_tag, I2C_F_POLL); 359 aprint_error_dev(&sc->sc_dev, "m41t00_clock_write: failed to write SECONDS\n"); 360 return (0); 361 } 362 363 cmdbuf[0] = M41T00_SEC; 364 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 365 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 366 iic_release_bus(sc->sc_tag, I2C_F_POLL); 367 aprint_error_dev(&sc->sc_dev, "m41t00_clock_write: failed to read " 368 "INITIAL SECONDS\n"); 369 return (0); 370 } 371 init_seconds = FROMBCD(init_seconds & M41T00_SEC_MASK); 372 373 for (i = 1; i < M41T00_DATE_BYTES; i++) { 374 cmdbuf[0] = m41t00_rtc_offset[i]; 375 if (iic_exec(sc->sc_tag, 376 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 377 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 378 iic_release_bus(sc->sc_tag, I2C_F_POLL); 379 aprint_error_dev(&sc->sc_dev, "m41t00_clock_write: failed to write rtc " 380 " at 0x%x\n", 381 m41t00_rtc_offset[i]); 382 return (0); 383 } 384 } 385 386 cmdbuf[0] = M41T00_SEC; 387 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 388 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 389 iic_release_bus(sc->sc_tag, I2C_F_POLL); 390 aprint_error_dev(&sc->sc_dev, "m41t00_clock_write: failed to read " 391 "FINAL SECONDS\n"); 392 393 if ((init_seconds != final_seconds) && 394 (((init_seconds + 1) % 60) != final_seconds)) { 395 #if 1 396 printf("%s: m41t00_clock_write: init %d, final %d, try again\n", 397 device_xname(&sc->sc_dev), init_seconds, final_seconds); 398 #endif 399 goto again; 400 } 401 402 iic_release_bus(sc->sc_tag, I2C_F_POLL); 403 404 return (1); 405 } 406
Indexes created Thu Sep 25 15:09:46 GMT 2025