m41t00.c revision 1.17
1 /* $NetBSD: m41t00.c,v 1.17 2014/03/16 05:20:27 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41t00.c,v 1.17 2014/03/16 05:20:27 dholland Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <dev/i2c/i2cvar.h> 56 #include <dev/i2c/m41t00reg.h> 57 58 struct m41t00_softc { 59 device_t sc_dev; 60 i2c_tag_t sc_tag; 61 int sc_address; 62 int sc_open; 63 struct todr_chip_handle sc_todr; 64 }; 65 66 static int m41t00_match(device_t, cfdata_t, void *); 67 static void m41t00_attach(device_t, device_t, void *); 68 69 CFATTACH_DECL_NEW(m41trtc, sizeof(struct m41t00_softc), 70 m41t00_match, m41t00_attach, NULL, NULL); 71 extern struct cfdriver m41trtc_cd; 72 73 dev_type_open(m41t00_open); 74 dev_type_close(m41t00_close); 75 dev_type_read(m41t00_read); 76 dev_type_write(m41t00_write); 77 78 const struct cdevsw m41t00_cdevsw = { 79 .d_open = m41t00_open, 80 .d_close = m41t00_close, 81 .d_read = m41t00_read, 82 .d_write = m41t00_write, 83 .d_ioctl = noioctl, 84 .d_stop = nostop, 85 .d_tty = notty, 86 .d_poll = nopoll, 87 .d_mmap = nommap, 88 .d_kqfilter = nokqfilter, 89 .d_flag = D_OTHER 90 }; 91 92 static int m41t00_clock_read(struct m41t00_softc *, struct clock_ymdhms *); 93 static int m41t00_clock_write(struct m41t00_softc *, struct clock_ymdhms *); 94 static int m41t00_gettime(struct todr_chip_handle *, struct timeval *); 95 static int m41t00_settime(struct todr_chip_handle *, struct timeval *); 96 97 int 98 m41t00_match(device_t parent, cfdata_t cf, void *aux) 99 { 100 struct i2c_attach_args *ia = aux; 101 102 if (ia->ia_addr == M41T00_ADDR) { 103 return 1; 104 } 105 106 return 0; 107 } 108 109 void 110 m41t00_attach(device_t parent, device_t self, void *aux) 111 { 112 struct m41t00_softc *sc = device_private(self); 113 struct i2c_attach_args *ia = aux; 114 115 sc->sc_tag = ia->ia_tag; 116 sc->sc_address = ia->ia_addr; 117 sc->sc_dev = self; 118 119 aprint_naive(": Real-time Clock\n"); 120 aprint_normal(": M41T00 Real-time Clock\n"); 121 122 sc->sc_open = 0; 123 sc->sc_todr.cookie = sc; 124 sc->sc_todr.todr_gettime = m41t00_gettime; 125 sc->sc_todr.todr_settime = m41t00_settime; 126 sc->sc_todr.todr_setwen = NULL; 127 128 todr_attach(&sc->sc_todr); 129 } 130 131 /*ARGSUSED*/ 132 int 133 m41t00_open(dev_t dev, int flag, int fmt, struct lwp *l) 134 { 135 struct m41t00_softc *sc; 136 137 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 138 return ENXIO; 139 140 /* XXX: Locking */ 141 142 if (sc->sc_open) 143 return EBUSY; 144 145 sc->sc_open = 1; 146 return 0; 147 } 148 149 /*ARGSUSED*/ 150 int 151 m41t00_close(dev_t dev, int flag, int fmt, struct lwp *l) 152 { 153 struct m41t00_softc *sc; 154 155 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 156 return ENXIO; 157 158 sc->sc_open = 0; 159 return 0; 160 } 161 162 /*ARGSUSED*/ 163 int 164 m41t00_read(dev_t dev, struct uio *uio, int flags) 165 { 166 struct m41t00_softc *sc; 167 u_int8_t ch, cmdbuf[1]; 168 int a, error; 169 170 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 171 return ENXIO; 172 173 if (uio->uio_offset >= M41T00_NBYTES) 174 return EINVAL; 175 176 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 177 return error; 178 179 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 180 a = (int)uio->uio_offset; 181 cmdbuf[0] = a; 182 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 183 sc->sc_address, cmdbuf, 1, 184 &ch, 1, 0)) != 0) { 185 iic_release_bus(sc->sc_tag, 0); 186 aprint_error_dev(sc->sc_dev, 187 "m41t00_read: read failed at 0x%x\n", a); 188 return error; 189 } 190 if ((error = uiomove(&ch, 1, uio)) != 0) { 191 iic_release_bus(sc->sc_tag, 0); 192 return error; 193 } 194 } 195 196 iic_release_bus(sc->sc_tag, 0); 197 198 return 0; 199 } 200 201 /*ARGSUSED*/ 202 int 203 m41t00_write(dev_t dev, struct uio *uio, int flags) 204 { 205 struct m41t00_softc *sc; 206 u_int8_t cmdbuf[2]; 207 int a, error; 208 209 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 210 return ENXIO; 211 212 if (uio->uio_offset >= M41T00_NBYTES) 213 return EINVAL; 214 215 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 216 return error; 217 218 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 219 a = (int)uio->uio_offset; 220 221 cmdbuf[0] = a; 222 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 223 break; 224 225 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 226 sc->sc_address, 227 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 228 aprint_error_dev(sc->sc_dev, 229 "m41t00_write: write failed at 0x%x\n", a); 230 break; 231 } 232 } 233 234 iic_release_bus(sc->sc_tag, 0); 235 236 return error; 237 } 238 239 static int 240 m41t00_gettime(struct todr_chip_handle *ch, struct timeval *tv) 241 { 242 struct m41t00_softc *sc = ch->cookie; 243 struct clock_ymdhms dt; 244 245 if (m41t00_clock_read(sc, &dt) == 0) 246 return -1; 247 248 tv->tv_sec = clock_ymdhms_to_secs(&dt); 249 tv->tv_usec = 0; 250 251 return 0; 252 } 253 254 static int 255 m41t00_settime(struct todr_chip_handle *ch, struct timeval *tv) 256 { 257 struct m41t00_softc *sc = ch->cookie; 258 struct clock_ymdhms dt; 259 260 clock_secs_to_ymdhms(tv->tv_sec, &dt); 261 262 if (m41t00_clock_write(sc, &dt) == 0) 263 return -1; 264 265 return 0; 266 } 267 268 static int m41t00_rtc_offset[] = { 269 M41T00_SEC, 270 M41T00_MIN, 271 M41T00_CENHR, 272 M41T00_DAY, 273 M41T00_DATE, 274 M41T00_MONTH, 275 M41T00_YEAR, 276 }; 277 278 static int 279 m41t00_clock_read(struct m41t00_softc *sc, struct clock_ymdhms *dt) 280 { 281 u_int8_t bcd[M41T00_NBYTES], cmdbuf[1]; 282 int i, n; 283 284 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 285 aprint_error_dev(sc->sc_dev, 286 "m41t00_clock_read: failed to acquire I2C bus\n"); 287 return 0; 288 } 289 290 /* Read each timekeeping register in order. */ 291 n = sizeof(m41t00_rtc_offset) / sizeof(m41t00_rtc_offset[0]); 292 for (i = 0; i < n ; i++) { 293 cmdbuf[0] = m41t00_rtc_offset[i]; 294 295 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 296 sc->sc_address, cmdbuf, 1, 297 &bcd[i], 1, I2C_F_POLL)) { 298 iic_release_bus(sc->sc_tag, I2C_F_POLL); 299 aprint_error_dev(sc->sc_dev, 300 "m41t00_clock_read: failed to read rtc " 301 "at 0x%x\n", 302 m41t00_rtc_offset[i]); 303 return 0; 304 } 305 } 306 307 /* Done with I2C */ 308 iic_release_bus(sc->sc_tag, I2C_F_POLL); 309 310 /* 311 * Convert the M41T00's register values into something useable 312 */ 313 dt->dt_sec = FROMBCD(bcd[M41T00_SEC] & M41T00_SEC_MASK); 314 dt->dt_min = FROMBCD(bcd[M41T00_MIN] & M41T00_MIN_MASK); 315 dt->dt_hour = FROMBCD(bcd[M41T00_CENHR] & M41T00_HOUR_MASK); 316 dt->dt_day = FROMBCD(bcd[M41T00_DATE] & M41T00_DATE_MASK); 317 dt->dt_wday = FROMBCD(bcd[M41T00_DAY] & M41T00_DAY_MASK); 318 dt->dt_mon = FROMBCD(bcd[M41T00_MONTH] & M41T00_MONTH_MASK); 319 dt->dt_year = FROMBCD(bcd[M41T00_YEAR] & M41T00_YEAR_MASK); 320 321 /* 322 * Since the m41t00 just stores 00-99, and this is 2003 as I write 323 * this comment, use 2000 as a base year 324 */ 325 dt->dt_year += 2000; 326 327 return 1; 328 } 329 330 static int 331 m41t00_clock_write(struct m41t00_softc *sc, struct clock_ymdhms *dt) 332 { 333 uint8_t bcd[M41T00_DATE_BYTES], cmdbuf[2]; 334 uint8_t init_seconds, final_seconds; 335 int i; 336 337 /* 338 * Convert our time representation into something the MAX6900 339 * can understand. 340 */ 341 bcd[M41T00_SEC] = TOBCD(dt->dt_sec); 342 bcd[M41T00_MIN] = TOBCD(dt->dt_min); 343 bcd[M41T00_CENHR] = TOBCD(dt->dt_hour); 344 bcd[M41T00_DATE] = TOBCD(dt->dt_day); 345 bcd[M41T00_DAY] = TOBCD(dt->dt_wday); 346 bcd[M41T00_MONTH] = TOBCD(dt->dt_mon); 347 bcd[M41T00_YEAR] = TOBCD(dt->dt_year % 100); 348 349 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 350 aprint_error_dev(sc->sc_dev, 351 "m41t00_clock_write: failed to acquire I2C bus\n"); 352 return 0; 353 } 354 355 /* 356 * The MAX6900 RTC manual recommends ensuring "atomicity" of 357 * a non-burst write by: 358 * 359 * - writing SECONDS 360 * - reading back SECONDS, remembering it as "initial seconds" 361 * - write the remaing RTC registers 362 * - read back SECONDS as "final seconds" 363 * - if "initial seconds" == 59, ensure "final seconds" == 59 364 * - else, ensure "final seconds" is no more than one second 365 * beyond "initial seconds". 366 * 367 * This sounds reasonable for the M41T00, too. 368 */ 369 again: 370 cmdbuf[0] = M41T00_SEC; 371 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 372 cmdbuf, 1, &bcd[M41T00_SEC], 1, I2C_F_POLL)) { 373 iic_release_bus(sc->sc_tag, I2C_F_POLL); 374 aprint_error_dev(sc->sc_dev, 375 "m41t00_clock_write: failed to write SECONDS\n"); 376 return 0; 377 } 378 379 cmdbuf[0] = M41T00_SEC; 380 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 381 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 382 iic_release_bus(sc->sc_tag, I2C_F_POLL); 383 aprint_error_dev(sc->sc_dev, 384 "m41t00_clock_write: failed to read " 385 "INITIAL SECONDS\n"); 386 return 0; 387 } 388 init_seconds = FROMBCD(init_seconds & M41T00_SEC_MASK); 389 390 for (i = 1; i < M41T00_DATE_BYTES; i++) { 391 cmdbuf[0] = m41t00_rtc_offset[i]; 392 if (iic_exec(sc->sc_tag, 393 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 394 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 395 iic_release_bus(sc->sc_tag, I2C_F_POLL); 396 aprint_error_dev(sc->sc_dev, 397 "m41t00_clock_write: failed to write rtc " 398 " at 0x%x\n", 399 m41t00_rtc_offset[i]); 400 return 0; 401 } 402 } 403 404 cmdbuf[0] = M41T00_SEC; 405 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 406 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 407 iic_release_bus(sc->sc_tag, I2C_F_POLL); 408 aprint_error_dev(sc->sc_dev, 409 "m41t00_clock_write: failed to read " 410 "FINAL SECONDS\n"); 411 return 0; 412 } 413 final_seconds = FROMBCD(final_seconds & M41T00_SEC_MASK); 414 415 if ((init_seconds != final_seconds) && 416 (((init_seconds + 1) % 60) != final_seconds)) { 417 #if 1 418 printf("%s: m41t00_clock_write: init %d, final %d, try again\n", 419 device_xname(sc->sc_dev), init_seconds, final_seconds); 420 #endif 421 goto again; 422 } 423 424 iic_release_bus(sc->sc_tag, I2C_F_POLL); 425 426 return 1; 427 } 428
Indexes created Fri Sep 26 08:10:20 GMT 2025