m41t00.c revision 1.21
1 /* $NetBSD: m41t00.c,v 1.21 2018/06/16 21:22:13 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41t00.c,v 1.21 2018/06/16 21:22:13 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <dev/i2c/i2cvar.h> 56 #include <dev/i2c/m41t00reg.h> 57 58 #include "ioconf.h" 59 60 struct m41t00_softc { 61 device_t sc_dev; 62 i2c_tag_t sc_tag; 63 int sc_address; 64 int sc_open; 65 struct todr_chip_handle sc_todr; 66 }; 67 68 static int m41t00_match(device_t, cfdata_t, void *); 69 static void m41t00_attach(device_t, device_t, void *); 70 71 CFATTACH_DECL_NEW(m41trtc, sizeof(struct m41t00_softc), 72 m41t00_match, m41t00_attach, NULL, NULL); 73 74 dev_type_open(m41t00_open); 75 dev_type_close(m41t00_close); 76 dev_type_read(m41t00_read); 77 dev_type_write(m41t00_write); 78 79 const struct cdevsw m41t00_cdevsw = { 80 .d_open = m41t00_open, 81 .d_close = m41t00_close, 82 .d_read = m41t00_read, 83 .d_write = m41t00_write, 84 .d_ioctl = noioctl, 85 .d_stop = nostop, 86 .d_tty = notty, 87 .d_poll = nopoll, 88 .d_mmap = nommap, 89 .d_kqfilter = nokqfilter, 90 .d_discard = nodiscard, 91 .d_flag = D_OTHER 92 }; 93 94 static int m41t00_clock_read(struct m41t00_softc *, struct clock_ymdhms *); 95 static int m41t00_clock_write(struct m41t00_softc *, struct clock_ymdhms *); 96 static int m41t00_gettime(struct todr_chip_handle *, struct timeval *); 97 static int m41t00_settime(struct todr_chip_handle *, struct timeval *); 98 99 int 100 m41t00_match(device_t parent, cfdata_t cf, void *aux) 101 { 102 struct i2c_attach_args *ia = aux; 103 104 if (ia->ia_addr == M41T00_ADDR) { 105 return I2C_MATCH_ADDRESS_ONLY; 106 } 107 108 return 0; 109 } 110 111 void 112 m41t00_attach(device_t parent, device_t self, void *aux) 113 { 114 struct m41t00_softc *sc = device_private(self); 115 struct i2c_attach_args *ia = aux; 116 117 sc->sc_tag = ia->ia_tag; 118 sc->sc_address = ia->ia_addr; 119 sc->sc_dev = self; 120 121 aprint_naive(": Real-time Clock\n"); 122 aprint_normal(": M41T00 Real-time Clock\n"); 123 124 sc->sc_open = 0; 125 sc->sc_todr.cookie = sc; 126 sc->sc_todr.todr_gettime = m41t00_gettime; 127 sc->sc_todr.todr_settime = m41t00_settime; 128 sc->sc_todr.todr_setwen = NULL; 129 130 todr_attach(&sc->sc_todr); 131 } 132 133 /*ARGSUSED*/ 134 int 135 m41t00_open(dev_t dev, int flag, int fmt, struct lwp *l) 136 { 137 struct m41t00_softc *sc; 138 139 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 140 return ENXIO; 141 142 /* XXX: Locking */ 143 144 if (sc->sc_open) 145 return EBUSY; 146 147 sc->sc_open = 1; 148 return 0; 149 } 150 151 /*ARGSUSED*/ 152 int 153 m41t00_close(dev_t dev, int flag, int fmt, struct lwp *l) 154 { 155 struct m41t00_softc *sc; 156 157 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 158 return ENXIO; 159 160 sc->sc_open = 0; 161 return 0; 162 } 163 164 /*ARGSUSED*/ 165 int 166 m41t00_read(dev_t dev, struct uio *uio, int flags) 167 { 168 struct m41t00_softc *sc; 169 u_int8_t ch, cmdbuf[1]; 170 int a, error; 171 172 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 173 return ENXIO; 174 175 if (uio->uio_offset >= M41T00_NBYTES) 176 return EINVAL; 177 178 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 179 return error; 180 181 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 182 a = (int)uio->uio_offset; 183 cmdbuf[0] = a; 184 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 185 sc->sc_address, cmdbuf, 1, 186 &ch, 1, 0)) != 0) { 187 iic_release_bus(sc->sc_tag, 0); 188 aprint_error_dev(sc->sc_dev, 189 "m41t00_read: read failed at 0x%x\n", a); 190 return error; 191 } 192 if ((error = uiomove(&ch, 1, uio)) != 0) { 193 iic_release_bus(sc->sc_tag, 0); 194 return error; 195 } 196 } 197 198 iic_release_bus(sc->sc_tag, 0); 199 200 return 0; 201 } 202 203 /*ARGSUSED*/ 204 int 205 m41t00_write(dev_t dev, struct uio *uio, int flags) 206 { 207 struct m41t00_softc *sc; 208 u_int8_t cmdbuf[2]; 209 int a, error; 210 211 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 212 return ENXIO; 213 214 if (uio->uio_offset >= M41T00_NBYTES) 215 return EINVAL; 216 217 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 218 return error; 219 220 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 221 a = (int)uio->uio_offset; 222 223 cmdbuf[0] = a; 224 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 225 break; 226 227 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 228 sc->sc_address, 229 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 230 aprint_error_dev(sc->sc_dev, 231 "m41t00_write: write failed at 0x%x\n", a); 232 break; 233 } 234 } 235 236 iic_release_bus(sc->sc_tag, 0); 237 238 return error; 239 } 240 241 static int 242 m41t00_gettime(struct todr_chip_handle *ch, struct timeval *tv) 243 { 244 struct m41t00_softc *sc = ch->cookie; 245 struct clock_ymdhms dt; 246 247 if (m41t00_clock_read(sc, &dt) == 0) 248 return -1; 249 250 tv->tv_sec = clock_ymdhms_to_secs(&dt); 251 tv->tv_usec = 0; 252 253 return 0; 254 } 255 256 static int 257 m41t00_settime(struct todr_chip_handle *ch, struct timeval *tv) 258 { 259 struct m41t00_softc *sc = ch->cookie; 260 struct clock_ymdhms dt; 261 262 clock_secs_to_ymdhms(tv->tv_sec, &dt); 263 264 if (m41t00_clock_write(sc, &dt) == 0) 265 return -1; 266 267 return 0; 268 } 269 270 static int m41t00_rtc_offset[] = { 271 M41T00_SEC, 272 M41T00_MIN, 273 M41T00_CENHR, 274 M41T00_DAY, 275 M41T00_DATE, 276 M41T00_MONTH, 277 M41T00_YEAR, 278 }; 279 280 static int 281 m41t00_clock_read(struct m41t00_softc *sc, struct clock_ymdhms *dt) 282 { 283 u_int8_t bcd[M41T00_NBYTES], cmdbuf[1]; 284 int i, n; 285 286 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 287 aprint_error_dev(sc->sc_dev, 288 "m41t00_clock_read: failed to acquire I2C bus\n"); 289 return 0; 290 } 291 292 /* Read each timekeeping register in order. */ 293 n = sizeof(m41t00_rtc_offset) / sizeof(m41t00_rtc_offset[0]); 294 for (i = 0; i < n ; i++) { 295 cmdbuf[0] = m41t00_rtc_offset[i]; 296 297 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 298 sc->sc_address, cmdbuf, 1, 299 &bcd[i], 1, I2C_F_POLL)) { 300 iic_release_bus(sc->sc_tag, I2C_F_POLL); 301 aprint_error_dev(sc->sc_dev, 302 "m41t00_clock_read: failed to read rtc " 303 "at 0x%x\n", 304 m41t00_rtc_offset[i]); 305 return 0; 306 } 307 } 308 309 /* Done with I2C */ 310 iic_release_bus(sc->sc_tag, I2C_F_POLL); 311 312 /* 313 * Convert the M41T00's register values into something useable 314 */ 315 dt->dt_sec = bcdtobin(bcd[M41T00_SEC] & M41T00_SEC_MASK); 316 dt->dt_min = bcdtobin(bcd[M41T00_MIN] & M41T00_MIN_MASK); 317 dt->dt_hour = bcdtobin(bcd[M41T00_CENHR] & M41T00_HOUR_MASK); 318 dt->dt_day = bcdtobin(bcd[M41T00_DATE] & M41T00_DATE_MASK); 319 dt->dt_wday = bcdtobin(bcd[M41T00_DAY] & M41T00_DAY_MASK); 320 dt->dt_mon = bcdtobin(bcd[M41T00_MONTH] & M41T00_MONTH_MASK); 321 dt->dt_year = bcdtobin(bcd[M41T00_YEAR] & M41T00_YEAR_MASK); 322 323 /* 324 * Since the m41t00 just stores 00-99, and this is 2003 as I write 325 * this comment, use 2000 as a base year 326 */ 327 dt->dt_year += 2000; 328 329 return 1; 330 } 331 332 static int 333 m41t00_clock_write(struct m41t00_softc *sc, struct clock_ymdhms *dt) 334 { 335 uint8_t bcd[M41T00_DATE_BYTES], cmdbuf[2]; 336 uint8_t init_seconds, final_seconds; 337 int i; 338 339 /* 340 * Convert our time representation into something the MAX6900 341 * can understand. 342 */ 343 bcd[M41T00_SEC] = bintobcd(dt->dt_sec); 344 bcd[M41T00_MIN] = bintobcd(dt->dt_min); 345 bcd[M41T00_CENHR] = bintobcd(dt->dt_hour); 346 bcd[M41T00_DATE] = bintobcd(dt->dt_day); 347 bcd[M41T00_DAY] = bintobcd(dt->dt_wday); 348 bcd[M41T00_MONTH] = bintobcd(dt->dt_mon); 349 bcd[M41T00_YEAR] = bintobcd(dt->dt_year % 100); 350 351 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 352 aprint_error_dev(sc->sc_dev, 353 "m41t00_clock_write: failed to acquire I2C bus\n"); 354 return 0; 355 } 356 357 /* 358 * The MAX6900 RTC manual recommends ensuring "atomicity" of 359 * a non-burst write by: 360 * 361 * - writing SECONDS 362 * - reading back SECONDS, remembering it as "initial seconds" 363 * - write the remaing RTC registers 364 * - read back SECONDS as "final seconds" 365 * - if "initial seconds" == 59, ensure "final seconds" == 59 366 * - else, ensure "final seconds" is no more than one second 367 * beyond "initial seconds". 368 * 369 * This sounds reasonable for the M41T00, too. 370 */ 371 again: 372 cmdbuf[0] = M41T00_SEC; 373 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 374 cmdbuf, 1, &bcd[M41T00_SEC], 1, I2C_F_POLL)) { 375 iic_release_bus(sc->sc_tag, I2C_F_POLL); 376 aprint_error_dev(sc->sc_dev, 377 "m41t00_clock_write: failed to write SECONDS\n"); 378 return 0; 379 } 380 381 cmdbuf[0] = M41T00_SEC; 382 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 383 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 384 iic_release_bus(sc->sc_tag, I2C_F_POLL); 385 aprint_error_dev(sc->sc_dev, 386 "m41t00_clock_write: failed to read " 387 "INITIAL SECONDS\n"); 388 return 0; 389 } 390 init_seconds = bcdtobin(init_seconds & M41T00_SEC_MASK); 391 392 for (i = 1; i < M41T00_DATE_BYTES; i++) { 393 cmdbuf[0] = m41t00_rtc_offset[i]; 394 if (iic_exec(sc->sc_tag, 395 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 396 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 397 iic_release_bus(sc->sc_tag, I2C_F_POLL); 398 aprint_error_dev(sc->sc_dev, 399 "m41t00_clock_write: failed to write rtc " 400 " at 0x%x\n", 401 m41t00_rtc_offset[i]); 402 return 0; 403 } 404 } 405 406 cmdbuf[0] = M41T00_SEC; 407 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 408 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 409 iic_release_bus(sc->sc_tag, I2C_F_POLL); 410 aprint_error_dev(sc->sc_dev, 411 "m41t00_clock_write: failed to read " 412 "FINAL SECONDS\n"); 413 return 0; 414 } 415 final_seconds = bcdtobin(final_seconds & M41T00_SEC_MASK); 416 417 if ((init_seconds != final_seconds) && 418 (((init_seconds + 1) % 60) != final_seconds)) { 419 #if 1 420 printf("%s: m41t00_clock_write: init %d, final %d, try again\n", 421 device_xname(sc->sc_dev), init_seconds, final_seconds); 422 #endif 423 goto again; 424 } 425 426 iic_release_bus(sc->sc_tag, I2C_F_POLL); 427 428 return 1; 429 } 430
Indexes created Thu Sep 25 08:09:54 GMT 2025