m41t00.c revision 1.26
1 /* $NetBSD: m41t00.c,v 1.26 2025/09/07 21:45:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: m41t00.c,v 1.26 2025/09/07 21:45:15 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/proc.h> 49 #include <sys/event.h> 50 51 #include <sys/bus.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <dev/i2c/i2cvar.h> 56 #include <dev/i2c/m41t00reg.h> 57 58 #include "ioconf.h" 59 60 struct m41t00_softc { 61 device_t sc_dev; 62 i2c_tag_t sc_tag; 63 int sc_address; 64 int sc_open; 65 struct todr_chip_handle sc_todr; 66 }; 67 68 static int m41t00_match(device_t, cfdata_t, void *); 69 static void m41t00_attach(device_t, device_t, void *); 70 71 CFATTACH_DECL_NEW(m41trtc, sizeof(struct m41t00_softc), 72 m41t00_match, m41t00_attach, NULL, NULL); 73 74 dev_type_open(m41t00_open); 75 dev_type_close(m41t00_close); 76 dev_type_read(m41t00_read); 77 dev_type_write(m41t00_write); 78 79 const struct cdevsw m41t00_cdevsw = { 80 .d_open = m41t00_open, 81 .d_close = m41t00_close, 82 .d_read = m41t00_read, 83 .d_write = m41t00_write, 84 .d_ioctl = noioctl, 85 .d_stop = nostop, 86 .d_tty = notty, 87 .d_poll = nopoll, 88 .d_mmap = nommap, 89 .d_kqfilter = nokqfilter, 90 .d_discard = nodiscard, 91 .d_flag = D_OTHER 92 }; 93 94 static int m41t00_gettime_ymdhms(struct todr_chip_handle *, 95 struct clock_ymdhms *); 96 static int m41t00_settime_ymdhms(struct todr_chip_handle *, 97 struct clock_ymdhms *); 98 99 int 100 m41t00_match(device_t parent, cfdata_t cf, void *aux) 101 { 102 struct i2c_attach_args *ia = aux; 103 104 if (ia->ia_addr == M41T00_ADDR) { 105 return I2C_MATCH_ADDRESS_ONLY; 106 } 107 108 return 0; 109 } 110 111 void 112 m41t00_attach(device_t parent, device_t self, void *aux) 113 { 114 struct m41t00_softc *sc = device_private(self); 115 struct i2c_attach_args *ia = aux; 116 117 sc->sc_tag = ia->ia_tag; 118 sc->sc_address = ia->ia_addr; 119 sc->sc_dev = self; 120 121 aprint_naive(": Real-time Clock\n"); 122 aprint_normal(": M41T00 Real-time Clock\n"); 123 124 sc->sc_open = 0; 125 sc->sc_todr.todr_dev = self; 126 sc->sc_todr.todr_gettime_ymdhms = m41t00_gettime_ymdhms; 127 sc->sc_todr.todr_settime_ymdhms = m41t00_settime_ymdhms; 128 129 todr_attach(&sc->sc_todr); 130 } 131 132 /*ARGSUSED*/ 133 int 134 m41t00_open(dev_t dev, int flag, int fmt, struct lwp *l) 135 { 136 struct m41t00_softc *sc; 137 138 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 139 return ENXIO; 140 141 /* XXX: Locking */ 142 143 if (sc->sc_open) 144 return EBUSY; 145 146 sc->sc_open = 1; 147 return 0; 148 } 149 150 /*ARGSUSED*/ 151 int 152 m41t00_close(dev_t dev, int flag, int fmt, struct lwp *l) 153 { 154 struct m41t00_softc *sc; 155 156 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 157 return ENXIO; 158 159 sc->sc_open = 0; 160 return 0; 161 } 162 163 /*ARGSUSED*/ 164 int 165 m41t00_read(dev_t dev, struct uio *uio, int flags) 166 { 167 struct m41t00_softc *sc; 168 u_int8_t ch, cmdbuf[1]; 169 int a, error; 170 171 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 172 return ENXIO; 173 174 if (uio->uio_offset >= M41T00_NBYTES) 175 return EINVAL; 176 177 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 178 return error; 179 180 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 181 a = (int)uio->uio_offset; 182 cmdbuf[0] = a; 183 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 184 sc->sc_address, cmdbuf, 1, 185 &ch, 1, 0)) != 0) { 186 iic_release_bus(sc->sc_tag, 0); 187 aprint_error_dev(sc->sc_dev, 188 "m41t00_read: read failed at 0x%x\n", a); 189 return error; 190 } 191 if ((error = uiomove(&ch, 1, uio)) != 0) { 192 iic_release_bus(sc->sc_tag, 0); 193 return error; 194 } 195 } 196 197 iic_release_bus(sc->sc_tag, 0); 198 199 return 0; 200 } 201 202 /*ARGSUSED*/ 203 int 204 m41t00_write(dev_t dev, struct uio *uio, int flags) 205 { 206 struct m41t00_softc *sc; 207 u_int8_t cmdbuf[2]; 208 int a, error; 209 210 if ((sc = device_lookup_private(&m41trtc_cd, minor(dev))) == NULL) 211 return ENXIO; 212 213 if (uio->uio_offset >= M41T00_NBYTES) 214 return EINVAL; 215 216 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 217 return error; 218 219 while (uio->uio_resid && uio->uio_offset < M41T00_NBYTES) { 220 a = (int)uio->uio_offset; 221 222 cmdbuf[0] = a; 223 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 224 break; 225 226 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 227 sc->sc_address, 228 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 229 aprint_error_dev(sc->sc_dev, 230 "m41t00_write: write failed at 0x%x\n", a); 231 break; 232 } 233 } 234 235 iic_release_bus(sc->sc_tag, 0); 236 237 return error; 238 } 239 240 static int m41t00_rtc_offset[] = { 241 M41T00_SEC, 242 M41T00_MIN, 243 M41T00_CENHR, 244 M41T00_DAY, 245 M41T00_DATE, 246 M41T00_MONTH, 247 M41T00_YEAR, 248 }; 249 250 static int 251 m41t00_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 252 { 253 struct m41t00_softc *sc = device_private(ch->todr_dev); 254 u_int8_t bcd[M41T00_NBYTES], cmdbuf[1]; 255 int i, n, error; 256 257 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 258 aprint_error_dev(sc->sc_dev, 259 "m41t00_clock_read: failed to acquire I2C bus\n"); 260 return error; 261 } 262 263 /* Read each timekeeping register in order. */ 264 n = sizeof(m41t00_rtc_offset) / sizeof(m41t00_rtc_offset[0]); 265 for (i = 0; i < n ; i++) { 266 cmdbuf[0] = m41t00_rtc_offset[i]; 267 268 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 269 sc->sc_address, cmdbuf, 1, 270 &bcd[i], 1, 0)) != 0) { 271 iic_release_bus(sc->sc_tag, 0); 272 aprint_error_dev(sc->sc_dev, 273 "m41t00_clock_read: failed to read rtc " 274 "at 0x%x\n", 275 m41t00_rtc_offset[i]); 276 return error; 277 } 278 } 279 280 /* Done with I2C */ 281 iic_release_bus(sc->sc_tag, 0); 282 283 /* 284 * Convert the M41T00's register values into something useable 285 */ 286 dt->dt_sec = bcdtobin(bcd[M41T00_SEC] & M41T00_SEC_MASK); 287 dt->dt_min = bcdtobin(bcd[M41T00_MIN] & M41T00_MIN_MASK); 288 dt->dt_hour = bcdtobin(bcd[M41T00_CENHR] & M41T00_HOUR_MASK); 289 dt->dt_day = bcdtobin(bcd[M41T00_DATE] & M41T00_DATE_MASK); 290 dt->dt_wday = bcdtobin(bcd[M41T00_DAY] & M41T00_DAY_MASK); 291 dt->dt_mon = bcdtobin(bcd[M41T00_MONTH] & M41T00_MONTH_MASK); 292 dt->dt_year = bcdtobin(bcd[M41T00_YEAR] & M41T00_YEAR_MASK); 293 294 /* 295 * Since the m41t00 just stores 00-99, and this is 2003 as I write 296 * this comment, use 2000 as a base year 297 */ 298 dt->dt_year += 2000; 299 300 return 0; 301 } 302 303 static int 304 m41t00_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 305 { 306 struct m41t00_softc *sc = device_private(ch->todr_dev); 307 uint8_t bcd[M41T00_DATE_BYTES], cmdbuf[2]; 308 uint8_t init_seconds, final_seconds; 309 int i, error; 310 311 /* 312 * Convert our time representation into something the MAX6900 313 * can understand. 314 */ 315 bcd[M41T00_SEC] = bintobcd(dt->dt_sec); 316 bcd[M41T00_MIN] = bintobcd(dt->dt_min); 317 bcd[M41T00_CENHR] = bintobcd(dt->dt_hour); 318 bcd[M41T00_DATE] = bintobcd(dt->dt_day); 319 bcd[M41T00_DAY] = bintobcd(dt->dt_wday); 320 bcd[M41T00_MONTH] = bintobcd(dt->dt_mon); 321 bcd[M41T00_YEAR] = bintobcd(dt->dt_year % 100); 322 323 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 324 aprint_error_dev(sc->sc_dev, 325 "m41t00_clock_write: failed to acquire I2C bus\n"); 326 return error; 327 } 328 329 /* 330 * The MAX6900 RTC manual recommends ensuring "atomicity" of 331 * a non-burst write by: 332 * 333 * - writing SECONDS 334 * - reading back SECONDS, remembering it as "initial seconds" 335 * - write the remaining RTC registers 336 * - read back SECONDS as "final seconds" 337 * - if "initial seconds" == 59, ensure "final seconds" == 59 338 * - else, ensure "final seconds" is no more than one second 339 * beyond "initial seconds". 340 * 341 * This sounds reasonable for the M41T00, too. 342 */ 343 again: 344 cmdbuf[0] = M41T00_SEC; 345 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 346 sc->sc_address, cmdbuf, 1, &bcd[M41T00_SEC], 1, 347 0)) != 0) { 348 iic_release_bus(sc->sc_tag, 0); 349 aprint_error_dev(sc->sc_dev, 350 "m41t00_clock_write: failed to write SECONDS\n"); 351 return error; 352 } 353 354 cmdbuf[0] = M41T00_SEC; 355 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 356 cmdbuf, 1, &init_seconds, 1, 0)) != 0) { 357 iic_release_bus(sc->sc_tag, 0); 358 aprint_error_dev(sc->sc_dev, 359 "m41t00_clock_write: failed to read " 360 "INITIAL SECONDS\n"); 361 return error; 362 } 363 init_seconds = bcdtobin(init_seconds & M41T00_SEC_MASK); 364 365 for (i = 1; i < M41T00_DATE_BYTES; i++) { 366 cmdbuf[0] = m41t00_rtc_offset[i]; 367 if ((error = iic_exec(sc->sc_tag, 368 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 369 cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 370 iic_release_bus(sc->sc_tag, 0); 371 aprint_error_dev(sc->sc_dev, 372 "m41t00_clock_write: failed to write rtc " 373 " at 0x%x\n", 374 m41t00_rtc_offset[i]); 375 return error; 376 } 377 } 378 379 cmdbuf[0] = M41T00_SEC; 380 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 381 cmdbuf, 1, &final_seconds, 1, 0)) != 0) { 382 iic_release_bus(sc->sc_tag, 0); 383 aprint_error_dev(sc->sc_dev, 384 "m41t00_clock_write: failed to read " 385 "FINAL SECONDS\n"); 386 return error; 387 } 388 final_seconds = bcdtobin(final_seconds & M41T00_SEC_MASK); 389 390 if ((init_seconds != final_seconds) && 391 (((init_seconds + 1) % 60) != final_seconds)) { 392 #if 1 393 printf("%s: m41t00_clock_write: init %d, final %d, try again\n", 394 device_xname(sc->sc_dev), init_seconds, final_seconds); 395 #endif 396 goto again; 397 } 398 399 iic_release_bus(sc->sc_tag, 0); 400 401 return 0; 402 } 403
Indexes created Thu Sep 25 06:09:39 GMT 2025