max6900.c revision 1.12.26.1
1 /* $NetBSD: max6900.c,v 1.12.26.1 2014/05/18 17:45:37 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: max6900.c,v 1.12.26.1 2014/05/18 17:45:37 rmind Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/max6900reg.h> 54 55 struct maxrtc_softc { 56 device_t sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static int maxrtc_match(device_t, cfdata_t, void *); 64 static void maxrtc_attach(device_t, device_t, void *); 65 66 CFATTACH_DECL_NEW(maxrtc, sizeof(struct maxrtc_softc), 67 maxrtc_match, maxrtc_attach, NULL, NULL); 68 extern struct cfdriver maxrtc_cd; 69 70 dev_type_open(maxrtc_open); 71 dev_type_close(maxrtc_close); 72 dev_type_read(maxrtc_read); 73 dev_type_write(maxrtc_write); 74 75 const struct cdevsw maxrtc_cdevsw = { 76 .d_open = maxrtc_open, 77 .d_close = maxrtc_close, 78 .d_read = maxrtc_read, 79 .d_write = maxrtc_write, 80 .d_ioctl = noioctl, 81 .d_stop = nostop, 82 .d_tty = notty, 83 .d_poll = nopoll, 84 .d_mmap = nommap, 85 .d_kqfilter = nokqfilter, 86 .d_flag = D_OTHER 87 }; 88 89 static int maxrtc_clock_read(struct maxrtc_softc *, struct clock_ymdhms *); 90 static int maxrtc_clock_write(struct maxrtc_softc *, struct clock_ymdhms *); 91 static int maxrtc_gettime(struct todr_chip_handle *, struct timeval *); 92 static int maxrtc_settime(struct todr_chip_handle *, struct timeval *); 93 94 int 95 maxrtc_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct i2c_attach_args *ia = aux; 98 99 if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR) 100 return (1); 101 102 return (0); 103 } 104 105 void 106 maxrtc_attach(device_t parent, device_t self, void *aux) 107 { 108 struct maxrtc_softc *sc = device_private(self); 109 struct i2c_attach_args *ia = aux; 110 111 sc->sc_tag = ia->ia_tag; 112 sc->sc_address = ia->ia_addr; 113 sc->sc_dev = self; 114 115 aprint_naive(": Real-time Clock/NVRAM\n"); 116 aprint_normal(": MAX6900 Real-time Clock/NVRAM\n"); 117 118 sc->sc_open = 0; 119 120 sc->sc_todr.cookie = sc; 121 sc->sc_todr.todr_gettime = maxrtc_gettime; 122 sc->sc_todr.todr_settime = maxrtc_settime; 123 sc->sc_todr.todr_setwen = NULL; 124 125 todr_attach(&sc->sc_todr); 126 } 127 128 /*ARGSUSED*/ 129 int 130 maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 131 { 132 struct maxrtc_softc *sc; 133 134 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 135 return (ENXIO); 136 137 /* XXX: Locking */ 138 139 if (sc->sc_open) 140 return (EBUSY); 141 142 sc->sc_open = 1; 143 return (0); 144 } 145 146 /*ARGSUSED*/ 147 int 148 maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 149 { 150 struct maxrtc_softc *sc; 151 152 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 153 return (ENXIO); 154 155 sc->sc_open = 0; 156 return (0); 157 } 158 159 /*ARGSUSED*/ 160 int 161 maxrtc_read(dev_t dev, struct uio *uio, int flags) 162 { 163 struct maxrtc_softc *sc; 164 u_int8_t ch, cmdbuf[1]; 165 int a, error; 166 167 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 168 return (ENXIO); 169 170 if (uio->uio_offset >= MAX6900_RAM_BYTES) 171 return (EINVAL); 172 173 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 174 return (error); 175 176 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 177 a = (int)uio->uio_offset; 178 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ; 179 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 180 sc->sc_address, cmdbuf, 1, 181 &ch, 1, 0)) != 0) { 182 iic_release_bus(sc->sc_tag, 0); 183 aprint_error_dev(sc->sc_dev, 184 "maxrtc_read: read failed at 0x%x\n", a); 185 return (error); 186 } 187 if ((error = uiomove(&ch, 1, uio)) != 0) { 188 iic_release_bus(sc->sc_tag, 0); 189 return (error); 190 } 191 } 192 193 iic_release_bus(sc->sc_tag, 0); 194 195 return (0); 196 } 197 198 /*ARGSUSED*/ 199 int 200 maxrtc_write(dev_t dev, struct uio *uio, int flags) 201 { 202 struct maxrtc_softc *sc; 203 u_int8_t cmdbuf[2]; 204 int a, error, sverror; 205 206 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL) 207 return (ENXIO); 208 209 if (uio->uio_offset >= MAX6900_RAM_BYTES) 210 return (EINVAL); 211 212 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 213 return (error); 214 215 /* Start by clearing the control register's write-protect bit. */ 216 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 217 cmdbuf[1] = 0; 218 219 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 220 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 221 iic_release_bus(sc->sc_tag, 0); 222 aprint_error_dev(sc->sc_dev, 223 "maxrtc_write: failed to clear WP bit\n"); 224 return (error); 225 } 226 227 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 228 a = (int)uio->uio_offset; 229 230 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE; 231 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 232 break; 233 234 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 235 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 236 aprint_error_dev(sc->sc_dev, 237 "maxrtc_write: write failed at 0x%x\n", a); 238 break; 239 } 240 } 241 242 /* Set the write-protect bit again. */ 243 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 244 cmdbuf[1] = MAX6900_CONTROL_WP; 245 246 sverror = error; 247 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 248 sc->sc_address, cmdbuf, 1, 249 &cmdbuf[1], 1, 0)) != 0) { 250 if (sverror != 0) 251 error = sverror; 252 aprint_error_dev(sc->sc_dev, 253 "maxrtc_write: failed to set WP bit\n"); 254 } 255 256 iic_release_bus(sc->sc_tag, 0); 257 258 return (error); 259 } 260 261 static int 262 maxrtc_gettime(struct todr_chip_handle *ch, struct timeval *tv) 263 { 264 struct maxrtc_softc *sc = ch->cookie; 265 struct clock_ymdhms dt; 266 267 if (maxrtc_clock_read(sc, &dt) == 0) 268 return (-1); 269 270 tv->tv_sec = clock_ymdhms_to_secs(&dt); 271 tv->tv_usec = 0; 272 273 return (0); 274 } 275 276 static int 277 maxrtc_settime(struct todr_chip_handle *ch, struct timeval *tv) 278 { 279 struct maxrtc_softc *sc = ch->cookie; 280 struct clock_ymdhms dt; 281 282 clock_secs_to_ymdhms(tv->tv_sec, &dt); 283 284 if (maxrtc_clock_write(sc, &dt) == 0) 285 return (-1); 286 287 return (0); 288 } 289 290 /* 291 * While the MAX6900 has a nice Clock Burst Read/Write command, 292 * we can't use it, since some I2C controllers do not support 293 * anything other than single-byte transfers. 294 */ 295 static int max6900_rtc_offset[] = { 296 MAX6900_REG_SECOND, 297 MAX6900_REG_MINUTE, 298 MAX6900_REG_HOUR, 299 MAX6900_REG_DATE, 300 MAX6900_REG_MONTH, 301 MAX6900_REG_DAY, 302 MAX6900_REG_YEAR, 303 MAX6900_REG_CENTURY, /* control, if burst */ 304 }; 305 306 static int 307 maxrtc_clock_read(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 308 { 309 u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1]; 310 int i; 311 312 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 313 aprint_error_dev(sc->sc_dev, 314 "maxrtc_clock_read: failed to acquire I2C bus\n"); 315 return (0); 316 } 317 318 /* Read each timekeeping register in order. */ 319 for (i = 0; i < MAX6900_BURST_LEN; i++) { 320 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ; 321 322 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 323 sc->sc_address, cmdbuf, 1, 324 &bcd[i], 1, I2C_F_POLL)) { 325 iic_release_bus(sc->sc_tag, I2C_F_POLL); 326 aprint_error_dev(sc->sc_dev, 327 "maxrtc_clock_read: failed to read rtc " 328 "at 0x%x\n", 329 max6900_rtc_offset[i]); 330 return (0); 331 } 332 } 333 334 /* Done with I2C */ 335 iic_release_bus(sc->sc_tag, I2C_F_POLL); 336 337 /* 338 * Convert the MAX6900's register values into something useable 339 */ 340 dt->dt_sec = FROMBCD(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK); 341 dt->dt_min = FROMBCD(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK); 342 343 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) { 344 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 345 MAX6900_HOUR_12MASK); 346 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM) 347 dt->dt_hour += 12; 348 } else { 349 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 350 MAX6900_HOUR_24MASK); 351 } 352 353 dt->dt_day = FROMBCD(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK); 354 dt->dt_mon = FROMBCD(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK); 355 dt->dt_year = FROMBCD(bcd[MAX6900_BURST_YEAR]); 356 /* century in the burst control slot */ 357 dt->dt_year += (int)FROMBCD(bcd[MAX6900_BURST_CONTROL]) * 100; 358 359 return (1); 360 } 361 362 static int 363 maxrtc_clock_write(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 364 { 365 uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2]; 366 uint8_t init_seconds, final_seconds; 367 int i; 368 369 /* 370 * Convert our time representation into something the MAX6900 371 * can understand. 372 */ 373 bcd[MAX6900_BURST_SECOND] = TOBCD(dt->dt_sec); 374 bcd[MAX6900_BURST_MINUTE] = TOBCD(dt->dt_min); 375 bcd[MAX6900_BURST_HOUR] = TOBCD(dt->dt_hour) & MAX6900_HOUR_24MASK; 376 bcd[MAX6900_BURST_DATE] = TOBCD(dt->dt_day); 377 bcd[MAX6900_BURST_WDAY] = TOBCD(dt->dt_wday); 378 bcd[MAX6900_BURST_MONTH] = TOBCD(dt->dt_mon); 379 bcd[MAX6900_BURST_YEAR] = TOBCD(dt->dt_year % 100); 380 /* century in control slot */ 381 bcd[MAX6900_BURST_CONTROL] = TOBCD(dt->dt_year / 100); 382 383 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 384 aprint_error_dev(sc->sc_dev, 385 "maxrtc_clock_write: failed to acquire I2C bus\n"); 386 return (0); 387 } 388 389 /* Start by clearing the control register's write-protect bit. */ 390 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 391 cmdbuf[1] = 0; 392 393 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 394 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 395 iic_release_bus(sc->sc_tag, I2C_F_POLL); 396 aprint_error_dev(sc->sc_dev, 397 "maxrtc_clock_write: failed to clear WP bit\n"); 398 return (0); 399 } 400 401 /* 402 * The MAX6900 RTC manual recommends ensuring "atomicity" of 403 * a non-burst write by: 404 * 405 * - writing SECONDS 406 * - reading back SECONDS, remembering it as "initial seconds" 407 * - write the remaing RTC registers 408 * - read back SECONDS as "final seconds" 409 * - if "initial seconds" == 59, ensure "final seconds" == 59 410 * - else, ensure "final seconds" is no more than one second 411 * beyond "initial seconds". 412 */ 413 again: 414 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE; 415 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 416 cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, I2C_F_POLL)) { 417 iic_release_bus(sc->sc_tag, I2C_F_POLL); 418 aprint_error_dev(sc->sc_dev, 419 "maxrtc_clock_write: failed to write SECONDS\n"); 420 return (0); 421 } 422 423 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 424 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 425 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 426 iic_release_bus(sc->sc_tag, I2C_F_POLL); 427 aprint_error_dev(sc->sc_dev, 428 "maxrtc_clock_write: failed to read " 429 "INITIAL SECONDS\n"); 430 return (0); 431 } 432 433 for (i = 1; i < MAX6900_BURST_LEN; i++) { 434 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE; 435 if (iic_exec(sc->sc_tag, 436 i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE : 437 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 438 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 439 iic_release_bus(sc->sc_tag, I2C_F_POLL); 440 aprint_error_dev(sc->sc_dev, 441 "maxrtc_clock_write: failed to write rtc " 442 " at 0x%x\n", 443 max6900_rtc_offset[i]); 444 return (0); 445 } 446 } 447 448 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 449 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 450 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 451 iic_release_bus(sc->sc_tag, I2C_F_POLL); 452 aprint_error_dev(sc->sc_dev, 453 "maxrtc_clock_write: failed to read " 454 "FINAL SECONDS\n"); 455 return (0); 456 } 457 458 if ((init_seconds == 59 && final_seconds != 59) || 459 (init_seconds != 59 && final_seconds != init_seconds + 1)) { 460 #if 1 461 printf("%s: maxrtc_clock_write: init %d, final %d, try again\n", 462 device_xname(sc->sc_dev), init_seconds, final_seconds); 463 #endif 464 goto again; 465 } 466 467 /* Finish by setting the control register's write-protect bit. */ 468 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 469 cmdbuf[1] = MAX6900_CONTROL_WP; 470 471 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 472 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 473 iic_release_bus(sc->sc_tag, I2C_F_POLL); 474 aprint_error_dev(sc->sc_dev, 475 "maxrtc_clock_write: failed to set WP bit\n"); 476 return (0); 477 } 478 479 iic_release_bus(sc->sc_tag, I2C_F_POLL); 480 481 return (1); 482 } 483
Indexes created Sun Oct 12 02:09:55 GMT 2025