max6900.c revision 1.7
1 /* $NetBSD: max6900.c,v 1.7 2007/01/12 19:33:21 cube Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/kernel.h> 42 #include <sys/fcntl.h> 43 #include <sys/uio.h> 44 #include <sys/conf.h> 45 #include <sys/event.h> 46 47 #include <dev/clock_subr.h> 48 49 #include <dev/i2c/i2cvar.h> 50 #include <dev/i2c/max6900reg.h> 51 52 struct maxrtc_softc { 53 struct device sc_dev; 54 i2c_tag_t sc_tag; 55 int sc_address; 56 int sc_open; 57 struct todr_chip_handle sc_todr; 58 }; 59 60 static int maxrtc_match(struct device *, struct cfdata *, void *); 61 static void maxrtc_attach(struct device *, struct device *, void *); 62 63 CFATTACH_DECL(maxrtc, sizeof(struct maxrtc_softc), 64 maxrtc_match, maxrtc_attach, NULL, NULL); 65 extern struct cfdriver maxrtc_cd; 66 67 dev_type_open(maxrtc_open); 68 dev_type_close(maxrtc_close); 69 dev_type_read(maxrtc_read); 70 dev_type_write(maxrtc_write); 71 72 const struct cdevsw maxrtc_cdevsw = { 73 maxrtc_open, maxrtc_close, maxrtc_read, maxrtc_write, noioctl, 74 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 75 }; 76 77 static int maxrtc_clock_read(struct maxrtc_softc *, struct clock_ymdhms *); 78 static int maxrtc_clock_write(struct maxrtc_softc *, struct clock_ymdhms *); 79 static int maxrtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 80 static int maxrtc_settime(struct todr_chip_handle *, volatile struct timeval *); 81 82 int 83 maxrtc_match(struct device *parent, struct cfdata *cf, void *aux) 84 { 85 struct i2c_attach_args *ia = aux; 86 87 if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR) 88 return (1); 89 90 return (0); 91 } 92 93 void 94 maxrtc_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct maxrtc_softc *sc = device_private(self); 97 struct i2c_attach_args *ia = aux; 98 99 sc->sc_tag = ia->ia_tag; 100 sc->sc_address = ia->ia_addr; 101 102 aprint_naive(": Real-time Clock/NVRAM\n"); 103 aprint_normal(": MAX6900 Real-time Clock/NVRAM\n"); 104 105 sc->sc_open = 0; 106 107 sc->sc_todr.cookie = sc; 108 sc->sc_todr.todr_gettime = maxrtc_gettime; 109 sc->sc_todr.todr_settime = maxrtc_settime; 110 sc->sc_todr.todr_setwen = NULL; 111 112 todr_attach(&sc->sc_todr); 113 } 114 115 /*ARGSUSED*/ 116 int 117 maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 118 { 119 struct maxrtc_softc *sc; 120 121 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 122 return (ENXIO); 123 124 /* XXX: Locking */ 125 126 if (sc->sc_open) 127 return (EBUSY); 128 129 sc->sc_open = 1; 130 return (0); 131 } 132 133 /*ARGSUSED*/ 134 int 135 maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 136 { 137 struct maxrtc_softc *sc; 138 139 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 140 return (ENXIO); 141 142 sc->sc_open = 0; 143 return (0); 144 } 145 146 /*ARGSUSED*/ 147 int 148 maxrtc_read(dev_t dev, struct uio *uio, int flags) 149 { 150 struct maxrtc_softc *sc; 151 u_int8_t ch, cmdbuf[1]; 152 int a, error; 153 154 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 155 return (ENXIO); 156 157 if (uio->uio_offset >= MAX6900_RAM_BYTES) 158 return (EINVAL); 159 160 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 161 return (error); 162 163 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 164 a = (int)uio->uio_offset; 165 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ; 166 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 167 sc->sc_address, cmdbuf, 1, 168 &ch, 1, 0)) != 0) { 169 iic_release_bus(sc->sc_tag, 0); 170 printf("%s: maxrtc_read: read failed at 0x%x\n", 171 sc->sc_dev.dv_xname, a); 172 return (error); 173 } 174 if ((error = uiomove(&ch, 1, uio)) != 0) { 175 iic_release_bus(sc->sc_tag, 0); 176 return (error); 177 } 178 } 179 180 iic_release_bus(sc->sc_tag, 0); 181 182 return (0); 183 } 184 185 /*ARGSUSED*/ 186 int 187 maxrtc_write(dev_t dev, struct uio *uio, int flags) 188 { 189 struct maxrtc_softc *sc; 190 u_int8_t cmdbuf[2]; 191 int a, error, sverror; 192 193 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 194 return (ENXIO); 195 196 if (uio->uio_offset >= MAX6900_RAM_BYTES) 197 return (EINVAL); 198 199 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 200 return (error); 201 202 /* Start by clearing the control register's write-protect bit. */ 203 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 204 cmdbuf[1] = 0; 205 206 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 207 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 208 iic_release_bus(sc->sc_tag, 0); 209 printf("%s: maxrtc_write: failed to clear WP bit\n", 210 sc->sc_dev.dv_xname); 211 return (error); 212 } 213 214 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 215 a = (int)uio->uio_offset; 216 217 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE; 218 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 219 break; 220 221 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 222 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 223 printf("%s: maxrtc_write: write failed at 0x%x\n", 224 sc->sc_dev.dv_xname, a); 225 break; 226 } 227 } 228 229 /* Set the write-protect bit again. */ 230 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 231 cmdbuf[1] = MAX6900_CONTROL_WP; 232 233 sverror = error; 234 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 235 sc->sc_address, cmdbuf, 1, 236 &cmdbuf[1], 1, 0)) != 0) { 237 if (sverror != 0) 238 error = sverror; 239 printf("%s: maxrtc_write: failed to set WP bit\n", 240 sc->sc_dev.dv_xname); 241 } 242 243 iic_release_bus(sc->sc_tag, 0); 244 245 return (error); 246 } 247 248 static int 249 maxrtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 250 { 251 struct maxrtc_softc *sc = ch->cookie; 252 struct clock_ymdhms dt; 253 254 if (maxrtc_clock_read(sc, &dt) == 0) 255 return (-1); 256 257 tv->tv_sec = clock_ymdhms_to_secs(&dt); 258 tv->tv_usec = 0; 259 260 return (0); 261 } 262 263 static int 264 maxrtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 265 { 266 struct maxrtc_softc *sc = ch->cookie; 267 struct clock_ymdhms dt; 268 269 clock_secs_to_ymdhms(tv->tv_sec, &dt); 270 271 if (maxrtc_clock_write(sc, &dt) == 0) 272 return (-1); 273 274 return (0); 275 } 276 277 /* 278 * While the MAX6900 has a nice Clock Burst Read/Write command, 279 * we can't use it, since some I2C controllers do not support 280 * anything other than single-byte transfers. 281 */ 282 static int max6900_rtc_offset[] = { 283 MAX6900_REG_SECOND, 284 MAX6900_REG_MINUTE, 285 MAX6900_REG_HOUR, 286 MAX6900_REG_DATE, 287 MAX6900_REG_MONTH, 288 MAX6900_REG_DAY, 289 MAX6900_REG_YEAR, 290 MAX6900_REG_CENTURY, /* control, if burst */ 291 }; 292 293 static int 294 maxrtc_clock_read(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 295 { 296 u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1]; 297 int i; 298 299 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 300 printf("%s: maxrtc_clock_read: failed to acquire I2C bus\n", 301 sc->sc_dev.dv_xname); 302 return (0); 303 } 304 305 /* Read each timekeeping register in order. */ 306 for (i = 0; i < MAX6900_BURST_LEN; i++) { 307 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ; 308 309 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 310 sc->sc_address, cmdbuf, 1, 311 &bcd[i], 1, I2C_F_POLL)) { 312 iic_release_bus(sc->sc_tag, I2C_F_POLL); 313 printf("%s: maxrtc_clock_read: failed to read rtc " 314 "at 0x%x\n", sc->sc_dev.dv_xname, 315 max6900_rtc_offset[i]); 316 return (0); 317 } 318 } 319 320 /* Done with I2C */ 321 iic_release_bus(sc->sc_tag, I2C_F_POLL); 322 323 /* 324 * Convert the MAX6900's register values into something useable 325 */ 326 dt->dt_sec = FROMBCD(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK); 327 dt->dt_min = FROMBCD(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK); 328 329 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) { 330 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 331 MAX6900_HOUR_12MASK); 332 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM) 333 dt->dt_hour += 12; 334 } else { 335 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 336 MAX6900_HOUR_24MASK); 337 } 338 339 dt->dt_day = FROMBCD(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK); 340 dt->dt_mon = FROMBCD(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK); 341 dt->dt_year = FROMBCD(bcd[MAX6900_BURST_YEAR]); 342 /* century in the burst control slot */ 343 dt->dt_year += (int)FROMBCD(bcd[MAX6900_BURST_CONTROL]) * 100; 344 345 return (1); 346 } 347 348 static int 349 maxrtc_clock_write(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 350 { 351 uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2]; 352 uint8_t init_seconds, final_seconds; 353 int i; 354 355 /* 356 * Convert our time representation into something the MAX6900 357 * can understand. 358 */ 359 bcd[MAX6900_BURST_SECOND] = TOBCD(dt->dt_sec); 360 bcd[MAX6900_BURST_MINUTE] = TOBCD(dt->dt_min); 361 bcd[MAX6900_BURST_HOUR] = TOBCD(dt->dt_hour) & MAX6900_HOUR_24MASK; 362 bcd[MAX6900_BURST_DATE] = TOBCD(dt->dt_day); 363 bcd[MAX6900_BURST_WDAY] = TOBCD(dt->dt_wday); 364 bcd[MAX6900_BURST_MONTH] = TOBCD(dt->dt_mon); 365 bcd[MAX6900_BURST_YEAR] = TOBCD(dt->dt_year % 100); 366 /* century in control slot */ 367 bcd[MAX6900_BURST_CONTROL] = TOBCD(dt->dt_year / 100); 368 369 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 370 printf("%s: maxrtc_clock_write: failed to acquire I2C bus\n", 371 sc->sc_dev.dv_xname); 372 return (0); 373 } 374 375 /* Start by clearing the control register's write-protect bit. */ 376 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 377 cmdbuf[1] = 0; 378 379 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 380 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 381 iic_release_bus(sc->sc_tag, I2C_F_POLL); 382 printf("%s: maxrtc_clock_write: failed to clear WP bit\n", 383 sc->sc_dev.dv_xname); 384 return (0); 385 } 386 387 /* 388 * The MAX6900 RTC manual recommends ensuring "atomicity" of 389 * a non-burst write by: 390 * 391 * - writing SECONDS 392 * - reading back SECONDS, remembering it as "initial seconds" 393 * - write the remaing RTC registers 394 * - read back SECONDS as "final seconds" 395 * - if "initial seconds" == 59, ensure "final seconds" == 59 396 * - else, ensure "final seconds" is no more than one second 397 * beyond "initial seconds". 398 */ 399 again: 400 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE; 401 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 402 cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, I2C_F_POLL)) { 403 iic_release_bus(sc->sc_tag, I2C_F_POLL); 404 printf("%s: maxrtc_clock_write: failed to write SECONDS\n", 405 sc->sc_dev.dv_xname); 406 return (0); 407 } 408 409 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 410 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 411 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 412 iic_release_bus(sc->sc_tag, I2C_F_POLL); 413 printf("%s: maxrtc_clock_write: failed to read " 414 "INITIAL SECONDS\n", sc->sc_dev.dv_xname); 415 return (0); 416 } 417 418 for (i = 1; i < MAX6900_BURST_LEN; i++) { 419 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE; 420 if (iic_exec(sc->sc_tag, 421 i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE : 422 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 423 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 424 iic_release_bus(sc->sc_tag, I2C_F_POLL); 425 printf("%s: maxrtc_clock_write: failed to write rtc " 426 " at 0x%x\n", sc->sc_dev.dv_xname, 427 max6900_rtc_offset[i]); 428 return (0); 429 } 430 } 431 432 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 433 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 434 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 435 iic_release_bus(sc->sc_tag, I2C_F_POLL); 436 printf("%s: maxrtc_clock_write: failed to read " 437 "FINAL SECONDS\n", sc->sc_dev.dv_xname); 438 return (0); 439 } 440 441 if ((init_seconds == 59 && final_seconds != 59) || 442 (init_seconds != 59 && final_seconds != init_seconds + 1)) { 443 #if 1 444 printf("%s: maxrtc_clock_write: init %d, final %d, try again\n", 445 sc->sc_dev.dv_xname, init_seconds, final_seconds); 446 #endif 447 goto again; 448 } 449 450 /* Finish by setting the control register's write-protect bit. */ 451 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 452 cmdbuf[1] = MAX6900_CONTROL_WP; 453 454 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 455 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 456 iic_release_bus(sc->sc_tag, I2C_F_POLL); 457 printf("%s: maxrtc_clock_write: failed to set WP bit\n", 458 sc->sc_dev.dv_xname); 459 return (0); 460 } 461 462 iic_release_bus(sc->sc_tag, I2C_F_POLL); 463 464 return (1); 465 } 466
Indexes created Tue Sep 23 07:09:52 GMT 2025