max6900.c revision 1.9
1 /* $NetBSD: max6900.c,v 1.9 2008/04/06 20:25:59 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: max6900.c,v 1.9 2008/04/06 20:25:59 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/fcntl.h> 46 #include <sys/uio.h> 47 #include <sys/conf.h> 48 #include <sys/event.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/max6900reg.h> 54 55 struct maxrtc_softc { 56 struct device sc_dev; 57 i2c_tag_t sc_tag; 58 int sc_address; 59 int sc_open; 60 struct todr_chip_handle sc_todr; 61 }; 62 63 static int maxrtc_match(struct device *, struct cfdata *, void *); 64 static void maxrtc_attach(struct device *, struct device *, void *); 65 66 CFATTACH_DECL(maxrtc, sizeof(struct maxrtc_softc), 67 maxrtc_match, maxrtc_attach, NULL, NULL); 68 extern struct cfdriver maxrtc_cd; 69 70 dev_type_open(maxrtc_open); 71 dev_type_close(maxrtc_close); 72 dev_type_read(maxrtc_read); 73 dev_type_write(maxrtc_write); 74 75 const struct cdevsw maxrtc_cdevsw = { 76 maxrtc_open, maxrtc_close, maxrtc_read, maxrtc_write, noioctl, 77 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER 78 }; 79 80 static int maxrtc_clock_read(struct maxrtc_softc *, struct clock_ymdhms *); 81 static int maxrtc_clock_write(struct maxrtc_softc *, struct clock_ymdhms *); 82 static int maxrtc_gettime(struct todr_chip_handle *, volatile struct timeval *); 83 static int maxrtc_settime(struct todr_chip_handle *, volatile struct timeval *); 84 85 int 86 maxrtc_match(struct device *parent, struct cfdata *cf, void *aux) 87 { 88 struct i2c_attach_args *ia = aux; 89 90 if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR) 91 return (1); 92 93 return (0); 94 } 95 96 void 97 maxrtc_attach(struct device *parent, struct device *self, void *aux) 98 { 99 struct maxrtc_softc *sc = device_private(self); 100 struct i2c_attach_args *ia = aux; 101 102 sc->sc_tag = ia->ia_tag; 103 sc->sc_address = ia->ia_addr; 104 105 aprint_naive(": Real-time Clock/NVRAM\n"); 106 aprint_normal(": MAX6900 Real-time Clock/NVRAM\n"); 107 108 sc->sc_open = 0; 109 110 sc->sc_todr.cookie = sc; 111 sc->sc_todr.todr_gettime = maxrtc_gettime; 112 sc->sc_todr.todr_settime = maxrtc_settime; 113 sc->sc_todr.todr_setwen = NULL; 114 115 todr_attach(&sc->sc_todr); 116 } 117 118 /*ARGSUSED*/ 119 int 120 maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 121 { 122 struct maxrtc_softc *sc; 123 124 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 125 return (ENXIO); 126 127 /* XXX: Locking */ 128 129 if (sc->sc_open) 130 return (EBUSY); 131 132 sc->sc_open = 1; 133 return (0); 134 } 135 136 /*ARGSUSED*/ 137 int 138 maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 139 { 140 struct maxrtc_softc *sc; 141 142 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 143 return (ENXIO); 144 145 sc->sc_open = 0; 146 return (0); 147 } 148 149 /*ARGSUSED*/ 150 int 151 maxrtc_read(dev_t dev, struct uio *uio, int flags) 152 { 153 struct maxrtc_softc *sc; 154 u_int8_t ch, cmdbuf[1]; 155 int a, error; 156 157 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 158 return (ENXIO); 159 160 if (uio->uio_offset >= MAX6900_RAM_BYTES) 161 return (EINVAL); 162 163 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 164 return (error); 165 166 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 167 a = (int)uio->uio_offset; 168 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ; 169 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 170 sc->sc_address, cmdbuf, 1, 171 &ch, 1, 0)) != 0) { 172 iic_release_bus(sc->sc_tag, 0); 173 aprint_error_dev(&sc->sc_dev, "maxrtc_read: read failed at 0x%x\n", a); 174 return (error); 175 } 176 if ((error = uiomove(&ch, 1, uio)) != 0) { 177 iic_release_bus(sc->sc_tag, 0); 178 return (error); 179 } 180 } 181 182 iic_release_bus(sc->sc_tag, 0); 183 184 return (0); 185 } 186 187 /*ARGSUSED*/ 188 int 189 maxrtc_write(dev_t dev, struct uio *uio, int flags) 190 { 191 struct maxrtc_softc *sc; 192 u_int8_t cmdbuf[2]; 193 int a, error, sverror; 194 195 if ((sc = device_lookup(&maxrtc_cd, minor(dev))) == NULL) 196 return (ENXIO); 197 198 if (uio->uio_offset >= MAX6900_RAM_BYTES) 199 return (EINVAL); 200 201 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 202 return (error); 203 204 /* Start by clearing the control register's write-protect bit. */ 205 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 206 cmdbuf[1] = 0; 207 208 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 209 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 210 iic_release_bus(sc->sc_tag, 0); 211 aprint_error_dev(&sc->sc_dev, "maxrtc_write: failed to clear WP bit\n"); 212 return (error); 213 } 214 215 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) { 216 a = (int)uio->uio_offset; 217 218 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE; 219 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 220 break; 221 222 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 223 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 224 aprint_error_dev(&sc->sc_dev, "maxrtc_write: write failed at 0x%x\n", a); 225 break; 226 } 227 } 228 229 /* Set the write-protect bit again. */ 230 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 231 cmdbuf[1] = MAX6900_CONTROL_WP; 232 233 sverror = error; 234 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 235 sc->sc_address, cmdbuf, 1, 236 &cmdbuf[1], 1, 0)) != 0) { 237 if (sverror != 0) 238 error = sverror; 239 aprint_error_dev(&sc->sc_dev, "maxrtc_write: failed to set WP bit\n"); 240 } 241 242 iic_release_bus(sc->sc_tag, 0); 243 244 return (error); 245 } 246 247 static int 248 maxrtc_gettime(struct todr_chip_handle *ch, volatile struct timeval *tv) 249 { 250 struct maxrtc_softc *sc = ch->cookie; 251 struct clock_ymdhms dt; 252 253 if (maxrtc_clock_read(sc, &dt) == 0) 254 return (-1); 255 256 tv->tv_sec = clock_ymdhms_to_secs(&dt); 257 tv->tv_usec = 0; 258 259 return (0); 260 } 261 262 static int 263 maxrtc_settime(struct todr_chip_handle *ch, volatile struct timeval *tv) 264 { 265 struct maxrtc_softc *sc = ch->cookie; 266 struct clock_ymdhms dt; 267 268 clock_secs_to_ymdhms(tv->tv_sec, &dt); 269 270 if (maxrtc_clock_write(sc, &dt) == 0) 271 return (-1); 272 273 return (0); 274 } 275 276 /* 277 * While the MAX6900 has a nice Clock Burst Read/Write command, 278 * we can't use it, since some I2C controllers do not support 279 * anything other than single-byte transfers. 280 */ 281 static int max6900_rtc_offset[] = { 282 MAX6900_REG_SECOND, 283 MAX6900_REG_MINUTE, 284 MAX6900_REG_HOUR, 285 MAX6900_REG_DATE, 286 MAX6900_REG_MONTH, 287 MAX6900_REG_DAY, 288 MAX6900_REG_YEAR, 289 MAX6900_REG_CENTURY, /* control, if burst */ 290 }; 291 292 static int 293 maxrtc_clock_read(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 294 { 295 u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1]; 296 int i; 297 298 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 299 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_read: failed to acquire I2C bus\n"); 300 return (0); 301 } 302 303 /* Read each timekeeping register in order. */ 304 for (i = 0; i < MAX6900_BURST_LEN; i++) { 305 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ; 306 307 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 308 sc->sc_address, cmdbuf, 1, 309 &bcd[i], 1, I2C_F_POLL)) { 310 iic_release_bus(sc->sc_tag, I2C_F_POLL); 311 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_read: failed to read rtc " 312 "at 0x%x\n", 313 max6900_rtc_offset[i]); 314 return (0); 315 } 316 } 317 318 /* Done with I2C */ 319 iic_release_bus(sc->sc_tag, I2C_F_POLL); 320 321 /* 322 * Convert the MAX6900's register values into something useable 323 */ 324 dt->dt_sec = FROMBCD(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK); 325 dt->dt_min = FROMBCD(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK); 326 327 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) { 328 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 329 MAX6900_HOUR_12MASK); 330 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM) 331 dt->dt_hour += 12; 332 } else { 333 dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] & 334 MAX6900_HOUR_24MASK); 335 } 336 337 dt->dt_day = FROMBCD(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK); 338 dt->dt_mon = FROMBCD(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK); 339 dt->dt_year = FROMBCD(bcd[MAX6900_BURST_YEAR]); 340 /* century in the burst control slot */ 341 dt->dt_year += (int)FROMBCD(bcd[MAX6900_BURST_CONTROL]) * 100; 342 343 return (1); 344 } 345 346 static int 347 maxrtc_clock_write(struct maxrtc_softc *sc, struct clock_ymdhms *dt) 348 { 349 uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2]; 350 uint8_t init_seconds, final_seconds; 351 int i; 352 353 /* 354 * Convert our time representation into something the MAX6900 355 * can understand. 356 */ 357 bcd[MAX6900_BURST_SECOND] = TOBCD(dt->dt_sec); 358 bcd[MAX6900_BURST_MINUTE] = TOBCD(dt->dt_min); 359 bcd[MAX6900_BURST_HOUR] = TOBCD(dt->dt_hour) & MAX6900_HOUR_24MASK; 360 bcd[MAX6900_BURST_DATE] = TOBCD(dt->dt_day); 361 bcd[MAX6900_BURST_WDAY] = TOBCD(dt->dt_wday); 362 bcd[MAX6900_BURST_MONTH] = TOBCD(dt->dt_mon); 363 bcd[MAX6900_BURST_YEAR] = TOBCD(dt->dt_year % 100); 364 /* century in control slot */ 365 bcd[MAX6900_BURST_CONTROL] = TOBCD(dt->dt_year / 100); 366 367 if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) { 368 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to acquire I2C bus\n"); 369 return (0); 370 } 371 372 /* Start by clearing the control register's write-protect bit. */ 373 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 374 cmdbuf[1] = 0; 375 376 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 377 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 378 iic_release_bus(sc->sc_tag, I2C_F_POLL); 379 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to clear WP bit\n"); 380 return (0); 381 } 382 383 /* 384 * The MAX6900 RTC manual recommends ensuring "atomicity" of 385 * a non-burst write by: 386 * 387 * - writing SECONDS 388 * - reading back SECONDS, remembering it as "initial seconds" 389 * - write the remaing RTC registers 390 * - read back SECONDS as "final seconds" 391 * - if "initial seconds" == 59, ensure "final seconds" == 59 392 * - else, ensure "final seconds" is no more than one second 393 * beyond "initial seconds". 394 */ 395 again: 396 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE; 397 if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 398 cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, I2C_F_POLL)) { 399 iic_release_bus(sc->sc_tag, I2C_F_POLL); 400 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to write SECONDS\n"); 401 return (0); 402 } 403 404 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 405 if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 406 cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) { 407 iic_release_bus(sc->sc_tag, I2C_F_POLL); 408 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to read " 409 "INITIAL SECONDS\n"); 410 return (0); 411 } 412 413 for (i = 1; i < MAX6900_BURST_LEN; i++) { 414 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE; 415 if (iic_exec(sc->sc_tag, 416 i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE : 417 I2C_OP_WRITE_WITH_STOP, sc->sc_address, 418 cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) { 419 iic_release_bus(sc->sc_tag, I2C_F_POLL); 420 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to write rtc " 421 " at 0x%x\n", 422 max6900_rtc_offset[i]); 423 return (0); 424 } 425 } 426 427 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ; 428 if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 429 cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) { 430 iic_release_bus(sc->sc_tag, I2C_F_POLL); 431 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to read " 432 "FINAL SECONDS\n"); 433 return (0); 434 } 435 436 if ((init_seconds == 59 && final_seconds != 59) || 437 (init_seconds != 59 && final_seconds != init_seconds + 1)) { 438 #if 1 439 printf("%s: maxrtc_clock_write: init %d, final %d, try again\n", 440 device_xname(&sc->sc_dev), init_seconds, final_seconds); 441 #endif 442 goto again; 443 } 444 445 /* Finish by setting the control register's write-protect bit. */ 446 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE; 447 cmdbuf[1] = MAX6900_CONTROL_WP; 448 449 if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 450 cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) { 451 iic_release_bus(sc->sc_tag, I2C_F_POLL); 452 aprint_error_dev(&sc->sc_dev, "maxrtc_clock_write: failed to set WP bit\n"); 453 return (0); 454 } 455 456 iic_release_bus(sc->sc_tag, I2C_F_POLL); 457 458 return (1); 459 } 460
Indexes created Sat Oct 11 19:10:01 GMT 2025