motoi2c.c revision 1.6 1 1.6 hkenken /* $NetBSD: motoi2c.c,v 1.6 2019/11/29 12:42:53 hkenken Exp $ */
2 1.1 matt
3 1.1 matt /*-
4 1.1 matt * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc.
5 1.1 matt * All rights reserved.
6 1.1 matt *
7 1.1 matt * This code is derived from software contributed to The NetBSD Foundation
8 1.2 nisimura * by Matt Thomas.
9 1.1 matt *
10 1.1 matt * Redistribution and use in source and binary forms, with or without
11 1.1 matt * modification, are permitted provided that the following conditions
12 1.1 matt * are met:
13 1.1 matt * 1. Redistributions of source code must retain the above copyright
14 1.1 matt * notice, this list of conditions and the following disclaimer.
15 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 matt * notice, this list of conditions and the following disclaimer in the
17 1.1 matt * documentation and/or other materials provided with the distribution.
18 1.1 matt *
19 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 matt * POSSIBILITY OF SUCH DAMAGE.
30 1.1 matt */
31 1.1 matt
32 1.1 matt #include <sys/cdefs.h>
33 1.6 hkenken __KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.6 2019/11/29 12:42:53 hkenken Exp $");
34 1.5 hkenken
35 1.5 hkenken #if defined(__arm__) || defined(__aarch64__)
36 1.5 hkenken #include "opt_fdt.h"
37 1.5 hkenken #endif
38 1.1 matt
39 1.1 matt #include <sys/param.h>
40 1.1 matt #include <sys/device.h>
41 1.1 matt #include <sys/systm.h>
42 1.1 matt #include <sys/mutex.h>
43 1.1 matt #include <sys/bus.h>
44 1.1 matt #include <sys/intr.h>
45 1.1 matt
46 1.1 matt #include <dev/i2c/i2cvar.h>
47 1.1 matt #include <dev/i2c/motoi2creg.h>
48 1.1 matt #include <dev/i2c/motoi2cvar.h>
49 1.1 matt
50 1.5 hkenken #ifdef FDT
51 1.5 hkenken #include <dev/fdt/fdtvar.h>
52 1.5 hkenken #endif
53 1.5 hkenken
54 1.1 matt #ifdef DEBUG
55 1.3 phx int motoi2c_debug = 0;
56 1.3 phx #define DPRINTF(x) if (motoi2c_debug) printf x
57 1.1 matt #else
58 1.3 phx #define DPRINTF(x)
59 1.1 matt #endif
60 1.1 matt
61 1.5 hkenken #ifdef FDT
62 1.5 hkenken static i2c_tag_t
63 1.5 hkenken motoi2c_get_tag(device_t dev)
64 1.5 hkenken {
65 1.5 hkenken struct motoi2c_softc * const sc = device_private(dev);
66 1.5 hkenken
67 1.5 hkenken return &sc->sc_i2c;
68 1.5 hkenken }
69 1.5 hkenken
70 1.5 hkenken static const struct fdtbus_i2c_controller_func motoi2c_funcs = {
71 1.5 hkenken .get_tag = motoi2c_get_tag,
72 1.5 hkenken };
73 1.5 hkenken #endif
74 1.5 hkenken
75 1.1 matt static int motoi2c_acquire_bus(void *, int);
76 1.1 matt static void motoi2c_release_bus(void *, int);
77 1.1 matt static int motoi2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
78 1.1 matt void *, size_t, int);
79 1.1 matt static int motoi2c_busy_wait(struct motoi2c_softc *, uint8_t);
80 1.1 matt
81 1.1 matt static const struct i2c_controller motoi2c = {
82 1.1 matt .ic_acquire_bus = motoi2c_acquire_bus,
83 1.1 matt .ic_release_bus = motoi2c_release_bus,
84 1.1 matt .ic_exec = motoi2c_exec,
85 1.1 matt };
86 1.1 matt
87 1.1 matt static const struct motoi2c_settings motoi2c_default_settings = {
88 1.1 matt .i2c_adr = MOTOI2C_ADR_DEFAULT,
89 1.1 matt .i2c_fdr = MOTOI2C_FDR_DEFAULT,
90 1.1 matt .i2c_dfsrr = MOTOI2C_DFSRR_DEFAULT,
91 1.1 matt };
92 1.1 matt
93 1.1 matt #define I2C_READ(r) ((*sc->sc_iord)(sc, (r)))
94 1.1 matt #define I2C_WRITE(r,v) ((*sc->sc_iowr)(sc, (r), (v)))
95 1.1 matt #define I2C_SETCLR(r, s, c) \
96 1.1 matt ((*sc->sc_iowr)(sc, (r), ((*sc->sc_iord)(sc, (r)) | (s)) & ~(c)))
97 1.1 matt
98 1.1 matt static uint8_t
99 1.1 matt motoi2c_iord1(struct motoi2c_softc *sc, bus_size_t off)
100 1.1 matt {
101 1.1 matt return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off);
102 1.1 matt }
103 1.1 matt
104 1.1 matt static void
105 1.1 matt motoi2c_iowr1(struct motoi2c_softc *sc, bus_size_t off, uint8_t data)
106 1.1 matt {
107 1.1 matt bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, data);
108 1.1 matt }
109 1.1 matt
110 1.1 matt void
111 1.1 matt motoi2c_attach_common(device_t self, struct motoi2c_softc *sc,
112 1.1 matt const struct motoi2c_settings *i2c)
113 1.1 matt {
114 1.1 matt struct i2cbus_attach_args iba;
115 1.1 matt
116 1.1 matt mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
117 1.1 matt
118 1.1 matt if (i2c == NULL)
119 1.1 matt i2c = &motoi2c_default_settings;
120 1.1 matt
121 1.1 matt sc->sc_i2c = motoi2c;
122 1.1 matt sc->sc_i2c.ic_cookie = sc;
123 1.1 matt if (sc->sc_iord == NULL)
124 1.1 matt sc->sc_iord = motoi2c_iord1;
125 1.1 matt if (sc->sc_iowr == NULL)
126 1.1 matt sc->sc_iowr = motoi2c_iowr1;
127 1.1 matt memset(&iba, 0, sizeof(iba));
128 1.1 matt iba.iba_tag = &sc->sc_i2c;
129 1.1 matt
130 1.1 matt I2C_WRITE(I2CCR, 0); /* reset before changing anything */
131 1.1 matt I2C_WRITE(I2CDFSRR, i2c->i2c_dfsrr); /* sampling units */
132 1.1 matt I2C_WRITE(I2CFDR, i2c->i2c_fdr); /* divider 3072 (0x31) */
133 1.1 matt I2C_WRITE(I2CADR, i2c->i2c_adr); /* our slave address is 0x7f */
134 1.1 matt I2C_WRITE(I2CSR, 0); /* clear status flags */
135 1.1 matt
136 1.5 hkenken #ifdef FDT
137 1.5 hkenken KASSERT(sc->sc_phandle != 0);
138 1.5 hkenken fdtbus_register_i2c_controller(self, sc->sc_phandle, &motoi2c_funcs);
139 1.5 hkenken
140 1.5 hkenken fdtbus_attach_i2cbus(self, sc->sc_phandle, &sc->sc_i2c, iicbus_print);
141 1.5 hkenken #else
142 1.1 matt config_found_ia(self, "i2cbus", &iba, iicbus_print);
143 1.5 hkenken #endif
144 1.1 matt }
145 1.1 matt
146 1.1 matt static int
147 1.1 matt motoi2c_acquire_bus(void *v, int flags)
148 1.1 matt {
149 1.1 matt struct motoi2c_softc * const sc = v;
150 1.1 matt
151 1.1 matt mutex_enter(&sc->sc_buslock);
152 1.1 matt I2C_WRITE(I2CCR, CR_MEN); /* enable the I2C module */
153 1.1 matt
154 1.1 matt return 0;
155 1.1 matt }
156 1.1 matt
157 1.1 matt static void
158 1.1 matt motoi2c_release_bus(void *v, int flags)
159 1.1 matt {
160 1.1 matt struct motoi2c_softc * const sc = v;
161 1.1 matt
162 1.1 matt I2C_WRITE(I2CCR, 0); /* reset before changing anything */
163 1.1 matt mutex_exit(&sc->sc_buslock);
164 1.1 matt }
165 1.1 matt
166 1.6 hkenken static int
167 1.6 hkenken motoi2c_stop_wait(struct motoi2c_softc *sc)
168 1.6 hkenken {
169 1.6 hkenken u_int timo;
170 1.6 hkenken int error = 0;
171 1.6 hkenken
172 1.6 hkenken timo = 1000;
173 1.6 hkenken while ((I2C_READ(I2CSR) & SR_MBB) != 0 && --timo)
174 1.6 hkenken DELAY(1);
175 1.6 hkenken
176 1.6 hkenken if (timo == 0) {
177 1.6 hkenken DPRINTF(("%s: timeout (sr=%#x)\n", __func__, I2C_READ(I2CSR)));
178 1.6 hkenken error = ETIMEDOUT;
179 1.6 hkenken }
180 1.6 hkenken
181 1.6 hkenken return error;
182 1.6 hkenken }
183 1.6 hkenken
184 1.1 matt /* busy waiting for byte data transfer completion */
185 1.1 matt static int
186 1.1 matt motoi2c_busy_wait(struct motoi2c_softc *sc, uint8_t cr)
187 1.1 matt {
188 1.1 matt uint8_t sr;
189 1.1 matt u_int timo;
190 1.1 matt int error = 0;
191 1.1 matt
192 1.1 matt timo = 1000;
193 1.1 matt while (((sr = I2C_READ(I2CSR)) & SR_MIF) == 0 && --timo)
194 1.1 matt DELAY(10);
195 1.1 matt
196 1.1 matt if (timo == 0) {
197 1.3 phx DPRINTF(("%s: timeout (sr=%#x, cr=%#x)\n",
198 1.3 phx __func__, sr, I2C_READ(I2CCR)));
199 1.1 matt error = ETIMEDOUT;
200 1.1 matt }
201 1.1 matt /*
202 1.1 matt * RXAK is only valid when transmitting.
203 1.1 matt */
204 1.1 matt if ((cr & CR_MTX) && (sr & SR_RXAK)) {
205 1.3 phx DPRINTF(("%s: missing rx ack (%#x): spin=%u\n",
206 1.3 phx __func__, sr, 1000 - timo));
207 1.1 matt error = EIO;
208 1.1 matt }
209 1.1 matt I2C_WRITE(I2CSR, 0);
210 1.1 matt return error;
211 1.1 matt }
212 1.1 matt
213 1.1 matt int
214 1.1 matt motoi2c_intr(void *v)
215 1.1 matt {
216 1.1 matt struct motoi2c_softc * const sc = v;
217 1.1 matt
218 1.1 matt panic("%s(%p)", __func__, sc);
219 1.1 matt
220 1.1 matt return 0;
221 1.1 matt }
222 1.1 matt
223 1.1 matt int
224 1.1 matt motoi2c_exec(void *v, i2c_op_t op, i2c_addr_t addr,
225 1.1 matt const void *cmdbuf, size_t cmdlen,
226 1.1 matt void *databuf, size_t datalen,
227 1.1 matt int flags)
228 1.1 matt {
229 1.1 matt struct motoi2c_softc * const sc = v;
230 1.1 matt uint8_t sr;
231 1.1 matt uint8_t cr;
232 1.1 matt int error;
233 1.1 matt
234 1.1 matt sr = I2C_READ(I2CSR);
235 1.1 matt cr = I2C_READ(I2CCR);
236 1.1 matt
237 1.1 matt #if 0
238 1.3 phx DPRINTF(("%s(%#x,%#x,%p,%zu,%p,%zu,%#x): sr=%#x cr=%#x\n",
239 1.1 matt __func__, op, addr, cmdbuf, cmdlen, databuf, datalen, flags,
240 1.3 phx sr, cr));
241 1.1 matt #endif
242 1.1 matt
243 1.1 matt if ((cr & CR_MSTA) == 0 && (sr & SR_MBB) != 0) {
244 1.1 matt /* wait for bus becoming available */
245 1.6 hkenken error = motoi2c_stop_wait(sc);
246 1.6 hkenken if (error)
247 1.1 matt return ETIMEDOUT;
248 1.1 matt }
249 1.1 matt
250 1.1 matt /* reset interrupt and arbitration-lost flags (all others are RO) */
251 1.1 matt I2C_WRITE(I2CSR, 0);
252 1.1 matt sr = I2C_READ(I2CSR);
253 1.1 matt
254 1.1 matt /*
255 1.6 hkenken * Generate start condition
256 1.1 matt */
257 1.1 matt cr = CR_MEN | CR_MTX | CR_MSTA;
258 1.6 hkenken I2C_WRITE(I2CCR, cr);
259 1.1 matt
260 1.3 phx DPRINTF(("%s: started: sr=%#x cr=%#x/%#x\n",
261 1.3 phx __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR)));
262 1.1 matt
263 1.1 matt sr = I2C_READ(I2CSR);
264 1.1 matt if (sr & SR_MAL) {
265 1.3 phx DPRINTF(("%s: lost bus: sr=%#x cr=%#x/%#x\n",
266 1.3 phx __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR)));
267 1.1 matt I2C_WRITE(I2CCR, 0);
268 1.1 matt DELAY(10);
269 1.1 matt I2C_WRITE(I2CCR, CR_MEN | CR_MTX | CR_MSTA);
270 1.1 matt DELAY(10);
271 1.1 matt sr = I2C_READ(I2CSR);
272 1.1 matt if (sr & SR_MAL) {
273 1.1 matt error = EBUSY;
274 1.1 matt goto out;
275 1.1 matt }
276 1.3 phx DPRINTF(("%s: reacquired bus: sr=%#x cr=%#x/%#x\n",
277 1.3 phx __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR)));
278 1.1 matt }
279 1.1 matt
280 1.1 matt /* send target address and transfer direction */
281 1.1 matt uint8_t addr_byte = (addr << 1)
282 1.1 matt | (cmdlen == 0 && I2C_OP_READ_P(op) ? 1 : 0);
283 1.1 matt I2C_WRITE(I2CDR, addr_byte);
284 1.1 matt
285 1.1 matt error = motoi2c_busy_wait(sc, cr);
286 1.1 matt if (error) {
287 1.3 phx DPRINTF(("%s: error sending address: %d\n", __func__, error));
288 1.1 matt if (error == EIO)
289 1.1 matt error = ENXIO;
290 1.1 matt goto out;
291 1.1 matt }
292 1.1 matt
293 1.1 matt const uint8_t *cmdptr = cmdbuf;
294 1.1 matt for (size_t i = 0; i < cmdlen; i++) {
295 1.1 matt I2C_WRITE(I2CDR, *cmdptr++);
296 1.1 matt
297 1.1 matt error = motoi2c_busy_wait(sc, cr);
298 1.1 matt if (error) {
299 1.3 phx DPRINTF(("%s: error sending cmd byte %zu (cr=%#x/%#x):"
300 1.3 phx " %d\n", __func__, i, I2C_READ(I2CCR), cr, error));
301 1.1 matt goto out;
302 1.1 matt }
303 1.1 matt }
304 1.1 matt
305 1.1 matt if (cmdlen > 0 && I2C_OP_READ_P(op)) {
306 1.1 matt KASSERT(cr & CR_MTX);
307 1.1 matt KASSERT((cr & CR_TXAK) == 0);
308 1.1 matt I2C_WRITE(I2CCR, cr | CR_RSTA);
309 1.1 matt #if 0
310 1.3 phx DPRINTF(("%s: restarted(read): sr=%#x cr=%#x(%#x)\n",
311 1.3 phx __func__, I2C_READ(I2CSR), cr | CR_RSTA, I2C_READ(I2CCR)));
312 1.1 matt #endif
313 1.1 matt
314 1.1 matt /* send target address and read transfer direction */
315 1.1 matt addr_byte |= 1;
316 1.1 matt I2C_WRITE(I2CDR, addr_byte);
317 1.1 matt
318 1.1 matt error = motoi2c_busy_wait(sc, cr);
319 1.1 matt if (error) {
320 1.1 matt if (error == EIO)
321 1.1 matt error = ENXIO;
322 1.1 matt goto out;
323 1.1 matt }
324 1.1 matt }
325 1.1 matt
326 1.1 matt if (I2C_OP_READ_P(op)) {
327 1.1 matt uint8_t *dataptr = databuf;
328 1.1 matt cr &= ~CR_MTX; /* clear transmit flags */
329 1.4 phx if (datalen <= 1)
330 1.1 matt cr |= CR_TXAK;
331 1.1 matt I2C_WRITE(I2CCR, cr);
332 1.1 matt DELAY(10);
333 1.1 matt (void)I2C_READ(I2CDR); /* dummy read */
334 1.1 matt for (size_t i = 0; i < datalen; i++) {
335 1.1 matt /*
336 1.1 matt * If a master receiver wants to terminate a data
337 1.1 matt * transfer, it must inform the slave transmitter by
338 1.1 matt * not acknowledging the last byte of data (by setting
339 1.1 matt * the transmit acknowledge bit (I2CCR[TXAK])) before
340 1.1 matt * reading the next-to-last byte of data.
341 1.1 matt */
342 1.1 matt error = motoi2c_busy_wait(sc, cr);
343 1.1 matt if (error) {
344 1.3 phx DPRINTF(("%s: error reading byte %zu: %d\n",
345 1.3 phx __func__, i, error));
346 1.1 matt goto out;
347 1.1 matt }
348 1.4 phx if (i == datalen - 2) {
349 1.4 phx cr |= CR_TXAK;
350 1.4 phx I2C_WRITE(I2CCR, cr);
351 1.4 phx } else if (i == datalen - 1 && I2C_OP_STOP_P(op)) {
352 1.6 hkenken cr = CR_MEN | CR_TXAK;
353 1.4 phx I2C_WRITE(I2CCR, cr);
354 1.1 matt }
355 1.1 matt *dataptr++ = I2C_READ(I2CDR);
356 1.1 matt }
357 1.1 matt if (datalen == 0) {
358 1.4 phx if (I2C_OP_STOP_P(op)) {
359 1.6 hkenken cr = CR_MEN | CR_TXAK;
360 1.4 phx I2C_WRITE(I2CCR, cr);
361 1.4 phx }
362 1.1 matt (void)I2C_READ(I2CDR); /* dummy read */
363 1.1 matt error = motoi2c_busy_wait(sc, cr);
364 1.1 matt if (error) {
365 1.3 phx DPRINTF(("%s: error reading dummy last byte:"
366 1.3 phx "%d\n", __func__, error));
367 1.1 matt goto out;
368 1.1 matt }
369 1.1 matt }
370 1.1 matt } else {
371 1.1 matt const uint8_t *dataptr = databuf;
372 1.1 matt for (size_t i = 0; i < datalen; i++) {
373 1.1 matt I2C_WRITE(I2CDR, *dataptr++);
374 1.1 matt error = motoi2c_busy_wait(sc, cr);
375 1.1 matt if (error) {
376 1.3 phx DPRINTF(("%s: error sending data byte %zu:"
377 1.3 phx " %d\n", __func__, i, error));
378 1.1 matt goto out;
379 1.1 matt }
380 1.1 matt }
381 1.1 matt }
382 1.1 matt
383 1.1 matt out:
384 1.1 matt /*
385 1.1 matt * If we encountered an error condition or caller wants a STOP,
386 1.1 matt * send a STOP.
387 1.1 matt */
388 1.1 matt if (error || (cr & CR_TXAK) || ((cr & CR_MSTA) && I2C_OP_STOP_P(op))) {
389 1.1 matt cr = CR_MEN;
390 1.1 matt I2C_WRITE(I2CCR, cr);
391 1.6 hkenken motoi2c_stop_wait(sc);
392 1.3 phx DPRINTF(("%s: stopping: cr=%#x/%#x\n", __func__,
393 1.3 phx cr, I2C_READ(I2CCR)));
394 1.1 matt }
395 1.1 matt
396 1.3 phx DPRINTF(("%s: exit sr=%#x cr=%#x: %d\n", __func__,
397 1.3 phx I2C_READ(I2CSR), I2C_READ(I2CCR), error));
398 1.1 matt
399 1.1 matt return error;
400 1.1 matt }
401