motoi2c.c revision 1.11
1 /* $NetBSD: motoi2c.c,v 1.11 2021/04/24 23:36:54 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.11 2021/04/24 23:36:54 thorpej Exp $"); 34 35 #if defined(__arm__) || defined(__aarch64__) 36 #include "opt_fdt.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 #include <sys/mutex.h> 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/motoi2creg.h> 48 #include <dev/i2c/motoi2cvar.h> 49 50 #ifdef FDT 51 #include <dev/fdt/fdtvar.h> 52 #endif 53 54 #ifdef DEBUG 55 int motoi2c_debug = 0; 56 #define DPRINTF(x) if (motoi2c_debug) printf x 57 #else 58 #define DPRINTF(x) 59 #endif 60 61 static int motoi2c_acquire_bus(void *, int); 62 static void motoi2c_release_bus(void *, int); 63 static int motoi2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 64 void *, size_t, int); 65 static int motoi2c_busy_wait(struct motoi2c_softc *, uint8_t); 66 67 static const struct motoi2c_settings motoi2c_default_settings = { 68 .i2c_adr = MOTOI2C_ADR_DEFAULT, 69 .i2c_fdr = MOTOI2C_FDR_DEFAULT, 70 .i2c_dfsrr = MOTOI2C_DFSRR_DEFAULT, 71 }; 72 73 #define I2C_READ(r) ((*sc->sc_iord)(sc, (r))) 74 #define I2C_WRITE(r,v) ((*sc->sc_iowr)(sc, (r), (v))) 75 #define I2C_SETCLR(r, s, c) \ 76 ((*sc->sc_iowr)(sc, (r), ((*sc->sc_iord)(sc, (r)) | (s)) & ~(c))) 77 78 static uint8_t 79 motoi2c_iord1(struct motoi2c_softc *sc, bus_size_t off) 80 { 81 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off); 82 } 83 84 static void 85 motoi2c_iowr1(struct motoi2c_softc *sc, bus_size_t off, uint8_t data) 86 { 87 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, data); 88 } 89 90 void 91 motoi2c_attach_common(device_t self, struct motoi2c_softc *sc, 92 const struct motoi2c_settings *i2c) 93 { 94 struct i2cbus_attach_args iba; 95 96 if (i2c == NULL) 97 i2c = &motoi2c_default_settings; 98 99 iic_tag_init(&sc->sc_i2c); 100 sc->sc_i2c.ic_cookie = sc; 101 sc->sc_i2c.ic_acquire_bus = motoi2c_acquire_bus; 102 sc->sc_i2c.ic_release_bus = motoi2c_release_bus; 103 sc->sc_i2c.ic_exec = motoi2c_exec; 104 if (sc->sc_iord == NULL) 105 sc->sc_iord = motoi2c_iord1; 106 if (sc->sc_iowr == NULL) 107 sc->sc_iowr = motoi2c_iowr1; 108 memset(&iba, 0, sizeof(iba)); 109 iba.iba_tag = &sc->sc_i2c; 110 iba.iba_child_devices = sc->sc_child_devices; 111 112 if ((sc->sc_flags & MOTOI2C_F_ENABLE_INV) != 0) { 113 sc->sc_enable_mask = 0; 114 sc->sc_disable_mask = CR_MEN; 115 } else { 116 sc->sc_enable_mask = CR_MEN; 117 sc->sc_disable_mask = 0; 118 } 119 120 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* reset before config */ 121 I2C_WRITE(I2CDFSRR, i2c->i2c_dfsrr); /* sampling units */ 122 I2C_WRITE(I2CFDR, i2c->i2c_fdr); /* divider 3072 (0x31) */ 123 I2C_WRITE(I2CADR, i2c->i2c_adr); /* our slave address is 0x7f */ 124 if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) { 125 I2C_WRITE(I2CSR, I2C_READ(I2CSR)); /* clear status flags */ 126 } else { 127 I2C_WRITE(I2CSR, 0); /* clear status flags */ 128 } 129 130 #ifdef FDT 131 if (sc->sc_phandle != 0) { 132 fdtbus_register_i2c_controller(&sc->sc_i2c, sc->sc_phandle); 133 fdtbus_attach_i2cbus(self, sc->sc_phandle, &sc->sc_i2c, 134 iicbus_print); 135 } else 136 #endif 137 config_found(self, &iba, iicbus_print, 138 CFARG_IATTR, "i2cbus", 139 CFARG_EOL); 140 } 141 142 static int 143 motoi2c_acquire_bus(void *v, int flags) 144 { 145 struct motoi2c_softc * const sc = v; 146 147 I2C_WRITE(I2CCR, sc->sc_enable_mask); /* enable the I2C module */ 148 149 return 0; 150 } 151 152 static void 153 motoi2c_release_bus(void *v, int flags) 154 { 155 struct motoi2c_softc * const sc = v; 156 157 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* disable the I2C module */ 158 } 159 160 static int 161 motoi2c_stop_wait(struct motoi2c_softc *sc) 162 { 163 u_int timo; 164 int error = 0; 165 166 timo = 1000; 167 while ((I2C_READ(I2CSR) & SR_MBB) != 0 && --timo) 168 DELAY(1); 169 170 if (timo == 0) { 171 DPRINTF(("%s: timeout (sr=%#x)\n", __func__, I2C_READ(I2CSR))); 172 error = ETIMEDOUT; 173 } 174 175 return error; 176 } 177 178 static void 179 motoi2c_clear_status(struct motoi2c_softc *sc, uint8_t sr) 180 { 181 if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) { 182 I2C_WRITE(I2CSR, sr); 183 } else { 184 I2C_WRITE(I2CSR, 0); 185 } 186 } 187 188 /* busy waiting for byte data transfer completion */ 189 static int 190 motoi2c_busy_wait(struct motoi2c_softc *sc, uint8_t cr) 191 { 192 uint8_t sr; 193 u_int timo; 194 int error = 0; 195 196 timo = 1000; 197 while (((sr = I2C_READ(I2CSR)) & SR_MIF) == 0 && --timo) 198 DELAY(10); 199 200 if (timo == 0) { 201 DPRINTF(("%s: timeout (sr=%#x, cr=%#x)\n", 202 __func__, sr, I2C_READ(I2CCR))); 203 error = ETIMEDOUT; 204 } 205 /* 206 * RXAK is only valid when transmitting. 207 */ 208 if ((cr & CR_MTX) && (sr & SR_RXAK)) { 209 DPRINTF(("%s: missing rx ack (%#x): spin=%u\n", 210 __func__, sr, 1000 - timo)); 211 error = EIO; 212 } 213 motoi2c_clear_status(sc, sr); 214 return error; 215 } 216 217 int 218 motoi2c_intr(void *v) 219 { 220 struct motoi2c_softc * const sc = v; 221 222 panic("%s(%p)", __func__, sc); 223 224 return 0; 225 } 226 227 int 228 motoi2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, 229 const void *cmdbuf, size_t cmdlen, 230 void *databuf, size_t datalen, 231 int flags) 232 { 233 struct motoi2c_softc * const sc = v; 234 uint8_t sr; 235 uint8_t cr; 236 int error; 237 238 sr = I2C_READ(I2CSR); 239 cr = I2C_READ(I2CCR); 240 241 #if 0 242 DPRINTF(("%s(%#x,%#x,%p,%zu,%p,%zu,%#x): sr=%#x cr=%#x\n", 243 __func__, op, addr, cmdbuf, cmdlen, databuf, datalen, flags, 244 sr, cr)); 245 #endif 246 247 if ((cr & CR_MSTA) == 0 && (sr & SR_MBB) != 0) { 248 /* wait for bus becoming available */ 249 error = motoi2c_stop_wait(sc); 250 if (error) 251 return ETIMEDOUT; 252 } 253 254 /* reset interrupt and arbitration-lost flags (all others are RO) */ 255 motoi2c_clear_status(sc, sr); 256 sr = I2C_READ(I2CSR); 257 258 /* 259 * Generate start condition 260 */ 261 cr = sc->sc_enable_mask | CR_MTX | CR_MSTA; 262 I2C_WRITE(I2CCR, cr); 263 264 DPRINTF(("%s: started: sr=%#x cr=%#x/%#x\n", 265 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 266 267 sr = I2C_READ(I2CSR); 268 if (sr & SR_MAL) { 269 DPRINTF(("%s: lost bus: sr=%#x cr=%#x/%#x\n", 270 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 271 I2C_WRITE(I2CCR, sc->sc_disable_mask); 272 DELAY(10); 273 I2C_WRITE(I2CCR, sc->sc_enable_mask | CR_MTX | CR_MSTA); 274 DELAY(10); 275 sr = I2C_READ(I2CSR); 276 if (sr & SR_MAL) { 277 error = EBUSY; 278 goto out; 279 } 280 DPRINTF(("%s: reacquired bus: sr=%#x cr=%#x/%#x\n", 281 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 282 } 283 284 /* send target address and transfer direction */ 285 uint8_t addr_byte = (addr << 1) 286 | (cmdlen == 0 && I2C_OP_READ_P(op) ? 1 : 0); 287 I2C_WRITE(I2CDR, addr_byte); 288 289 error = motoi2c_busy_wait(sc, cr); 290 if (error) { 291 DPRINTF(("%s: error sending address: %d\n", __func__, error)); 292 if (error == EIO) 293 error = ENXIO; 294 goto out; 295 } 296 297 const uint8_t *cmdptr = cmdbuf; 298 for (size_t i = 0; i < cmdlen; i++) { 299 I2C_WRITE(I2CDR, *cmdptr++); 300 301 error = motoi2c_busy_wait(sc, cr); 302 if (error) { 303 DPRINTF(("%s: error sending cmd byte %zu (cr=%#x/%#x):" 304 " %d\n", __func__, i, I2C_READ(I2CCR), cr, error)); 305 goto out; 306 } 307 } 308 309 if (cmdlen > 0 && I2C_OP_READ_P(op)) { 310 KASSERT(cr & CR_MTX); 311 KASSERT((cr & CR_TXAK) == 0); 312 I2C_WRITE(I2CCR, cr | CR_RSTA); 313 #if 0 314 DPRINTF(("%s: restarted(read): sr=%#x cr=%#x(%#x)\n", 315 __func__, I2C_READ(I2CSR), cr | CR_RSTA, I2C_READ(I2CCR))); 316 #endif 317 318 /* send target address and read transfer direction */ 319 addr_byte |= 1; 320 I2C_WRITE(I2CDR, addr_byte); 321 322 error = motoi2c_busy_wait(sc, cr); 323 if (error) { 324 if (error == EIO) 325 error = ENXIO; 326 goto out; 327 } 328 } 329 330 if (I2C_OP_READ_P(op)) { 331 uint8_t *dataptr = databuf; 332 cr &= ~CR_MTX; /* clear transmit flags */ 333 if (datalen <= 1) 334 cr |= CR_TXAK; 335 I2C_WRITE(I2CCR, cr); 336 DELAY(10); 337 (void)I2C_READ(I2CDR); /* dummy read */ 338 for (size_t i = 0; i < datalen; i++) { 339 /* 340 * If a master receiver wants to terminate a data 341 * transfer, it must inform the slave transmitter by 342 * not acknowledging the last byte of data (by setting 343 * the transmit acknowledge bit (I2CCR[TXAK])) before 344 * reading the next-to-last byte of data. 345 */ 346 error = motoi2c_busy_wait(sc, cr); 347 if (error) { 348 DPRINTF(("%s: error reading byte %zu: %d\n", 349 __func__, i, error)); 350 goto out; 351 } 352 if (i == datalen - 2) { 353 cr |= CR_TXAK; 354 I2C_WRITE(I2CCR, cr); 355 } else if (i == datalen - 1 && I2C_OP_STOP_P(op)) { 356 cr = sc->sc_enable_mask | CR_TXAK; 357 I2C_WRITE(I2CCR, cr); 358 } 359 *dataptr++ = I2C_READ(I2CDR); 360 } 361 if (datalen == 0) { 362 if (I2C_OP_STOP_P(op)) { 363 cr = sc->sc_enable_mask | CR_TXAK; 364 I2C_WRITE(I2CCR, cr); 365 } 366 (void)I2C_READ(I2CDR); /* dummy read */ 367 error = motoi2c_busy_wait(sc, cr); 368 if (error) { 369 DPRINTF(("%s: error reading dummy last byte:" 370 "%d\n", __func__, error)); 371 goto out; 372 } 373 } 374 } else { 375 const uint8_t *dataptr = databuf; 376 for (size_t i = 0; i < datalen; i++) { 377 I2C_WRITE(I2CDR, *dataptr++); 378 error = motoi2c_busy_wait(sc, cr); 379 if (error) { 380 DPRINTF(("%s: error sending data byte %zu:" 381 " %d\n", __func__, i, error)); 382 goto out; 383 } 384 } 385 } 386 387 out: 388 /* 389 * If we encountered an error condition or caller wants a STOP, 390 * send a STOP. 391 */ 392 if (error || (cr & CR_TXAK) || ((cr & CR_MSTA) && I2C_OP_STOP_P(op))) { 393 cr = sc->sc_enable_mask; 394 I2C_WRITE(I2CCR, cr); 395 motoi2c_stop_wait(sc); 396 DPRINTF(("%s: stopping: cr=%#x/%#x\n", __func__, 397 cr, I2C_READ(I2CCR))); 398 } 399 400 DPRINTF(("%s: exit sr=%#x cr=%#x: %d\n", __func__, 401 I2C_READ(I2CSR), I2C_READ(I2CCR), error)); 402 403 return error; 404 } 405
Indexes created Thu Sep 25 16:09:42 GMT 2025