motoi2c.c revision 1.14
1 /* $NetBSD: motoi2c.c,v 1.14 2025/09/15 13:23:03 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.14 2025/09/15 13:23:03 thorpej Exp $"); 34 35 #if defined(__arm__) || defined(__aarch64__) 36 #include "opt_fdt.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 #include <sys/mutex.h> 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/motoi2creg.h> 48 #include <dev/i2c/motoi2cvar.h> 49 50 #ifdef FDT 51 #include <dev/fdt/fdtvar.h> 52 #endif 53 54 #ifdef DEBUG 55 int motoi2c_debug = 0; 56 #define DPRINTF(x) if (motoi2c_debug) printf x 57 #else 58 #define DPRINTF(x) 59 #endif 60 61 static int motoi2c_acquire_bus(void *, int); 62 static void motoi2c_release_bus(void *, int); 63 static int motoi2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 64 void *, size_t, int); 65 static void motoi2c_clear_status(struct motoi2c_softc *, uint8_t); 66 static int motoi2c_busy_wait(struct motoi2c_softc *, uint8_t); 67 68 static const struct motoi2c_settings motoi2c_default_settings = { 69 .i2c_adr = MOTOI2C_ADR_DEFAULT, 70 .i2c_fdr = MOTOI2C_FDR_DEFAULT, 71 .i2c_dfsrr = MOTOI2C_DFSRR_DEFAULT, 72 }; 73 74 #define I2C_READ(r) ((*sc->sc_iord)(sc, (r))) 75 #define I2C_WRITE(r,v) ((*sc->sc_iowr)(sc, (r), (v))) 76 #define I2C_SETCLR(r, s, c) \ 77 ((*sc->sc_iowr)(sc, (r), ((*sc->sc_iord)(sc, (r)) | (s)) & ~(c))) 78 79 static uint8_t 80 motoi2c_iord1(struct motoi2c_softc *sc, bus_size_t off) 81 { 82 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off); 83 } 84 85 static void 86 motoi2c_iowr1(struct motoi2c_softc *sc, bus_size_t off, uint8_t data) 87 { 88 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, data); 89 } 90 91 void 92 motoi2c_attach(struct motoi2c_softc *sc, 93 const struct motoi2c_settings *settings) 94 { 95 struct i2cbus_attach_args iba; 96 97 if (settings == NULL) { 98 sc->sc_settings = motoi2c_default_settings; 99 } else { 100 sc->sc_settings = *settings; 101 } 102 if (sc->sc_iord == NULL) 103 sc->sc_iord = motoi2c_iord1; 104 if (sc->sc_iowr == NULL) 105 sc->sc_iowr = motoi2c_iowr1; 106 107 iic_tag_init(&sc->sc_i2c); 108 sc->sc_i2c.ic_cookie = sc; 109 sc->sc_i2c.ic_acquire_bus = motoi2c_acquire_bus; 110 sc->sc_i2c.ic_release_bus = motoi2c_release_bus; 111 sc->sc_i2c.ic_exec = motoi2c_exec; 112 memset(&iba, 0, sizeof(iba)); 113 iba.iba_tag = &sc->sc_i2c; 114 iba.iba_child_devices = sc->sc_child_devices; 115 116 if ((sc->sc_flags & MOTOI2C_F_ENABLE_INV) != 0) { 117 sc->sc_enable_mask = 0; 118 sc->sc_disable_mask = CR_MEN; 119 } else { 120 sc->sc_enable_mask = CR_MEN; 121 sc->sc_disable_mask = 0; 122 } 123 124 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* reset before config */ 125 I2C_WRITE(I2CDFSRR, sc->sc_settings.i2c_dfsrr); /* sampling units */ 126 I2C_WRITE(I2CFDR, sc->sc_settings.i2c_fdr); /* divider 3072 */ 127 I2C_WRITE(I2CADR, sc->sc_settings.i2c_adr); /* our slave address */ 128 motoi2c_clear_status(sc, I2C_READ(I2CSR)); 129 130 #ifdef FDT 131 if (sc->sc_phandle != 0) { 132 fdtbus_register_i2c_controller(&sc->sc_i2c, sc->sc_phandle); 133 fdtbus_attach_i2cbus(sc->sc_dev, sc->sc_phandle, &sc->sc_i2c, 134 iicbus_print); 135 } else 136 #endif 137 iicbus_attach(sc->sc_dev, &sc->sc_i2c); 138 } 139 140 static int 141 motoi2c_acquire_bus(void *v, int flags) 142 { 143 struct motoi2c_softc * const sc = v; 144 145 I2C_WRITE(I2CCR, sc->sc_enable_mask); /* enable the I2C module */ 146 147 return 0; 148 } 149 150 static void 151 motoi2c_release_bus(void *v, int flags) 152 { 153 struct motoi2c_softc * const sc = v; 154 155 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* disable the I2C module */ 156 } 157 158 static int 159 motoi2c_stop_wait(struct motoi2c_softc *sc) 160 { 161 u_int timo; 162 int error = 0; 163 164 timo = 1000; 165 while ((I2C_READ(I2CSR) & SR_MBB) != 0 && --timo) 166 DELAY(1); 167 168 if (timo == 0) { 169 DPRINTF(("%s: timeout (sr=%#x)\n", __func__, I2C_READ(I2CSR))); 170 error = ETIMEDOUT; 171 } 172 173 return error; 174 } 175 176 static void 177 motoi2c_clear_status(struct motoi2c_softc *sc, uint8_t sr) 178 { 179 if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) { 180 I2C_WRITE(I2CSR, sr); 181 } else { 182 I2C_WRITE(I2CSR, 0); 183 } 184 } 185 186 /* busy waiting for byte data transfer completion */ 187 static int 188 motoi2c_busy_wait(struct motoi2c_softc *sc, uint8_t cr) 189 { 190 uint8_t sr; 191 u_int timo; 192 int error = 0; 193 194 timo = 1000; 195 while (((sr = I2C_READ(I2CSR)) & SR_MIF) == 0 && --timo) 196 DELAY(10); 197 198 if (timo == 0) { 199 DPRINTF(("%s: timeout (sr=%#x, cr=%#x)\n", 200 __func__, sr, I2C_READ(I2CCR))); 201 error = ETIMEDOUT; 202 } 203 /* 204 * RXAK is only valid when transmitting. 205 */ 206 if ((cr & CR_MTX) && (sr & SR_RXAK)) { 207 DPRINTF(("%s: missing rx ack (%#x): spin=%u\n", 208 __func__, sr, 1000 - timo)); 209 error = EIO; 210 } 211 motoi2c_clear_status(sc, sr); 212 return error; 213 } 214 215 int 216 motoi2c_intr(void *v) 217 { 218 struct motoi2c_softc * const sc = v; 219 220 panic("%s(%p)", __func__, sc); 221 222 return 0; 223 } 224 225 int 226 motoi2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, 227 const void *cmdbuf, size_t cmdlen, 228 void *databuf, size_t datalen, 229 int flags) 230 { 231 struct motoi2c_softc * const sc = v; 232 uint8_t sr; 233 uint8_t cr; 234 int error; 235 236 sr = I2C_READ(I2CSR); 237 cr = I2C_READ(I2CCR); 238 239 #if 0 240 DPRINTF(("%s(%#x,%#x,%p,%zu,%p,%zu,%#x): sr=%#x cr=%#x\n", 241 __func__, op, addr, cmdbuf, cmdlen, databuf, datalen, flags, 242 sr, cr)); 243 #endif 244 245 if ((cr & CR_MSTA) == 0 && (sr & SR_MBB) != 0) { 246 /* wait for bus becoming available */ 247 error = motoi2c_stop_wait(sc); 248 if (error) 249 return ETIMEDOUT; 250 } 251 252 /* reset interrupt and arbitration-lost flags (all others are RO) */ 253 motoi2c_clear_status(sc, sr); 254 sr = I2C_READ(I2CSR); 255 256 /* 257 * Generate start condition 258 */ 259 cr = sc->sc_enable_mask | CR_MTX | CR_MSTA; 260 I2C_WRITE(I2CCR, cr); 261 262 DPRINTF(("%s: started: sr=%#x cr=%#x/%#x\n", 263 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 264 265 sr = I2C_READ(I2CSR); 266 if (sr & SR_MAL) { 267 DPRINTF(("%s: lost bus: sr=%#x cr=%#x/%#x\n", 268 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 269 I2C_WRITE(I2CCR, sc->sc_disable_mask); 270 DELAY(10); 271 I2C_WRITE(I2CCR, sc->sc_enable_mask | CR_MTX | CR_MSTA); 272 DELAY(10); 273 sr = I2C_READ(I2CSR); 274 if (sr & SR_MAL) { 275 error = EBUSY; 276 goto out; 277 } 278 DPRINTF(("%s: reacquired bus: sr=%#x cr=%#x/%#x\n", 279 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 280 } 281 282 /* send target address and transfer direction */ 283 uint8_t addr_byte = (addr << 1) 284 | (cmdlen == 0 && I2C_OP_READ_P(op) ? 1 : 0); 285 I2C_WRITE(I2CDR, addr_byte); 286 287 error = motoi2c_busy_wait(sc, cr); 288 if (error) { 289 DPRINTF(("%s: error sending address: %d\n", __func__, error)); 290 if (error == EIO) 291 error = ENXIO; 292 goto out; 293 } 294 295 const uint8_t *cmdptr = cmdbuf; 296 for (size_t i = 0; i < cmdlen; i++) { 297 I2C_WRITE(I2CDR, *cmdptr++); 298 299 error = motoi2c_busy_wait(sc, cr); 300 if (error) { 301 DPRINTF(("%s: error sending cmd byte %zu (cr=%#x/%#x):" 302 " %d\n", __func__, i, I2C_READ(I2CCR), cr, error)); 303 goto out; 304 } 305 } 306 307 if (cmdlen > 0 && I2C_OP_READ_P(op)) { 308 KASSERT(cr & CR_MTX); 309 KASSERT((cr & CR_TXAK) == 0); 310 I2C_WRITE(I2CCR, cr | CR_RSTA); 311 #if 0 312 DPRINTF(("%s: restarted(read): sr=%#x cr=%#x(%#x)\n", 313 __func__, I2C_READ(I2CSR), cr | CR_RSTA, I2C_READ(I2CCR))); 314 #endif 315 316 /* send target address and read transfer direction */ 317 addr_byte |= 1; 318 I2C_WRITE(I2CDR, addr_byte); 319 320 error = motoi2c_busy_wait(sc, cr); 321 if (error) { 322 if (error == EIO) 323 error = ENXIO; 324 goto out; 325 } 326 } 327 328 if (I2C_OP_READ_P(op)) { 329 uint8_t *dataptr = databuf; 330 cr &= ~CR_MTX; /* clear transmit flags */ 331 if (datalen <= 1) 332 cr |= CR_TXAK; 333 I2C_WRITE(I2CCR, cr); 334 DELAY(10); 335 (void)I2C_READ(I2CDR); /* dummy read */ 336 for (size_t i = 0; i < datalen; i++) { 337 /* 338 * If a master receiver wants to terminate a data 339 * transfer, it must inform the slave transmitter by 340 * not acknowledging the last byte of data (by setting 341 * the transmit acknowledge bit (I2CCR[TXAK])) before 342 * reading the next-to-last byte of data. 343 */ 344 error = motoi2c_busy_wait(sc, cr); 345 if (error) { 346 DPRINTF(("%s: error reading byte %zu: %d\n", 347 __func__, i, error)); 348 goto out; 349 } 350 if (i == datalen - 2) { 351 cr |= CR_TXAK; 352 I2C_WRITE(I2CCR, cr); 353 } else if (i == datalen - 1 && I2C_OP_STOP_P(op)) { 354 cr = sc->sc_enable_mask | CR_TXAK; 355 I2C_WRITE(I2CCR, cr); 356 } 357 *dataptr++ = I2C_READ(I2CDR); 358 } 359 if (datalen == 0) { 360 if (I2C_OP_STOP_P(op)) { 361 cr = sc->sc_enable_mask | CR_TXAK; 362 I2C_WRITE(I2CCR, cr); 363 } 364 (void)I2C_READ(I2CDR); /* dummy read */ 365 error = motoi2c_busy_wait(sc, cr); 366 if (error) { 367 DPRINTF(("%s: error reading dummy last byte:" 368 "%d\n", __func__, error)); 369 goto out; 370 } 371 } 372 } else { 373 const uint8_t *dataptr = databuf; 374 for (size_t i = 0; i < datalen; i++) { 375 I2C_WRITE(I2CDR, *dataptr++); 376 error = motoi2c_busy_wait(sc, cr); 377 if (error) { 378 DPRINTF(("%s: error sending data byte %zu:" 379 " %d\n", __func__, i, error)); 380 goto out; 381 } 382 } 383 } 384 385 out: 386 /* 387 * If we encountered an error condition or caller wants a STOP, 388 * send a STOP. 389 */ 390 if (error || (cr & CR_TXAK) || ((cr & CR_MSTA) && I2C_OP_STOP_P(op))) { 391 cr = sc->sc_enable_mask; 392 I2C_WRITE(I2CCR, cr); 393 motoi2c_stop_wait(sc); 394 DPRINTF(("%s: stopping: cr=%#x/%#x\n", __func__, 395 cr, I2C_READ(I2CCR))); 396 } 397 398 DPRINTF(("%s: exit sr=%#x cr=%#x: %d\n", __func__, 399 I2C_READ(I2CSR), I2C_READ(I2CCR), error)); 400 401 return error; 402 } 403
Indexes created Mon Sep 22 21:09:42 GMT 2025