motoi2c.c revision 1.17
1 /* $NetBSD: motoi2c.c,v 1.17 2025/09/16 11:55:17 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: motoi2c.c,v 1.17 2025/09/16 11:55:17 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/bus.h> 40 #include <sys/intr.h> 41 42 #include <dev/i2c/i2cvar.h> 43 #include <dev/i2c/motoi2creg.h> 44 #include <dev/i2c/motoi2cvar.h> 45 46 #ifdef DEBUG 47 int motoi2c_debug = 0; 48 #define DPRINTF(x) if (motoi2c_debug) printf x 49 #else 50 #define DPRINTF(x) 51 #endif 52 53 static int motoi2c_acquire_bus(void *, int); 54 static void motoi2c_release_bus(void *, int); 55 static int motoi2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 56 void *, size_t, int); 57 static void motoi2c_clear_status(struct motoi2c_softc *, uint8_t); 58 static int motoi2c_busy_wait(struct motoi2c_softc *, uint8_t); 59 60 static const struct motoi2c_settings motoi2c_default_settings = { 61 .i2c_adr = MOTOI2C_ADR_DEFAULT, 62 .i2c_fdr = MOTOI2C_FDR_DEFAULT, 63 .i2c_dfsrr = MOTOI2C_DFSRR_DEFAULT, 64 }; 65 66 #define I2C_READ(r) ((*sc->sc_iord)(sc, (r))) 67 #define I2C_WRITE(r,v) ((*sc->sc_iowr)(sc, (r), (v))) 68 #define I2C_SETCLR(r, s, c) \ 69 ((*sc->sc_iowr)(sc, (r), ((*sc->sc_iord)(sc, (r)) | (s)) & ~(c))) 70 71 static uint8_t 72 motoi2c_iord1(struct motoi2c_softc *sc, bus_size_t off) 73 { 74 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off); 75 } 76 77 static void 78 motoi2c_iowr1(struct motoi2c_softc *sc, bus_size_t off, uint8_t data) 79 { 80 bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, data); 81 } 82 83 void 84 motoi2c_attach(struct motoi2c_softc *sc, 85 const struct motoi2c_settings *settings) 86 { 87 if (settings == NULL) { 88 sc->sc_settings = motoi2c_default_settings; 89 } else { 90 sc->sc_settings = *settings; 91 } 92 if (sc->sc_iord == NULL) 93 sc->sc_iord = motoi2c_iord1; 94 if (sc->sc_iowr == NULL) 95 sc->sc_iowr = motoi2c_iowr1; 96 97 iic_tag_init(&sc->sc_i2c); 98 sc->sc_i2c.ic_cookie = sc; 99 sc->sc_i2c.ic_acquire_bus = motoi2c_acquire_bus; 100 sc->sc_i2c.ic_release_bus = motoi2c_release_bus; 101 sc->sc_i2c.ic_exec = motoi2c_exec; 102 103 if ((sc->sc_flags & MOTOI2C_F_ENABLE_INV) != 0) { 104 sc->sc_enable_mask = 0; 105 sc->sc_disable_mask = CR_MEN; 106 } else { 107 sc->sc_enable_mask = CR_MEN; 108 sc->sc_disable_mask = 0; 109 } 110 111 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* reset before config */ 112 I2C_WRITE(I2CDFSRR, sc->sc_settings.i2c_dfsrr); /* sampling units */ 113 I2C_WRITE(I2CFDR, sc->sc_settings.i2c_fdr); /* divider 3072 */ 114 I2C_WRITE(I2CADR, sc->sc_settings.i2c_adr); /* our slave address */ 115 motoi2c_clear_status(sc, I2C_READ(I2CSR)); 116 117 iicbus_attach(sc->sc_dev, &sc->sc_i2c); 118 } 119 120 static int 121 motoi2c_acquire_bus(void *v, int flags) 122 { 123 struct motoi2c_softc * const sc = v; 124 125 I2C_WRITE(I2CCR, sc->sc_enable_mask); /* enable the I2C module */ 126 127 return 0; 128 } 129 130 static void 131 motoi2c_release_bus(void *v, int flags) 132 { 133 struct motoi2c_softc * const sc = v; 134 135 I2C_WRITE(I2CCR, sc->sc_disable_mask); /* disable the I2C module */ 136 } 137 138 static int 139 motoi2c_stop_wait(struct motoi2c_softc *sc) 140 { 141 u_int timo; 142 int error = 0; 143 144 timo = 1000; 145 while ((I2C_READ(I2CSR) & SR_MBB) != 0 && --timo) 146 DELAY(1); 147 148 if (timo == 0) { 149 DPRINTF(("%s: timeout (sr=%#x)\n", __func__, I2C_READ(I2CSR))); 150 error = ETIMEDOUT; 151 } 152 153 return error; 154 } 155 156 static void 157 motoi2c_clear_status(struct motoi2c_softc *sc, uint8_t sr) 158 { 159 if ((sc->sc_flags & MOTOI2C_F_STATUS_W1C) != 0) { 160 I2C_WRITE(I2CSR, sr); 161 } else { 162 I2C_WRITE(I2CSR, 0); 163 } 164 } 165 166 /* busy waiting for byte data transfer completion */ 167 static int 168 motoi2c_busy_wait(struct motoi2c_softc *sc, uint8_t cr) 169 { 170 uint8_t sr; 171 u_int timo; 172 int error = 0; 173 174 timo = 1000; 175 while (((sr = I2C_READ(I2CSR)) & SR_MIF) == 0 && --timo) 176 DELAY(10); 177 178 if (timo == 0) { 179 DPRINTF(("%s: timeout (sr=%#x, cr=%#x)\n", 180 __func__, sr, I2C_READ(I2CCR))); 181 error = ETIMEDOUT; 182 } 183 /* 184 * RXAK is only valid when transmitting. 185 */ 186 if ((cr & CR_MTX) && (sr & SR_RXAK)) { 187 DPRINTF(("%s: missing rx ack (%#x): spin=%u\n", 188 __func__, sr, 1000 - timo)); 189 error = EIO; 190 } 191 motoi2c_clear_status(sc, sr); 192 return error; 193 } 194 195 int 196 motoi2c_intr(void *v) 197 { 198 struct motoi2c_softc * const sc = v; 199 200 panic("%s(%p)", __func__, sc); 201 202 return 0; 203 } 204 205 int 206 motoi2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, 207 const void *cmdbuf, size_t cmdlen, 208 void *databuf, size_t datalen, 209 int flags) 210 { 211 struct motoi2c_softc * const sc = v; 212 uint8_t sr; 213 uint8_t cr; 214 int error; 215 216 sr = I2C_READ(I2CSR); 217 cr = I2C_READ(I2CCR); 218 219 #if 0 220 DPRINTF(("%s(%#x,%#x,%p,%zu,%p,%zu,%#x): sr=%#x cr=%#x\n", 221 __func__, op, addr, cmdbuf, cmdlen, databuf, datalen, flags, 222 sr, cr)); 223 #endif 224 225 if ((cr & CR_MSTA) == 0 && (sr & SR_MBB) != 0) { 226 /* wait for bus becoming available */ 227 error = motoi2c_stop_wait(sc); 228 if (error) 229 return ETIMEDOUT; 230 } 231 232 /* reset interrupt and arbitration-lost flags (all others are RO) */ 233 motoi2c_clear_status(sc, sr); 234 sr = I2C_READ(I2CSR); 235 236 /* 237 * Generate start condition 238 */ 239 cr = sc->sc_enable_mask | CR_MTX | CR_MSTA; 240 I2C_WRITE(I2CCR, cr); 241 242 DPRINTF(("%s: started: sr=%#x cr=%#x/%#x\n", 243 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 244 245 sr = I2C_READ(I2CSR); 246 if (sr & SR_MAL) { 247 DPRINTF(("%s: lost bus: sr=%#x cr=%#x/%#x\n", 248 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 249 I2C_WRITE(I2CCR, sc->sc_disable_mask); 250 DELAY(10); 251 I2C_WRITE(I2CCR, sc->sc_enable_mask | CR_MTX | CR_MSTA); 252 DELAY(10); 253 sr = I2C_READ(I2CSR); 254 if (sr & SR_MAL) { 255 error = EBUSY; 256 goto out; 257 } 258 DPRINTF(("%s: reacquired bus: sr=%#x cr=%#x/%#x\n", 259 __func__, I2C_READ(I2CSR), cr, I2C_READ(I2CCR))); 260 } 261 262 /* send target address and transfer direction */ 263 uint8_t addr_byte = (addr << 1) 264 | (cmdlen == 0 && I2C_OP_READ_P(op) ? 1 : 0); 265 I2C_WRITE(I2CDR, addr_byte); 266 267 error = motoi2c_busy_wait(sc, cr); 268 if (error) { 269 DPRINTF(("%s: error sending address: %d\n", __func__, error)); 270 if (error == EIO) 271 error = ENXIO; 272 goto out; 273 } 274 275 const uint8_t *cmdptr = cmdbuf; 276 for (size_t i = 0; i < cmdlen; i++) { 277 I2C_WRITE(I2CDR, *cmdptr++); 278 279 error = motoi2c_busy_wait(sc, cr); 280 if (error) { 281 DPRINTF(("%s: error sending cmd byte %zu (cr=%#x/%#x):" 282 " %d\n", __func__, i, I2C_READ(I2CCR), cr, error)); 283 goto out; 284 } 285 } 286 287 if (cmdlen > 0 && I2C_OP_READ_P(op)) { 288 KASSERT(cr & CR_MTX); 289 KASSERT((cr & CR_TXAK) == 0); 290 I2C_WRITE(I2CCR, cr | CR_RSTA); 291 #if 0 292 DPRINTF(("%s: restarted(read): sr=%#x cr=%#x(%#x)\n", 293 __func__, I2C_READ(I2CSR), cr | CR_RSTA, I2C_READ(I2CCR))); 294 #endif 295 296 /* send target address and read transfer direction */ 297 addr_byte |= 1; 298 I2C_WRITE(I2CDR, addr_byte); 299 300 error = motoi2c_busy_wait(sc, cr); 301 if (error) { 302 if (error == EIO) 303 error = ENXIO; 304 goto out; 305 } 306 } 307 308 if (I2C_OP_READ_P(op)) { 309 uint8_t *dataptr = databuf; 310 cr &= ~CR_MTX; /* clear transmit flags */ 311 if (datalen <= 1) 312 cr |= CR_TXAK; 313 I2C_WRITE(I2CCR, cr); 314 DELAY(10); 315 (void)I2C_READ(I2CDR); /* dummy read */ 316 for (size_t i = 0; i < datalen; i++) { 317 /* 318 * If a master receiver wants to terminate a data 319 * transfer, it must inform the slave transmitter by 320 * not acknowledging the last byte of data (by setting 321 * the transmit acknowledge bit (I2CCR[TXAK])) before 322 * reading the next-to-last byte of data. 323 */ 324 error = motoi2c_busy_wait(sc, cr); 325 if (error) { 326 DPRINTF(("%s: error reading byte %zu: %d\n", 327 __func__, i, error)); 328 goto out; 329 } 330 if (i == datalen - 2) { 331 cr |= CR_TXAK; 332 I2C_WRITE(I2CCR, cr); 333 } else if (i == datalen - 1 && I2C_OP_STOP_P(op)) { 334 cr = sc->sc_enable_mask | CR_TXAK; 335 I2C_WRITE(I2CCR, cr); 336 } 337 *dataptr++ = I2C_READ(I2CDR); 338 } 339 if (datalen == 0) { 340 if (I2C_OP_STOP_P(op)) { 341 cr = sc->sc_enable_mask | CR_TXAK; 342 I2C_WRITE(I2CCR, cr); 343 } 344 (void)I2C_READ(I2CDR); /* dummy read */ 345 error = motoi2c_busy_wait(sc, cr); 346 if (error) { 347 DPRINTF(("%s: error reading dummy last byte:" 348 "%d\n", __func__, error)); 349 goto out; 350 } 351 } 352 } else { 353 const uint8_t *dataptr = databuf; 354 for (size_t i = 0; i < datalen; i++) { 355 I2C_WRITE(I2CDR, *dataptr++); 356 error = motoi2c_busy_wait(sc, cr); 357 if (error) { 358 DPRINTF(("%s: error sending data byte %zu:" 359 " %d\n", __func__, i, error)); 360 goto out; 361 } 362 } 363 } 364 365 out: 366 /* 367 * If we encountered an error condition or caller wants a STOP, 368 * send a STOP. 369 */ 370 if (error || (cr & CR_TXAK) || ((cr & CR_MSTA) && I2C_OP_STOP_P(op))) { 371 cr = sc->sc_enable_mask; 372 I2C_WRITE(I2CCR, cr); 373 motoi2c_stop_wait(sc); 374 DPRINTF(("%s: stopping: cr=%#x/%#x\n", __func__, 375 cr, I2C_READ(I2CCR))); 376 } 377 378 DPRINTF(("%s: exit sr=%#x cr=%#x: %d\n", __func__, 379 I2C_READ(I2CSR), I2C_READ(I2CCR), error)); 380 381 return error; 382 } 383
Indexes created Wed Sep 24 05:09:52 GMT 2025