mt2131.c revision 1.4.30.2
1 /* $NetBSD: mt2131.c,v 1.4.30.2 2017/08/28 17:52:03 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: mt2131.c,v 1.4.30.2 2017/08/28 17:52:03 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/syslog.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 40 #include <dev/i2c/mt2131var.h> 41 42 #define PWR 0x07 43 #define UPC_1 0x0b 44 #define AGC_RL 0x10 45 #define MISC_2 0x15 46 47 #define IF1 1220 48 #define IF2 44000 49 #define REF 16000 50 51 static const uint8_t mt2131_initstring[] = { 52 0x01, 53 0x50, 0x00, 0x50, 0x80, 0x00, 0x49, 54 0xfa, 0x88, 0x08, 0x77, 0x41, 0x04, 0x00, 0x00, 0x00, 0x32, 55 0x7f, 0xda, 0x4c, 0x00, 0x10, 0xaa, 0x78, 0x80, 0xff, 0x68, 56 0xa0, 0xff, 0xdd, 0x00, 0x00 57 }; 58 59 static const uint8_t mt2131_agcinitstring[] = { 60 AGC_RL, 61 0x7f, 0xc8, 0x0a, 0x5f, 0x00, 0x04 62 }; 63 64 65 struct mt2131_softc { 66 device_t parent; 67 i2c_tag_t tag; 68 i2c_addr_t addr; 69 uint32_t frequency; 70 uint32_t bandwidth; 71 }; 72 73 static int mt2131_init(struct mt2131_softc *); 74 75 static int mt2131_read(struct mt2131_softc *, uint8_t, uint8_t *); 76 static int mt2131_write(struct mt2131_softc *, uint8_t, uint8_t); 77 78 struct mt2131_softc * 79 mt2131_open(device_t parent, i2c_tag_t t, i2c_addr_t a) 80 { 81 struct mt2131_softc *sc; 82 int ret; 83 uint8_t cmd, reg; 84 85 cmd = reg = 0; 86 87 /* get id reg */ 88 iic_acquire_bus(t, I2C_F_POLL); 89 ret = iic_exec(t, I2C_OP_READ_WITH_STOP, a, &cmd, 1, ®, 1, I2C_F_POLL); 90 iic_release_bus(t, I2C_F_POLL); 91 92 if (ret) { 93 device_printf(parent, "%s(): read fail\n", __func__); 94 return NULL; 95 } 96 97 if ((reg & 0xfe) != 0x3e) { 98 device_printf(parent, "%s(): chip id %02x unknown\n", 99 __func__, reg); 100 return NULL; 101 } 102 103 sc = kmem_alloc(sizeof(*sc), KM_SLEEP); 104 sc->parent = parent; 105 sc->tag = t; 106 sc->addr = a; 107 108 mt2131_init(sc); 109 110 return sc; 111 } 112 113 void 114 mt2131_close(struct mt2131_softc *sc) 115 { 116 kmem_free(sc, sizeof(*sc)); 117 } 118 119 int 120 mt2131_tune_dtv(struct mt2131_softc *sc, const struct dvb_frontend_parameters *p) 121 { 122 int rv, i; 123 uint64_t o1, o2; 124 uint64_t d1, d2; 125 uint32_t r1, r2; 126 uint32_t fr; 127 uint8_t b[7]; 128 uint8_t regval; 129 130 mt2131_init(sc); 131 132 b[0] = 0x01; 133 134 if(p->frequency != 0 && 135 (p->frequency < 50000000 || p->frequency > 1000000000)) 136 return EINVAL; 137 138 fr = p->frequency / 1000; 139 140 o1 = fr + IF1 * 1000; 141 o2 = o1 - fr - IF2; 142 143 d1 = (o1 * 8192)/REF; 144 d2 = (o2 * 8192)/REF; 145 146 r1 = d1/8192; 147 r2 = d2/8192; 148 149 b[1] = (d1 & 0x1fe0) >> 5; 150 b[2] = (d1 & 0x001f); 151 b[3] = r1; 152 b[4] = (d2 & 0x1fe0) >> 5; 153 b[5] = (d2 & 0x001f); 154 b[6] = r2; 155 156 iic_acquire_bus(sc->tag, I2C_F_POLL); 157 rv = iic_exec(sc->tag, I2C_OP_WRITE_WITH_STOP, sc->addr, b, 7, NULL, 0, I2C_F_POLL); 158 iic_release_bus(sc->tag, I2C_F_POLL); 159 160 regval = (fr - 27501) / 55000; 161 162 if(regval > 0x13) 163 regval = 0x13; 164 165 rv = mt2131_write(sc, UPC_1, regval); 166 167 if (rv != 0) 168 device_printf(sc->parent, "%s write failed\n", __func__); 169 170 sc->frequency = (o1 - o2 - IF2) * 1000; 171 172 for (i = 0; i < 100; i++) { 173 kpause("mt2131", true, 1, NULL); 174 175 rv = mt2131_read(sc, 0x08, ®val); 176 if (rv != 0) 177 device_printf(sc->parent, "%s read failed\n", __func__); 178 179 if (( regval & 0x88 ) == 0x88 ) { 180 return 0; 181 } 182 } 183 184 device_printf(sc->parent, "mt2131 not locked, %02x\n", b[1]); 185 186 return rv; 187 } 188 189 static int 190 mt2131_init(struct mt2131_softc *sc) 191 { 192 int ret; 193 194 ret = iic_acquire_bus(sc->tag, I2C_F_POLL); 195 if (ret) 196 return -1; 197 ret = iic_exec(sc->tag, I2C_OP_WRITE_WITH_STOP, sc->addr, 198 mt2131_initstring, sizeof(mt2131_initstring), NULL, 0, I2C_F_POLL); 199 if (ret) 200 return -1; 201 iic_release_bus(sc->tag, I2C_F_POLL); 202 203 ret = mt2131_write(sc, UPC_1, 0x09); 204 ret = mt2131_write(sc, MISC_2, 0x47); 205 ret = mt2131_write(sc, PWR, 0xf2); 206 ret = mt2131_write(sc, UPC_1, 0x01); 207 208 ret = iic_acquire_bus(sc->tag, I2C_F_POLL); 209 if (ret) 210 return -1; 211 ret = iic_exec(sc->tag, I2C_OP_WRITE_WITH_STOP, sc->addr, 212 mt2131_agcinitstring, sizeof(mt2131_agcinitstring), 213 NULL, 0, I2C_F_POLL); 214 iic_release_bus(sc->tag, I2C_F_POLL); 215 if (ret) 216 return -1; 217 218 return 0; 219 } 220 221 static int 222 mt2131_read(struct mt2131_softc *sc, uint8_t r, uint8_t *v) 223 { 224 int ret; 225 226 ret = iic_acquire_bus(sc->tag, I2C_F_POLL); 227 if (ret) 228 return ret; 229 ret = iic_exec(sc->tag, I2C_OP_READ_WITH_STOP, sc->addr, 230 &r, 1, v, 1, I2C_F_POLL); 231 232 iic_release_bus(sc->tag, I2C_F_POLL); 233 234 return ret; 235 } 236 237 static int 238 mt2131_write(struct mt2131_softc *sc, uint8_t a, uint8_t v) 239 { 240 int ret; 241 uint8_t b[] = { a, v }; 242 243 ret = iic_acquire_bus(sc->tag, I2C_F_POLL); 244 if (ret) 245 return ret; 246 247 ret = iic_exec(sc->tag, I2C_OP_READ_WITH_STOP, sc->addr, 248 b, sizeof(b), NULL, 0, I2C_F_POLL); 249 250 iic_release_bus(sc->tag, I2C_F_POLL); 251 252 return ret; 253 } 254 255 MODULE(MODULE_CLASS_DRIVER, mt2131, "i2cexec"); 256 257 static int 258 mt2131_modcmd(modcmd_t cmd, void *priv) 259 { 260 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 261 return 0; 262 return ENOTTY; 263 } 264
Indexes created Mon Oct 20 20:10:13 GMT 2025