pca9685.c revision 1.4 1 /* $NetBSD: pca9685.c,v 1.4 2021/01/17 21:42:35 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018, 2019 Jason R. Thorpe
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: pca9685.c,v 1.4 2021/01/17 21:42:35 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/mutex.h>
36
37 #include <dev/i2c/i2cvar.h>
38 #include <dev/i2c/pca9685reg.h>
39
40 #include <dev/pwm/pwmvar.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 /*
45 * Special channel number used to indicate that we want to set the
46 * pulse mode for all channels on this controller.
47 */
48 #define PCA9685_ALL_CHANNELS PCA9685_NCHANNELS
49
50 struct pcapwm_channel {
51 struct pwm_controller ch_controller;
52 struct pwm_config ch_conf;
53 u_int ch_number;
54 };
55
56 struct pcapwm_softc {
57 device_t sc_dev;
58 i2c_tag_t sc_i2c;
59 i2c_addr_t sc_addr;
60
61 /*
62 * Locking order is:
63 * pcapwm mutex -> i2c bus
64 */
65 kmutex_t sc_lock;
66
67 /*
68 * The PCA9685 only has a single pre-scaler, so the configured
69 * PWM frequency / period is shared by all channels.
70 */
71 u_int sc_period; /* nanoseconds */
72 u_int sc_clk_freq;
73 bool sc_ext_clk;
74 bool sc_invert; /* "invert" property specified */
75 bool sc_open_drain; /* "open-drain" property specified */
76
77 /*
78 * +1 because we treat channel "16" as the all-channels
79 * pseudo-channel.
80 */
81 struct pcapwm_channel sc_channels[PCA9685_NCHANNELS+1];
82 };
83
84 static int pcapwm_pwm_enable(struct pwm_controller *, bool);
85 static int pcapwm_pwm_get_config(struct pwm_controller *,
86 struct pwm_config *);
87 static int pcapwm_pwm_set_config(struct pwm_controller *,
88 const struct pwm_config *);
89
90 static const struct device_compatible_entry compat_data[] = {
91 { .compat = "nxp,pca9685-pwm" },
92
93 { 0 }
94 };
95
96 static int
97 pcapwm_read1(struct pcapwm_softc * const sc, uint8_t reg, uint8_t *valp)
98 {
99
100 return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP,
101 sc->sc_addr, ®, sizeof(reg),
102 valp, sizeof(*valp), 0);
103 }
104
105 static int
106 pcapwm_write1(struct pcapwm_softc * const sc, uint8_t reg, uint8_t val)
107 {
108
109 return iic_exec(sc->sc_i2c, I2C_OP_WRITE_WITH_STOP,
110 sc->sc_addr, ®, sizeof(reg),
111 &val, sizeof(val), 0);
112 }
113
114 static int
115 pcapwm_read_LEDn(struct pcapwm_softc * const sc, uint8_t reg, uint8_t *buf,
116 size_t buflen)
117 {
118
119 /* We rely on register auto-increment being enabled. */
120 return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP,
121 sc->sc_addr, ®, sizeof(reg),
122 buf, buflen, 0);
123 }
124
125 static int
126 pcapwm_write_LEDn(struct pcapwm_softc * const sc, uint8_t reg, uint8_t *buf,
127 size_t buflen)
128 {
129
130 /* We rely on register auto-increment being enabled. */
131 return iic_exec(sc->sc_i2c, I2C_OP_WRITE_WITH_STOP,
132 sc->sc_addr, ®, sizeof(reg),
133 buf, buflen, 0);
134 }
135
136 static int
137 pcapwm_program_channel(struct pcapwm_softc * const sc,
138 struct pcapwm_channel * const chan,
139 uint16_t on_tick, uint16_t off_tick)
140 {
141 const uint8_t reg = chan->ch_number == PCA9685_ALL_CHANNELS ?
142 PCA9685_ALL_LED_ON_L : PCA9685_LEDx_ON_L(chan->ch_number);
143 uint8_t regs[4];
144 int error;
145
146 regs[0] = (uint8_t)(on_tick & 0xff);
147 regs[1] = (uint8_t)((on_tick >> 8) & 0xff);
148 regs[2] = (uint8_t)(off_tick & 0xff);
149 regs[3] = (uint8_t)((off_tick >> 8) & 0xff);
150
151 error = iic_acquire_bus(sc->sc_i2c, 0);
152 if (error) {
153 device_printf(sc->sc_dev,
154 "program_channel: failed to acquire I2C bus\n");
155 return error;
156 }
157
158 error = pcapwm_write_LEDn(sc, reg, regs, sizeof(regs));
159
160 iic_release_bus(sc->sc_i2c, 0);
161
162 return error;
163 }
164
165 static int
166 pcapwm_inspect_channel(struct pcapwm_softc * const sc,
167 struct pcapwm_channel * const chan,
168 uint16_t *on_tickp, uint16_t *off_tickp)
169 {
170 const uint8_t reg = chan->ch_number == PCA9685_ALL_CHANNELS ?
171 PCA9685_ALL_LED_ON_L : PCA9685_LEDx_ON_L(chan->ch_number);
172 uint8_t regs[4];
173 int error;
174
175 error = iic_acquire_bus(sc->sc_i2c, 0);
176 if (error) {
177 device_printf(sc->sc_dev,
178 "inspect_channel: failed to acquire I2C bus\n");
179 return error;
180 }
181
182 error = pcapwm_read_LEDn(sc, reg, regs, sizeof(regs));
183
184 iic_release_bus(sc->sc_i2c, 0);
185
186 if (error) {
187 return error;
188 }
189
190 *on_tickp = regs[0] | (((uint16_t)regs[1]) << 8);
191 *off_tickp = regs[2] | (((uint16_t)regs[3]) << 8);
192
193 return 0;
194 }
195
196 static struct pcapwm_channel *
197 pcapwm_lookup_channel(struct pcapwm_softc * const sc, u_int index)
198 {
199
200 if (index > PCA9685_ALL_CHANNELS)
201 return NULL;
202
203 return &sc->sc_channels[index];
204 }
205
206 static void
207 pcapwm_init_channel(struct pcapwm_softc * const sc, u_int index)
208 {
209 struct pcapwm_channel * const chan = pcapwm_lookup_channel(sc, index);
210
211 KASSERT(chan != NULL);
212
213 chan->ch_number = index;
214
215 chan->ch_controller.pwm_enable = pcapwm_pwm_enable;
216 chan->ch_controller.pwm_get_config = pcapwm_pwm_get_config;
217 chan->ch_controller.pwm_set_config = pcapwm_pwm_set_config;
218
219 chan->ch_controller.pwm_dev = sc->sc_dev;
220 chan->ch_controller.pwm_priv = chan;
221 }
222
223 static pwm_tag_t
224 pcapwm_get_tag(device_t dev, const void *data, size_t len)
225 {
226 struct pcapwm_softc * const sc = device_private(dev);
227 const u_int *pwm = data;
228
229 /* #pwm-cells == 2 in the PCA9685 DT bindings. */
230 if (len != 12)
231 return NULL;
232
233 /* Channel 16 is the special call-channels channel. */
234 const u_int index = be32toh(pwm[1]);
235 struct pcapwm_channel * const chan = pcapwm_lookup_channel(sc, index);
236 if (chan == NULL)
237 return NULL;
238
239 const u_int period = be32toh(pwm[2]);
240
241 mutex_enter(&sc->sc_lock);
242
243 /*
244 * XXX Should we reflect the value of the "invert" property in
245 * pwm_config::polarity? I'm thinking not, but...
246 */
247 chan->ch_conf.period = period;
248 chan->ch_conf.polarity = PWM_ACTIVE_HIGH;
249
250 mutex_exit(&sc->sc_lock);
251
252 return &chan->ch_controller;
253 }
254
255 static struct fdtbus_pwm_controller_func pcapwm_pwm_funcs = {
256 .get_tag = pcapwm_get_tag,
257 };
258
259 static int
260 pcapwm_pwm_enable(pwm_tag_t pwm, bool enable)
261 {
262 struct pcapwm_softc * const sc = device_private(pwm->pwm_dev);
263 struct pcapwm_channel * const chan = pwm->pwm_priv;
264 int error;
265
266 if (enable) {
267 /* Set whatever is programmed for the channel. */
268 error = pwm_set_config(pwm, &chan->ch_conf);
269 if (error) {
270 device_printf(sc->sc_dev,
271 "enable: unable to set config for channel %u\n",
272 chan->ch_number);
273 }
274 return error;
275 }
276
277 mutex_enter(&sc->sc_lock);
278
279 error = pcapwm_program_channel(sc, chan, 0, PCA9685_PWM_TICKS);
280 if (error) {
281 device_printf(sc->sc_dev,
282 "disable: unable to program channel %u\n",
283 chan->ch_number);
284 }
285
286 mutex_exit(&sc->sc_lock);
287
288 return error;
289 }
290
291 static int
292 pcapwm_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf)
293 {
294 struct pcapwm_softc * const sc = device_private(pwm->pwm_dev);
295 struct pcapwm_channel * const chan = pwm->pwm_priv;
296 uint16_t on_tick, off_tick;
297 u_int duty_cycle;
298 int error;
299
300 mutex_enter(&sc->sc_lock);
301
302 error = pcapwm_inspect_channel(sc, chan, &on_tick, &off_tick);
303 if (error) {
304 device_printf(sc->sc_dev,
305 "get_config: unable to inspect channel %u\n",
306 chan->ch_number);
307 goto out;
308 }
309
310 if (on_tick & PCA9685_PWM_TICKS) {
311 duty_cycle = chan->ch_conf.period;
312 } else if (off_tick & PCA9685_PWM_TICKS) {
313 duty_cycle = 0;
314 } else {
315 /*
316 * Compute the number of ticks, accounting for a non-zero
317 * on-tick (which the hardware can do, even if the software
318 * can't).
319 */
320 int signed_off_tick = off_tick;
321 signed_off_tick -= on_tick;
322 if (signed_off_tick < 0)
323 signed_off_tick += PCA9685_PWM_TICKS;
324 const uint64_t nticks = signed_off_tick;
325 duty_cycle = (u_int)((nticks * chan->ch_conf.period) /
326 PCA9685_PWM_TICKS);
327 }
328
329 *conf = chan->ch_conf;
330 conf->duty_cycle = duty_cycle;
331
332 out:
333 mutex_exit(&sc->sc_lock);
334
335 return error;
336 }
337
338 static int
339 pcapwm_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf)
340 {
341 struct pcapwm_softc * const sc = device_private(pwm->pwm_dev);
342 struct pcapwm_channel * const chan = pwm->pwm_priv;
343 int error = 0;
344
345 mutex_enter(&sc->sc_lock);
346
347 /* Only active-high is supported. */
348 if (conf->polarity != PWM_ACTIVE_HIGH) {
349 device_printf(sc->sc_dev,
350 "set_config: invalid polarity: %d\n", conf->polarity);
351 error = EINVAL;
352 goto out;
353 }
354
355 if (sc->sc_period != conf->period) {
356 /*
357 * Formula for the prescale is:
358 *
359 * ( clk_freq )
360 * round( ----------------- ) - 1
361 * ( 4096 * pwm_freq )
362 *
363 * pwm_freq == 1000000000 / period.
364 *
365 * To do the rounding step, we scale the oscillator_freq
366 * by 100, check for the rounding condition, and then
367 * de-scale before the subtraction step.
368 */
369 const u_int pwm_freq = 1000000000 / conf->period;
370 u_int prescale = (sc->sc_clk_freq * 100) /
371 (PCA9685_PWM_TICKS * pwm_freq);
372 if ((prescale % 100) >= 50)
373 prescale += 100;
374 prescale = (prescale / 100) - 1;
375 if (prescale < PCA9685_PRESCALE_MIN ||
376 prescale > PCA9685_PRESCALE_MAX) {
377 device_printf(sc->sc_dev,
378 "set_config: invalid period: %uns\n", conf->period);
379 error = EINVAL;
380 goto out;
381 }
382
383 error = iic_acquire_bus(sc->sc_i2c, 0);
384 if (error) {
385 device_printf(sc->sc_dev,
386 "set_config: unable to acquire I2C bus\n");
387 goto out;
388 }
389
390 uint8_t mode1;
391 error = pcapwm_read1(sc, PCA9685_MODE1, &mode1);
392 if (error) {
393 device_printf(sc->sc_dev,
394 "set_config: unable to read MODE1\n");
395 goto out_release_i2c;
396 }
397
398 /* Disable the internal oscillator. */
399 mode1 |= MODE1_SLEEP;
400 error = pcapwm_write1(sc, PCA9685_MODE1, mode1);
401 if (error) {
402 device_printf(sc->sc_dev,
403 "set_config: unable to write MODE1\n");
404 goto out_release_i2c;
405 }
406
407 /* Update the prescale register. */
408 error = pcapwm_write1(sc, PCA9685_PRE_SCALE,
409 (uint8_t)(prescale & 0xff));
410 if (error) {
411 device_printf(sc->sc_dev,
412 "set_config: unable to write PRE_SCALE\n");
413 goto out_release_i2c;
414 }
415
416 /*
417 * If we're using an external clock source, keep the
418 * internal oscillator turned off.
419 *
420 * XXX The datasheet is a little ambiguous about how this
421 * XXX is supposed to work -- on the same page it says to
422 * XXX perform this procedure, and also that PWM control of
423 * XXX the channels is not possible when the oscillator is
424 * XXX disabled. I haven't tested this with an external
425 * XXX oscillator yet, so I don't know for sure.
426 */
427 if (sc->sc_ext_clk) {
428 mode1 |= MODE1_EXTCLK;
429 } else {
430 mode1 &= ~MODE1_SLEEP;
431 }
432
433 /*
434 * We rely on auto-increment for the PWM register updates.
435 */
436 mode1 |= MODE1_AI;
437
438 error = pcapwm_write1(sc, PCA9685_MODE1, mode1);
439 if (error) {
440 device_printf(sc->sc_dev,
441 "set_config: unable to write MODE1\n");
442 goto out_release_i2c;
443 }
444
445 iic_release_bus(sc->sc_i2c, 0);
446
447 if (sc->sc_ext_clk == false) {
448 /* Wait for 500us for the clock to settle. */
449 delay(500);
450 }
451
452 sc->sc_period = conf->period;
453 }
454
455 uint16_t on_tick, off_tick;
456
457 /*
458 * The PWM framework doesn't support the phase-shift / start-delay
459 * feature of this chip, so all duty cycles start at 0 ticks.
460 */
461
462 /*
463 * For full-on and full-off, use the magic FULL-{ON,OFF} values
464 * described in the data sheet.
465 */
466 if (conf->duty_cycle == 0) {
467 on_tick = 0;
468 off_tick = PCA9685_PWM_TICKS;
469 } else if (conf->duty_cycle == sc->sc_period) {
470 on_tick = PCA9685_PWM_TICKS;
471 off_tick = 0;
472 } else {
473 uint64_t ticks =
474 PCA9685_PWM_TICKS * (uint64_t)conf->duty_cycle;
475 /* Scale up so we can check if we need to round. */
476 ticks = (ticks * 100) / sc->sc_period;
477 /* Round up. */
478 if (ticks % 100)
479 ticks += 100;
480 ticks /= 100;
481 if (ticks >= PCA9685_PWM_TICKS) {
482 ticks = PCA9685_PWM_TICKS - 1;
483 }
484
485 on_tick = 0;
486 off_tick = (u_int)ticks;
487 }
488
489 error = pcapwm_program_channel(sc, chan, on_tick, off_tick);
490 if (error) {
491 device_printf(sc->sc_dev,
492 "set_config: unable to program channel %u\n",
493 chan->ch_number);
494 goto out;
495 }
496
497 chan->ch_conf = *conf;
498
499 out:
500 mutex_exit(&sc->sc_lock);
501
502 return error;
503
504 out_release_i2c:
505 iic_release_bus(sc->sc_i2c, 0);
506 goto out;
507 }
508
509 static int
510 pcapwm_match(device_t parent, cfdata_t cf, void *aux)
511 {
512 struct i2c_attach_args * const ia = aux;
513 int match_result;
514
515 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) {
516 return match_result;
517 }
518
519 /* This device is direct-config only. */
520
521 return 0;
522 }
523
524 static void
525 pcapwm_attach(device_t parent, device_t self, void *aux)
526 {
527 struct pcapwm_softc * const sc = device_private(self);
528 struct i2c_attach_args * const ia = aux;
529 struct clk *clk;
530 const int phandle = (int)ia->ia_cookie;
531 u_int index;
532 int error;
533
534 sc->sc_dev = self;
535 sc->sc_i2c = ia->ia_tag;
536 sc->sc_addr = ia->ia_addr;
537
538 aprint_naive("\n");
539 aprint_normal(": PCA9685 PWM controller\n");
540
541 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
542
543 for (index = 0; index <= PCA9685_ALL_CHANNELS; index++) {
544 pcapwm_init_channel(sc, index);
545 }
546
547 clk = fdtbus_clock_get_index(phandle, 0);
548 if (clk != NULL) {
549 sc->sc_ext_clk = true;
550 sc->sc_clk_freq = clk_get_rate(clk);
551 } else {
552 sc->sc_clk_freq = PCA9685_INTERNAL_FREQ;
553 }
554
555 if (of_hasprop(phandle, "invert")) {
556 sc->sc_invert = true;
557 }
558
559 if (of_hasprop(phandle, "open-drain")) {
560 sc->sc_open_drain = true;
561 }
562
563 /*
564 * XXX No DT bindings for the OUTNEx configurations in
565 * MODE2.
566 */
567
568 error = iic_acquire_bus(sc->sc_i2c, 0);
569 if (error) {
570 aprint_error_dev(sc->sc_dev, "failed to acquire I2C bus\n");
571 return;
572 }
573
574 /*
575 * Set up the outputs. We want the channel to update when
576 * we send the I2C "STOP" condition.
577 */
578 uint8_t mode2;
579 error = pcapwm_read1(sc, PCA9685_MODE2, &mode2);
580 if (error == 0) {
581 mode2 &= ~(MODE2_OUTDRV | MODE2_OCH | MODE2_INVRT);
582 if (sc->sc_invert) {
583 mode2 |= MODE2_INVRT;
584 }
585 if (sc->sc_open_drain == false) {
586 mode2 |= MODE2_OUTDRV;
587 }
588 error = pcapwm_write1(sc, PCA9685_MODE2, mode2);
589 }
590 iic_release_bus(sc->sc_i2c, 0);
591 if (error) {
592 aprint_error_dev(sc->sc_dev, "failed to configure MODE2\n");
593 return;
594 }
595
596 fdtbus_register_pwm_controller(self, phandle,
597 &pcapwm_pwm_funcs);
598 }
599
600 CFATTACH_DECL_NEW(pcapwm, sizeof(struct pcapwm_softc),
601 pcapwm_match, pcapwm_attach, NULL, NULL);
602