rkpmic.c revision 1.5
1 /* $NetBSD: rkpmic.c,v 1.5 2019/09/18 15:12:37 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rkpmic.c,v 1.5 2019/09/18 15:12:37 tnn Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/kmem.h> 39 40 #include <dev/clock_subr.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #define SECONDS_REG 0x00 47 #define MINUTES_REG 0x01 48 #define HOURS_REG 0x02 49 #define DAYS_REG 0x03 50 #define MONTHS_REG 0x04 51 #define YEARS_REG 0x05 52 #define WEEKS_REG 0x06 53 54 #define RTC_CTRL_REG 0x10 55 #define RTC_CTRL_READSEL __BIT(7) 56 #define RTC_CTRL_GET_TIME __BIT(6) 57 #define RTC_CTRL_SET_32_COUNTER __BIT(5) 58 #define RTC_CTRL_TEST_MODE __BIT(4) 59 #define RTC_CTRL_AMPM_MODE __BIT(3) 60 #define RTC_CTRL_AUTO_COMP __BIT(2) 61 #define RTC_CTRL_ROUND_30S __BIT(1) 62 #define RTC_CTRL_STOP_RTC __BIT(0) 63 64 #define RTC_INT_REG 0x12 65 #define RTC_COMP_LSB_REG 0x13 66 #define RTC_COMP_MSB_REG 0x14 67 #define CHIP_NAME_REG 0x17 68 #define CHIP_VER_REG 0x18 69 70 struct rkpmic_ctrl { 71 const char * name; 72 uint8_t enable_reg; 73 uint8_t enable_mask; 74 uint8_t vsel_reg; 75 uint8_t vsel_mask; 76 u_int base; 77 u_int step; 78 u_int flags; 79 #define F_ENABLE_WRITE_MASK 0x00 80 }; 81 82 struct rkpmic_config { 83 const char * name; 84 const struct rkpmic_ctrl *ctrl; 85 u_int nctrl; 86 }; 87 88 static const struct rkpmic_ctrl rk805_ctrls[] = { 89 /* DCDC */ 90 { .name = "DCDC_REG1", .flags = F_ENABLE_WRITE_MASK, 91 .enable_reg = 0x23, .enable_mask = __BIT(0), 92 .vsel_reg = 0x2f, .vsel_mask = __BITS(5,0), 93 .base = 712500, .step = 12500 }, 94 { .name = "DCDC_REG2", .flags = F_ENABLE_WRITE_MASK, 95 .enable_reg = 0x23, .enable_mask = __BIT(1), 96 .vsel_reg = 0x33, .vsel_mask = __BITS(5,0), 97 .base = 712500, .step = 12500 }, 98 { .name = "DCDC_REG3", .flags = F_ENABLE_WRITE_MASK, 99 .enable_reg = 0x23, .enable_mask = __BIT(2) }, 100 { .name = "DCDC_REG4", .flags = F_ENABLE_WRITE_MASK, 101 .enable_reg = 0x23, .enable_mask = __BIT(3), 102 .vsel_reg = 0x38, .vsel_mask = __BITS(3,0), 103 .base = 800000, .step = 100000 }, 104 105 /* LDO */ 106 { .name = "LDO_REG1", .flags = F_ENABLE_WRITE_MASK, 107 .enable_reg = 0x27, .enable_mask = __BIT(0), 108 .vsel_reg = 0x3b, .vsel_mask = __BITS(4,0), 109 .base = 800000, .step = 100000 }, 110 { .name = "LDO_REG2", .flags = F_ENABLE_WRITE_MASK, 111 .enable_reg = 0x27, .enable_mask = __BIT(1), 112 .vsel_reg = 0x3d, .vsel_mask = __BITS(4,0), 113 .base = 800000, .step = 100000 }, 114 { .name = "LDO_REG3", .flags = F_ENABLE_WRITE_MASK, 115 .enable_reg = 0x27, .enable_mask = __BIT(2), 116 .vsel_reg = 0x3f, .vsel_mask = __BITS(4,0), 117 .base = 800000, .step = 100000 }, 118 }; 119 120 static const struct rkpmic_config rk805_config = { 121 .name = "RK805", 122 .ctrl = rk805_ctrls, 123 .nctrl = __arraycount(rk805_ctrls), 124 }; 125 126 static const struct rkpmic_ctrl rk808_ctrls[] = { 127 /* DCDC */ 128 { .name = "DCDC_REG1", 129 .enable_reg = 0x23, .enable_mask = __BIT(0), 130 .vsel_reg = 0x2f, .vsel_mask = __BITS(5,0), 131 .base = 712500, .step = 12500 }, 132 { .name = "DCDC_REG2", 133 .enable_reg = 0x23, .enable_mask = __BIT(1), 134 .vsel_reg = 0x33, .vsel_mask = __BITS(5,0), 135 .base = 712500, .step = 12500 }, 136 { .name = "DCDC_REG3", 137 .enable_reg = 0x23, .enable_mask = __BIT(2) }, 138 { .name = "DCDC_REG4", 139 .enable_reg = 0x23, .enable_mask = __BIT(3), 140 .vsel_reg = 0x38, .vsel_mask = __BITS(3,0), 141 .base = 1800000, .step = 100000 }, 142 143 /* LDO */ 144 { .name = "LDO_REG1", 145 .enable_reg = 0x24, .enable_mask = __BIT(0), 146 .vsel_reg = 0x3b, .vsel_mask = __BITS(4,0), 147 .base = 1800000, .step = 100000 }, 148 { .name = "LDO_REG2", 149 .enable_reg = 0x24, .enable_mask = __BIT(1), 150 .vsel_reg = 0x3d, .vsel_mask = __BITS(4,0), 151 .base = 1800000, .step = 100000 }, 152 { .name = "LDO_REG3", 153 .enable_reg = 0x24, .enable_mask = __BIT(2), 154 .vsel_reg = 0x3f, .vsel_mask = __BITS(3,0), 155 .base = 800000, .step = 100000 }, 156 { .name = "LDO_REG4", 157 .enable_reg = 0x24, .enable_mask = __BIT(3), 158 .vsel_reg = 0x41, .vsel_mask = __BITS(4,0), 159 .base = 1800000, .step = 100000 }, 160 { .name = "LDO_REG5", 161 .enable_reg = 0x24, .enable_mask = __BIT(4), 162 .vsel_reg = 0x43, .vsel_mask = __BITS(4,0), 163 .base = 1800000, .step = 100000 }, 164 { .name = "LDO_REG6", 165 .enable_reg = 0x24, .enable_mask = __BIT(5), 166 .vsel_reg = 0x45, .vsel_mask = __BITS(4,0), 167 .base = 800000, .step = 100000 }, 168 { .name = "LDO_REG7", 169 .enable_reg = 0x24, .enable_mask = __BIT(6), 170 .vsel_reg = 0x47, .vsel_mask = __BITS(4,0), 171 .base = 800000, .step = 100000 }, 172 { .name = "LDO_REG8", 173 .enable_reg = 0x24, .enable_mask = __BIT(7), 174 .vsel_reg = 0x49, .vsel_mask = __BITS(4,0), 175 .base = 1800000, .step = 100000 }, 176 177 /* SWITCH */ 178 { .name = "SWITCH_REG1", 179 .enable_reg = 0x23, .enable_mask = __BIT(5) }, 180 { .name = "SWITCH_REG2", 181 .enable_reg = 0x23, .enable_mask = __BIT(6) }, 182 }; 183 184 static const struct rkpmic_config rk808_config = { 185 .name = "RK808", 186 .ctrl = rk808_ctrls, 187 .nctrl = __arraycount(rk808_ctrls), 188 }; 189 190 struct rkpmic_softc { 191 device_t sc_dev; 192 i2c_tag_t sc_i2c; 193 i2c_addr_t sc_addr; 194 int sc_phandle; 195 struct todr_chip_handle sc_todr; 196 struct rkpmic_config *sc_conf; 197 }; 198 199 struct rkreg_softc { 200 device_t sc_dev; 201 struct rkpmic_softc *sc_pmic; 202 const struct rkpmic_ctrl *sc_ctrl; 203 }; 204 205 struct rkreg_attach_args { 206 const struct rkpmic_ctrl *reg_ctrl; 207 int reg_phandle; 208 }; 209 210 static const struct device_compatible_entry compat_data[] = { 211 { "rockchip,rk805", (uintptr_t)&rk805_config }, 212 { "rockchip,rk808", (uintptr_t)&rk808_config }, 213 { NULL } 214 }; 215 216 static uint8_t 217 rkpmic_read(struct rkpmic_softc *sc, uint8_t reg, int flags) 218 { 219 uint8_t val = 0; 220 int error; 221 222 error = iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, &val, flags); 223 if (error != 0) 224 device_printf(sc->sc_dev, "error reading reg %#x: %d\n", reg, error); 225 226 return val; 227 } 228 229 static void 230 rkpmic_write(struct rkpmic_softc *sc, uint8_t reg, uint8_t val, int flags) 231 { 232 int error; 233 234 error = iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, flags); 235 if (error != 0) 236 device_printf(sc->sc_dev, "error writing reg %#x: %d\n", reg, error); 237 } 238 239 #define I2C_READ(sc, reg) rkpmic_read((sc), (reg), I2C_F_POLL) 240 #define I2C_WRITE(sc, reg, val) rkpmic_write((sc), (reg), (val), I2C_F_POLL) 241 #define I2C_LOCK(sc) iic_acquire_bus((sc)->sc_i2c, I2C_F_POLL) 242 #define I2C_UNLOCK(sc) iic_release_bus((sc)->sc_i2c, I2C_F_POLL) 243 244 static int 245 rkpmic_todr_settime(todr_chip_handle_t ch, struct clock_ymdhms *dt) 246 { 247 struct rkpmic_softc * const sc = ch->cookie; 248 uint8_t val; 249 250 if (dt->dt_year < 2000 || dt->dt_year >= 2100) { 251 device_printf(sc->sc_dev, "year out of range\n"); 252 return EINVAL; 253 } 254 255 if (I2C_LOCK(sc)) 256 return EBUSY; 257 258 val = I2C_READ(sc, RTC_CTRL_REG); 259 I2C_WRITE(sc, RTC_CTRL_REG, val | RTC_CTRL_STOP_RTC); 260 I2C_WRITE(sc, SECONDS_REG, bintobcd(dt->dt_sec)); 261 I2C_WRITE(sc, MINUTES_REG, bintobcd(dt->dt_min)); 262 I2C_WRITE(sc, HOURS_REG, bintobcd(dt->dt_hour)); 263 I2C_WRITE(sc, DAYS_REG, bintobcd(dt->dt_day)); 264 I2C_WRITE(sc, MONTHS_REG, bintobcd(dt->dt_mon)); 265 I2C_WRITE(sc, YEARS_REG, bintobcd(dt->dt_year % 100)); 266 I2C_WRITE(sc, WEEKS_REG, bintobcd(dt->dt_wday == 0 ? 7 : dt->dt_wday)); 267 I2C_WRITE(sc, RTC_CTRL_REG, val); 268 I2C_UNLOCK(sc); 269 270 return 0; 271 } 272 273 static int 274 rkpmic_todr_gettime(todr_chip_handle_t ch, struct clock_ymdhms *dt) 275 { 276 struct rkpmic_softc * const sc = ch->cookie; 277 uint8_t val; 278 279 if (I2C_LOCK(sc)) 280 return EBUSY; 281 282 val = I2C_READ(sc, RTC_CTRL_REG); 283 I2C_WRITE(sc, RTC_CTRL_REG, val | RTC_CTRL_GET_TIME | RTC_CTRL_READSEL); 284 delay(1000000 / 32768); /* wait one cycle for shadow regs to latch */ 285 I2C_WRITE(sc, RTC_CTRL_REG, val | RTC_CTRL_READSEL); 286 dt->dt_sec = bcdtobin(I2C_READ(sc, SECONDS_REG)); 287 dt->dt_min = bcdtobin(I2C_READ(sc, MINUTES_REG)); 288 dt->dt_hour = bcdtobin(I2C_READ(sc, HOURS_REG)); 289 dt->dt_day = bcdtobin(I2C_READ(sc, DAYS_REG)); 290 dt->dt_mon = bcdtobin(I2C_READ(sc, MONTHS_REG)); 291 dt->dt_year = 2000 + bcdtobin(I2C_READ(sc, YEARS_REG)); 292 dt->dt_wday = bcdtobin(I2C_READ(sc, WEEKS_REG)); 293 if (dt->dt_wday == 7) 294 dt->dt_wday = 0; 295 I2C_WRITE(sc, RTC_CTRL_REG, val); 296 I2C_UNLOCK(sc); 297 298 /* 299 * RK808 has a hw bug which makes the 31st of November a valid day. 300 * If we detect the 31st of November we skip ahead one day. 301 * If the system has been turned off during the crossover the clock 302 * will have lost a day. No easy way to detect this. Oh well. 303 */ 304 if (dt->dt_mon == 11 && dt->dt_day == 31) { 305 dt->dt_day--; 306 clock_secs_to_ymdhms(clock_ymdhms_to_secs(dt) + 86400, dt); 307 rkpmic_todr_settime(ch, dt); 308 } 309 310 #if 0 311 device_printf(sc->sc_dev, "%04" PRIu64 "-%02u-%02u (%u) %02u:%02u:%02u\n", 312 dt->dt_year, dt->dt_mon, dt->dt_day, dt->dt_wday, 313 dt->dt_hour, dt->dt_min, dt->dt_sec); 314 #endif 315 316 return 0; 317 } 318 319 320 static int 321 rkpmic_match(device_t parent, cfdata_t match, void *aux) 322 { 323 struct i2c_attach_args *ia = aux; 324 int match_result; 325 326 if (iic_use_direct_match(ia, match, compat_data, &match_result)) 327 return match_result; 328 329 return 0; 330 } 331 332 static void 333 rkpmic_attach(device_t parent, device_t self, void *aux) 334 { 335 struct rkpmic_softc * const sc = device_private(self); 336 struct i2c_attach_args *ia = aux; 337 struct rkreg_attach_args raa; 338 const struct device_compatible_entry *entry; 339 int child, regulators; 340 u_int chipid, n; 341 342 iic_compatible_match(ia, compat_data, &entry); 343 344 sc->sc_dev = self; 345 sc->sc_i2c = ia->ia_tag; 346 sc->sc_addr = ia->ia_addr; 347 sc->sc_phandle = ia->ia_cookie; 348 sc->sc_conf = (void *)entry->data; 349 350 memset(&sc->sc_todr, 0, sizeof(sc->sc_todr)); 351 sc->sc_todr.cookie = sc; 352 sc->sc_todr.todr_gettime_ymdhms = rkpmic_todr_gettime; 353 sc->sc_todr.todr_settime_ymdhms = rkpmic_todr_settime; 354 355 aprint_naive("\n"); 356 aprint_normal(": %s Power Management and Real Time Clock IC\n", sc->sc_conf->name); 357 358 I2C_LOCK(sc); 359 chipid = I2C_READ(sc, CHIP_NAME_REG) << 8; 360 chipid |= I2C_READ(sc, CHIP_VER_REG); 361 aprint_debug_dev(self, "Chip ID 0x%04x\n", chipid); 362 I2C_WRITE(sc, RTC_CTRL_REG, 0x0); 363 I2C_WRITE(sc, RTC_INT_REG, 0); 364 I2C_WRITE(sc, RTC_COMP_LSB_REG, 0); 365 I2C_WRITE(sc, RTC_COMP_MSB_REG, 0); 366 I2C_UNLOCK(sc); 367 368 fdtbus_todr_attach(self, sc->sc_phandle, &sc->sc_todr); 369 370 regulators = of_find_firstchild_byname(sc->sc_phandle, "regulators"); 371 if (regulators < 0) 372 return; 373 374 for (n = 0; n < sc->sc_conf->nctrl; n++) { 375 child = of_find_firstchild_byname(regulators, sc->sc_conf->ctrl[n].name); 376 if (child < 0) 377 continue; 378 raa.reg_ctrl = &sc->sc_conf->ctrl[n]; 379 raa.reg_phandle = child; 380 config_found(self, &raa, NULL); 381 } 382 } 383 384 static int 385 rkreg_acquire(device_t dev) 386 { 387 return 0; 388 } 389 390 static void 391 rkreg_release(device_t dev) 392 { 393 } 394 395 static int 396 rkreg_enable(device_t dev, bool enable) 397 { 398 struct rkreg_softc * const sc = device_private(dev); 399 const struct rkpmic_ctrl *c = sc->sc_ctrl; 400 uint8_t val; 401 402 if (!c->enable_mask) 403 return EINVAL; 404 405 I2C_LOCK(sc->sc_pmic); 406 if (c->flags & F_ENABLE_WRITE_MASK) 407 val |= c->enable_mask << 4; 408 else 409 val = I2C_READ(sc->sc_pmic, c->enable_reg); 410 if (enable) 411 val |= c->enable_mask; 412 else 413 val &= ~c->enable_mask; 414 I2C_WRITE(sc->sc_pmic, c->enable_reg, val); 415 I2C_UNLOCK(sc->sc_pmic); 416 417 return 0; 418 } 419 420 static int 421 rkreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol) 422 { 423 struct rkreg_softc * const sc = device_private(dev); 424 const struct rkpmic_ctrl *c = sc->sc_ctrl; 425 uint8_t val; 426 u_int vsel; 427 428 if (!c->vsel_mask) 429 return EINVAL; 430 431 if (min_uvol < c->base) 432 return ERANGE; 433 434 vsel = (min_uvol - c->base) / c->step; 435 if (vsel > __SHIFTOUT_MASK(c->vsel_mask)) 436 return ERANGE; 437 438 I2C_LOCK(sc->sc_pmic); 439 val = I2C_READ(sc->sc_pmic, c->vsel_reg); 440 val &= ~c->vsel_mask; 441 val |= __SHIFTIN(vsel, c->vsel_mask); 442 I2C_WRITE(sc->sc_pmic, c->vsel_reg, val); 443 I2C_UNLOCK(sc->sc_pmic); 444 445 return 0; 446 } 447 448 static int 449 rkreg_get_voltage(device_t dev, u_int *puvol) 450 { 451 struct rkreg_softc * const sc = device_private(dev); 452 const struct rkpmic_ctrl *c = sc->sc_ctrl; 453 uint8_t val; 454 455 if (!c->vsel_mask) 456 return EINVAL; 457 458 I2C_LOCK(sc->sc_pmic); 459 val = I2C_READ(sc->sc_pmic, c->vsel_reg); 460 I2C_UNLOCK(sc->sc_pmic); 461 462 *puvol = __SHIFTOUT(val, c->vsel_mask) * c->step + c->base; 463 464 return 0; 465 } 466 467 static struct fdtbus_regulator_controller_func rkreg_funcs = { 468 .acquire = rkreg_acquire, 469 .release = rkreg_release, 470 .enable = rkreg_enable, 471 .set_voltage = rkreg_set_voltage, 472 .get_voltage = rkreg_get_voltage, 473 }; 474 475 static int 476 rkreg_match(device_t parent, cfdata_t match, void *aux) 477 { 478 return 1; 479 } 480 481 static void 482 rkreg_attach(device_t parent, device_t self, void *aux) 483 { 484 struct rkreg_softc * const sc = device_private(self); 485 struct rkreg_attach_args *raa = aux; 486 const int phandle = raa->reg_phandle; 487 const char *name; 488 489 sc->sc_dev = self; 490 sc->sc_pmic = device_private(parent); 491 sc->sc_ctrl = raa->reg_ctrl; 492 493 fdtbus_register_regulator_controller(self, phandle, 494 &rkreg_funcs); 495 496 aprint_naive("\n"); 497 name = fdtbus_get_string(phandle, "regulator-name"); 498 if (!name) 499 name = fdtbus_get_string(phandle, "name"); 500 aprint_normal(": %s\n", name); 501 } 502 503 CFATTACH_DECL_NEW(rkpmic, sizeof(struct rkpmic_softc), 504 rkpmic_match, rkpmic_attach, NULL, NULL); 505 506 CFATTACH_DECL_NEW(rkreg, sizeof(struct rkreg_softc), 507 rkreg_match, rkreg_attach, NULL, NULL); 508
Indexes created Wed Sep 24 05:09:52 GMT 2025