sdtemp_reg.h revision 1.9
1 /* $NetBSD: sdtemp_reg.h,v 1.9 2016/07/26 07:30:16 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_I2C_SDTEMPREG_H 33 #define _DEV_I2C_SDTEMPREG_H 34 35 /* 36 * Following definitions derived from JEDEC Standard 21-C section 4.7 37 * available at http://www.jedec.org/download/search/4_07R15.pdf 38 */ 39 #define SDTEMP_ADDRMASK 0x3f8 40 #define SDTEMP_ADDR 0x18 /* I2C address 001 1xxx */ 41 42 #define SDTEMP_REG_CAPABILITY 0x00 43 #define SDTEMP_REG_CONFIG 0x01 44 #define SDTEMP_REG_UPPER_LIM 0x02 45 #define SDTEMP_REG_LOWER_LIM 0x03 46 #define SDTEMP_REG_CRIT_LIM 0x04 47 #define SDTEMP_REG_AMBIENT_TEMP 0x05 48 #define SDTEMP_REG_MFG_ID 0x06 49 #define SDTEMP_REG_DEV_REV 0x07 50 51 #define SDTEMP_CAP_HAS_ALARM 0x0001 52 #define SDTEMP_CAP_ACCURACY_1C 0x0002 53 #define SDTEMP_CAP_WIDER_RANGE 0x0004 54 #define SDTEMP_CAP_RESOLUTION 0x0018 55 #define SDTEMP_CAP_RESOLUTION_MAX 0x0003 /* 0.0625C */ 56 #define SDTEMP_CAP_VHV 0x0020 57 #define SDTEMP_CAP_TMOUT 0x0040 58 #define SDTEMP_CAP_EVSD 0x0080 59 60 61 #define SDTEMP_CONFIG_EVENT_MODE 0x0001 62 #define SDTEMP_CONFIG_EVENT_POL_AH 0x0002 63 #define SDTEMP_CONFIG_EVENT_CRIT_ONLY 0x0004 64 #define SDTEMP_CONFIG_EVENT_ENABLED 0x0008 65 #define SDTEMP_CONFIG_EVENT_STATUS 0x0010 66 #define SDTEMP_CONFIG_INT_CLEAR 0x0020 67 #define SDTEMP_CONFIG_WINDOW_LOCKED 0x0040 68 #define SDTEMP_CONFIG_CRITICAL_LOCKED 0x0080 69 #define SDTEMP_CONFIG_SHUTDOWN_MODE 0x0100 70 #define SDTEMP_CONFIG_HYSTERESIS 0x0600 71 72 #define SDTEMP_HYSTERESIS_NONE 0x0000 73 #define SDTEMP_HYSTERESIS_15 0x0200 74 #define SDTEMP_HYSTERESIS_30 0x0400 75 #define SDTEMP_HYSTERESIS_60 0x0600 76 77 /* 78 * Temperature is a 13-bit value in the range of -256 <= x < +256 degrees. 79 * Maximum resolution is 0.0625C (1/16th degree, 4 bits), but some devices 80 * may have only 0.2500C or 0.1250C (1 or 2 bits), and some devices may not 81 * be able to represent negative values (not that we'd expect them, anyway). 82 */ 83 #define SDTEMP_TEMP_MASK 0x0FFF 84 #define SDTEMP_TEMP_NEGATIVE 0x1000 85 #define SDTEMP_TEMP_SIGN_EXT 0xF000 86 87 /* 88 * Status bits set in SDTEMP_REG_AMBIENT_TEMP only 89 */ 90 #define SDTEMP_ABOVE_CRIT 0x8000 91 #define SDTEMP_ABOVE_UPPER 0x4000 92 #define SDTEMP_BELOW_LOWER 0x2000 93 94 /* 95 * Devices known to conform to JEDEC JC42.4 96 */ 97 98 /* Atmel */ 99 #define AT_MANUFACTURER_ID 0x001f 100 #define AT_30TS00_DEVICE_ID 0x8201 /* Also matches 002A and 002B */ 101 #define AT_30TS00_MASK 0xFFFF 102 103 #define AT2_MANUFACTURER_ID 0x1114 104 #define AT2_30TSE004_DEVICE_ID 0x2200 105 #define AT2_30TSE004_MASK 0xFFFF 106 107 /* Giantec Semiconductor */ 108 #define GT_MANUFACTURER_ID 0x1C68 109 #define GT_30TS00_DEVICE_ID 0x2201 110 #define GT_30TS00_MASK 0xFFFF 111 112 #define GT2_MANUFACTURER_ID 0x132D 113 #define GT2_34TS02_DEVICE_ID 0x3300 114 #define GT2_34TS02_MASK 0xFFFF 115 116 /* Maxim */ 117 #define MAXIM_MANUFACTURER_ID 0x004D 118 #define MAX_6604_DEVICE_ID 0x3E00 119 #define MAX_6604_MASK 0xFFFF 120 121 /* Microchip */ 122 #define MCP_MANUFACTURER_ID 0x0054 123 #define MCP_9804_DEVICE_ID 0x0200 124 #define MCP_9804_MASK 0xFFFC 125 #define MCP_9805_DEVICE_ID 0x0000 /* Also matches MCP9843 */ 126 #define MCP_9805_MASK 0xFFFE 127 #define MCP_98242_DEVICE_ID 0x2000 128 #define MCP_98242_MASK 0xFFFC 129 #define MCP_98243_DEVICE_ID 0x2100 130 #define MCP_98243_MASK 0xFFFC 131 #define MCP_98244_DEVICE_ID 0x2200 132 #define MCP_98244_MASK 0xFFFC 133 134 #define SDTEMP_REG_MCP_RESOLUTION_9804 0x08 /* 9804, 9824[23] */ 135 #define SDTEMP_REG_MCP_RESOLUTION_98244 0x09 /* 98244 */ 136 137 /* NXP Semiconductors */ 138 /* According to datasheets, SE97 and SE98 have same ID */ 139 #define NXP_MANUFACTURER_ID 0x1131 140 #define NXP_SE98_DEVICE_ID 0xA100 141 #define NXP_SE98_MASK 0xFFFC 142 #define NXP_SE97_DEVICE_ID 0xA200 143 #define NXP_SE97_MASK 0xFFFC 144 145 /* Analog Devices */ 146 #define ADT_MANUFACTURER_ID 0x11D4 147 #define ADT_7408_DEVICE_ID 0x8001 148 #define ADT_7408_MASK 0xFFFF 149 150 /* IDT */ 151 #define IDT_MANUFACTURER_ID 0x00B3 152 #define IDT_TS3000B3_DEVICE_ID 0x2903 /* Also matches TSE2002B3 */ 153 #define IDT_TS3000B3_MASK 0xFFFF 154 #define IDT_TS3000GB0_DEVICE_ID 0x2913 155 #define IDT_TS3000GB0_MASK 0xFFFF 156 #define IDT_TS3000GB2_DEVICE_ID 0x2912 157 #define IDT_TS3000GB2_MASK 0xFFFF 158 #define IDT_TS3001GB2_DEVICE_ID 0x3001 159 #define IDT_TS3001GB2_MASK 0xFFFF 160 #define IDT_TSE2002GB2_DEVICE_ID 0x2912 161 #define IDT_TSE2002GB2_MASK 0xFFFF 162 #define IDT_TSE2004GB2_DEVICE_ID 0x2214 163 #define IDT_TSE2004GB2_MASK 0xFFFF 164 165 #define SDTEMP_REG_IDT_RESOLUTION 0x08 /* 2002 */ 166 167 /* STmicroelectronics */ 168 #define STTS_MANUFACTURER_ID 0x104A 169 #define STTS_424_DEVICE_ID 0x0101 170 #define STTS_424_MASK 0xFFFF 171 #define STTS_424E_DEVICE_ID 0x0000 172 #define STTS_424E_MASK 0xFFFE 173 #define STTS_3000_DEVICE_ID 0x0200 174 #define STTS_3000_MASK 0xFFFF 175 #define STTS_2002_DEVICE_ID 0x0300 176 #define STTS_2002_MASK 0xFFFF 177 #define STTS_2004_DEVICE_ID 0x2201 178 #define STTS_2004_MASK 0xFFFF 179 180 /* On Semiconductor (Catalyst) */ 181 /* According to datasheets, both the CAT6095 and CAT34TS02 have the same ID */ 182 #define CAT_MANUFACTURER_ID 0x1B09 183 #define CAT_34TS02_DEVICE_ID 0x0800 184 #define CAT_34TS02_MASK 0xFFE0 185 #define CAT_34TS02C_DEVICE_ID 0x0a00 186 #define CAT_34TS02C_MASK 0xFFFF 187 #define CAT_34TS04_DEVICE_ID 0x2200 188 #define CAT_34TS04_MASK 0xFFFF 189 190 #endif /* _DEV_I2C_SDTEMPREG_H */ 191
Indexes created Wed Sep 24 05:09:52 GMT 2025