ssdfb_i2c.c revision 1.6 1 1.6 thorpej /* $NetBSD: ssdfb_i2c.c,v 1.6 2021/01/17 21:42:35 thorpej Exp $ */
2 1.1 tnn
3 1.1 tnn /*
4 1.1 tnn * Copyright (c) 2019 The NetBSD Foundation, Inc.
5 1.1 tnn * All rights reserved.
6 1.1 tnn *
7 1.1 tnn * This code is derived from software contributed to The NetBSD Foundation
8 1.1 tnn * by Tobias Nygren.
9 1.1 tnn *
10 1.1 tnn * Redistribution and use in source and binary forms, with or without
11 1.1 tnn * modification, are permitted provided that the following conditions
12 1.1 tnn * are met:
13 1.1 tnn * 1. Redistributions of source code must retain the above copyright
14 1.1 tnn * notice, this list of conditions and the following disclaimer.
15 1.1 tnn * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 tnn * notice, this list of conditions and the following disclaimer in the
17 1.1 tnn * documentation and/or other materials provided with the distribution.
18 1.1 tnn *
19 1.1 tnn * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 tnn * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 tnn * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 tnn * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 tnn * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 tnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 tnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 tnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 tnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 tnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 tnn * POSSIBILITY OF SUCH DAMAGE.
30 1.1 tnn */
31 1.1 tnn
32 1.1 tnn #include <sys/cdefs.h>
33 1.6 thorpej __KERNEL_RCSID(0, "$NetBSD: ssdfb_i2c.c,v 1.6 2021/01/17 21:42:35 thorpej Exp $");
34 1.1 tnn
35 1.1 tnn #include <sys/param.h>
36 1.1 tnn #include <sys/device.h>
37 1.1 tnn #include <dev/wscons/wsdisplayvar.h>
38 1.1 tnn #include <dev/rasops/rasops.h>
39 1.1 tnn #include <dev/i2c/i2cvar.h>
40 1.1 tnn #include <dev/ic/ssdfbvar.h>
41 1.1 tnn
42 1.1 tnn struct ssdfb_i2c_softc {
43 1.1 tnn struct ssdfb_softc sc;
44 1.1 tnn i2c_tag_t sc_i2c_tag;
45 1.1 tnn i2c_addr_t sc_i2c_addr;
46 1.5 tnn size_t sc_transfer_size;
47 1.1 tnn };
48 1.1 tnn
49 1.1 tnn static int ssdfb_i2c_match(device_t, cfdata_t, void *);
50 1.1 tnn static void ssdfb_i2c_attach(device_t, device_t, void *);
51 1.1 tnn static int ssdfb_i2c_detach(device_t, int);
52 1.1 tnn
53 1.5 tnn static int ssdfb_i2c_probe_transfer_size(struct ssdfb_i2c_softc *, bool);
54 1.5 tnn static int ssdfb_i2c_transfer(struct ssdfb_i2c_softc *, uint8_t, uint8_t *,
55 1.5 tnn size_t, int);
56 1.1 tnn static int ssdfb_i2c_cmd(void *, uint8_t *, size_t, bool);
57 1.1 tnn static int ssdfb_i2c_transfer_rect(void *, uint8_t, uint8_t, uint8_t,
58 1.1 tnn uint8_t, uint8_t *, size_t, bool);
59 1.1 tnn static int ssdfb_i2c_transfer_rect_ssd1306(void *, uint8_t, uint8_t,
60 1.1 tnn uint8_t, uint8_t, uint8_t *, size_t, bool);
61 1.1 tnn static int ssdfb_i2c_transfer_rect_sh1106(void *, uint8_t, uint8_t,
62 1.1 tnn uint8_t, uint8_t, uint8_t *, size_t, bool);
63 1.1 tnn static int ssdfb_smbus_transfer_rect(void *, uint8_t, uint8_t, uint8_t,
64 1.1 tnn uint8_t, uint8_t *, size_t, bool);
65 1.1 tnn
66 1.1 tnn CFATTACH_DECL_NEW(ssdfb_iic, sizeof(struct ssdfb_i2c_softc),
67 1.1 tnn ssdfb_i2c_match, ssdfb_i2c_attach, ssdfb_i2c_detach, NULL);
68 1.1 tnn
69 1.1 tnn static const struct device_compatible_entry compat_data[] = {
70 1.6 thorpej { .compat = "solomon,ssd1306fb-i2c" },
71 1.6 thorpej { .compat = "sino,sh1106fb-i2c" },
72 1.6 thorpej
73 1.6 thorpej { 0 }
74 1.1 tnn };
75 1.1 tnn
76 1.1 tnn static int
77 1.1 tnn ssdfb_i2c_match(device_t parent, cfdata_t match, void *aux)
78 1.1 tnn {
79 1.1 tnn struct i2c_attach_args *ia = aux;
80 1.1 tnn int match_result;
81 1.1 tnn
82 1.1 tnn if (iic_use_direct_match(ia, match, compat_data, &match_result))
83 1.1 tnn return match_result;
84 1.1 tnn
85 1.1 tnn switch (ia->ia_addr) {
86 1.1 tnn case SSDFB_I2C_DEFAULT_ADDR:
87 1.1 tnn case SSDFB_I2C_ALTERNATIVE_ADDR:
88 1.1 tnn return I2C_MATCH_ADDRESS_ONLY;
89 1.1 tnn }
90 1.1 tnn
91 1.1 tnn return 0;
92 1.1 tnn }
93 1.1 tnn
94 1.1 tnn static void
95 1.1 tnn ssdfb_i2c_attach(device_t parent, device_t self, void *aux)
96 1.1 tnn {
97 1.1 tnn struct ssdfb_i2c_softc *sc = device_private(self);
98 1.1 tnn struct cfdata *cf = device_cfdata(self);
99 1.1 tnn struct i2c_attach_args *ia = aux;
100 1.1 tnn int flags = cf->cf_flags;
101 1.1 tnn int i;
102 1.1 tnn
103 1.1 tnn if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN) {
104 1.1 tnn for (i = 0; i < ia->ia_ncompat; i++) {
105 1.1 tnn if (strncmp("solomon,ssd1306", ia->ia_compat[i], 15)
106 1.1 tnn == 0) {
107 1.1 tnn flags |= SSDFB_PRODUCT_SSD1306_GENERIC;
108 1.1 tnn break;
109 1.1 tnn }
110 1.1 tnn else if (strncmp("sino,sh1106", ia->ia_compat[i], 11)
111 1.1 tnn == 0) {
112 1.1 tnn flags |= SSDFB_PRODUCT_SH1106_GENERIC;
113 1.1 tnn break;
114 1.1 tnn }
115 1.1 tnn }
116 1.1 tnn }
117 1.1 tnn if ((flags & SSDFB_ATTACH_FLAG_PRODUCT_MASK) == SSDFB_PRODUCT_UNKNOWN)
118 1.1 tnn flags |= SSDFB_PRODUCT_SSD1306_GENERIC;
119 1.1 tnn
120 1.4 tnn flags |= SSDFB_ATTACH_FLAG_MPSAFE;
121 1.1 tnn sc->sc.sc_dev = self;
122 1.1 tnn sc->sc_i2c_tag = ia->ia_tag;
123 1.1 tnn sc->sc_i2c_addr = ia->ia_addr;
124 1.1 tnn sc->sc.sc_cookie = (void *)sc;
125 1.1 tnn sc->sc.sc_cmd = ssdfb_i2c_cmd;
126 1.1 tnn sc->sc.sc_transfer_rect = ssdfb_i2c_transfer_rect;
127 1.1 tnn
128 1.1 tnn ssdfb_attach(&sc->sc, flags);
129 1.1 tnn }
130 1.1 tnn
131 1.1 tnn static int
132 1.1 tnn ssdfb_i2c_detach(device_t self, int flags)
133 1.1 tnn {
134 1.1 tnn struct ssdfb_i2c_softc *sc = device_private(self);
135 1.1 tnn
136 1.1 tnn return ssdfb_detach(&sc->sc);
137 1.1 tnn }
138 1.1 tnn
139 1.1 tnn static int
140 1.5 tnn ssdfb_i2c_probe_transfer_size(struct ssdfb_i2c_softc *sc, bool usepoll)
141 1.5 tnn {
142 1.5 tnn int flags = usepoll ? I2C_F_POLL : 0;
143 1.5 tnn uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK;
144 1.5 tnn int error;
145 1.5 tnn uint8_t buf[128];
146 1.5 tnn size_t len;
147 1.5 tnn
148 1.5 tnn error = iic_acquire_bus(sc->sc_i2c_tag, flags);
149 1.5 tnn if (error)
150 1.5 tnn return error;
151 1.5 tnn len = sizeof(buf);
152 1.5 tnn memset(buf, 0, len);
153 1.5 tnn while (len > 0) {
154 1.5 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
155 1.5 tnn sc->sc_i2c_addr, &cb, sizeof(cb), buf, len, flags);
156 1.5 tnn if (!error) {
157 1.5 tnn break;
158 1.5 tnn }
159 1.5 tnn len >>= 1;
160 1.5 tnn }
161 1.5 tnn if (!error && len < 2) {
162 1.5 tnn error = E2BIG;
163 1.5 tnn } else {
164 1.5 tnn sc->sc_transfer_size = len;
165 1.5 tnn }
166 1.5 tnn (void) iic_release_bus(sc->sc_i2c_tag, flags);
167 1.5 tnn
168 1.5 tnn return error;
169 1.5 tnn }
170 1.5 tnn
171 1.5 tnn static int
172 1.5 tnn ssdfb_i2c_transfer(struct ssdfb_i2c_softc *sc, uint8_t cb, uint8_t *data,
173 1.5 tnn size_t len, int flags)
174 1.5 tnn {
175 1.5 tnn int error;
176 1.5 tnn size_t xfer_size = sc->sc_transfer_size;
177 1.5 tnn
178 1.5 tnn while (len >= xfer_size) {
179 1.5 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
180 1.5 tnn sc->sc_i2c_addr, &cb, sizeof(cb), data, xfer_size, flags);
181 1.5 tnn if (error)
182 1.5 tnn return error;
183 1.5 tnn len -= xfer_size;
184 1.5 tnn data += xfer_size;
185 1.5 tnn }
186 1.5 tnn if (len > 0) {
187 1.5 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
188 1.5 tnn sc->sc_i2c_addr, &cb, sizeof(cb), data, len, flags);
189 1.5 tnn }
190 1.5 tnn
191 1.5 tnn return error;
192 1.5 tnn }
193 1.5 tnn
194 1.5 tnn static int
195 1.1 tnn ssdfb_i2c_cmd(void *cookie, uint8_t *cmd, size_t len, bool usepoll)
196 1.1 tnn {
197 1.1 tnn struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie;
198 1.1 tnn int flags = usepoll ? I2C_F_POLL : 0;
199 1.1 tnn uint8_t cb = 0;
200 1.1 tnn int error;
201 1.1 tnn
202 1.1 tnn error = iic_acquire_bus(sc->sc_i2c_tag, flags);
203 1.1 tnn if (error)
204 1.1 tnn return error;
205 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
206 1.1 tnn sc->sc_i2c_addr, &cb, sizeof(cb), cmd, len, flags);
207 1.1 tnn (void) iic_release_bus(sc->sc_i2c_tag, flags);
208 1.1 tnn
209 1.1 tnn return error;
210 1.1 tnn }
211 1.1 tnn
212 1.1 tnn static int
213 1.1 tnn ssdfb_i2c_transfer_rect(void *cookie, uint8_t fromcol, uint8_t tocol,
214 1.1 tnn uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll)
215 1.1 tnn {
216 1.1 tnn struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie;
217 1.1 tnn uint8_t cmd[2];
218 1.1 tnn int error;
219 1.1 tnn
220 1.1 tnn /*
221 1.1 tnn * Test if large transfers are supported by the parent i2c bus and
222 1.1 tnn * pick the fastest transfer routine for subsequent invocations.
223 1.1 tnn */
224 1.1 tnn switch (sc->sc.sc_p->p_controller_id) {
225 1.1 tnn case SSDFB_CONTROLLER_SSD1306:
226 1.1 tnn sc->sc.sc_transfer_rect = ssdfb_i2c_transfer_rect_ssd1306;
227 1.1 tnn break;
228 1.1 tnn case SSDFB_CONTROLLER_SH1106:
229 1.1 tnn sc->sc.sc_transfer_rect = ssdfb_i2c_transfer_rect_sh1106;
230 1.1 tnn break;
231 1.1 tnn default:
232 1.1 tnn sc->sc.sc_transfer_rect = ssdfb_smbus_transfer_rect;
233 1.1 tnn break;
234 1.1 tnn }
235 1.1 tnn
236 1.1 tnn if (sc->sc.sc_transfer_rect != ssdfb_smbus_transfer_rect) {
237 1.5 tnn error = ssdfb_i2c_probe_transfer_size(sc, usepoll);
238 1.1 tnn if (error)
239 1.1 tnn return error;
240 1.5 tnn aprint_verbose_dev(sc->sc.sc_dev, "%zd-byte transfers\n",
241 1.5 tnn sc->sc_transfer_size);
242 1.5 tnn if (sc->sc_transfer_size == 2) {
243 1.1 tnn sc->sc.sc_transfer_rect = ssdfb_smbus_transfer_rect;
244 1.1 tnn }
245 1.1 tnn }
246 1.1 tnn
247 1.1 tnn /*
248 1.1 tnn * Set addressing mode for SSD1306.
249 1.1 tnn */
250 1.1 tnn if (sc->sc.sc_p->p_controller_id == SSDFB_CONTROLLER_SSD1306) {
251 1.1 tnn cmd[0] = SSD1306_CMD_SET_MEMORY_ADDRESSING_MODE;
252 1.1 tnn cmd[1] = sc->sc.sc_transfer_rect
253 1.1 tnn == ssdfb_i2c_transfer_rect_ssd1306
254 1.1 tnn ? SSD1306_MEMORY_ADDRESSING_MODE_HORIZONTAL
255 1.1 tnn : SSD1306_MEMORY_ADDRESSING_MODE_PAGE;
256 1.1 tnn error = ssdfb_i2c_cmd(cookie, cmd, sizeof(cmd), usepoll);
257 1.1 tnn if (error)
258 1.1 tnn return error;
259 1.1 tnn }
260 1.1 tnn
261 1.1 tnn return sc->sc.sc_transfer_rect(cookie, fromcol, tocol, frompage, topage,
262 1.1 tnn p, stride, usepoll);
263 1.1 tnn }
264 1.1 tnn
265 1.1 tnn
266 1.1 tnn static int
267 1.1 tnn ssdfb_i2c_transfer_rect_ssd1306(void *cookie, uint8_t fromcol, uint8_t tocol,
268 1.1 tnn uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll)
269 1.1 tnn {
270 1.1 tnn struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie;
271 1.1 tnn int flags = usepoll ? I2C_F_POLL : 0;
272 1.1 tnn uint8_t cc = 0;
273 1.1 tnn uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK;
274 1.3 tnn size_t len = tocol + 1 - fromcol;
275 1.1 tnn int error;
276 1.1 tnn /*
277 1.1 tnn * SSD1306 does not implement the Continuation bit correctly.
278 1.1 tnn * The SH1106 protocol defines that a control byte WITH Co
279 1.1 tnn * set must be inserted between each command. But SSD1306
280 1.1 tnn * fails to parse the commands if we do that.
281 1.1 tnn */
282 1.1 tnn uint8_t cmds[] = {
283 1.1 tnn SSD1306_CMD_SET_COLUMN_ADDRESS,
284 1.1 tnn fromcol, tocol,
285 1.1 tnn SSD1306_CMD_SET_PAGE_ADDRESS,
286 1.1 tnn frompage, topage
287 1.1 tnn };
288 1.1 tnn
289 1.1 tnn error = iic_acquire_bus(sc->sc_i2c_tag, flags);
290 1.1 tnn if (error)
291 1.1 tnn return error;
292 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
293 1.1 tnn sc->sc_i2c_addr, &cc, sizeof(cc), cmds, sizeof(cmds), flags);
294 1.1 tnn if (error)
295 1.1 tnn goto out;
296 1.1 tnn while (frompage <= topage) {
297 1.5 tnn error = ssdfb_i2c_transfer(sc, cb, p, len, flags);
298 1.1 tnn if (error)
299 1.1 tnn goto out;
300 1.1 tnn frompage++;
301 1.1 tnn p += stride;
302 1.1 tnn }
303 1.1 tnn out:
304 1.1 tnn (void) iic_release_bus(sc->sc_i2c_tag, flags);
305 1.1 tnn
306 1.1 tnn return error;
307 1.1 tnn }
308 1.1 tnn
309 1.1 tnn static int
310 1.1 tnn ssdfb_i2c_transfer_rect_sh1106(void *cookie, uint8_t fromcol, uint8_t tocol,
311 1.1 tnn uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll)
312 1.1 tnn {
313 1.1 tnn struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie;
314 1.1 tnn int flags = usepoll ? I2C_F_POLL : 0;
315 1.1 tnn uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK;
316 1.1 tnn uint8_t cc = SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK;
317 1.3 tnn size_t len = tocol + 1 - fromcol;
318 1.1 tnn int error;
319 1.1 tnn uint8_t cmds[] = {
320 1.1 tnn SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE + frompage,
321 1.1 tnn SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK,
322 1.1 tnn SSDFB_CMD_SET_HIGHER_COLUMN_START_ADDRESS_BASE + (fromcol >> 4),
323 1.1 tnn SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK,
324 1.1 tnn SSDFB_CMD_SET_LOWER_COLUMN_START_ADDRESS_BASE + (fromcol & 0xf)
325 1.1 tnn };
326 1.1 tnn
327 1.1 tnn error = iic_acquire_bus(sc->sc_i2c_tag, flags);
328 1.1 tnn if (error)
329 1.1 tnn return error;
330 1.1 tnn while (frompage <= topage) {
331 1.1 tnn cmds[0] = SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE + frompage;
332 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
333 1.1 tnn sc->sc_i2c_addr, &cc, sizeof(cc), cmds, sizeof(cmds), flags);
334 1.1 tnn if (error)
335 1.1 tnn goto out;
336 1.5 tnn error = ssdfb_i2c_transfer(sc, cb, p, len, flags);
337 1.1 tnn if (error)
338 1.1 tnn goto out;
339 1.1 tnn frompage++;
340 1.1 tnn p += stride;
341 1.1 tnn }
342 1.1 tnn out:
343 1.1 tnn (void) iic_release_bus(sc->sc_i2c_tag, flags);
344 1.1 tnn
345 1.1 tnn return error;
346 1.1 tnn }
347 1.1 tnn
348 1.1 tnn /*
349 1.1 tnn * If the parent is an SMBus, then we can only send 2 bytes
350 1.1 tnn * of payload per txn. The SSD1306 triple byte commands are
351 1.1 tnn * not available so we have to use PAGE addressing mode
352 1.1 tnn * and split data into multiple txns.
353 1.1 tnn * This is ugly and slow but it's the best we can do.
354 1.1 tnn */
355 1.1 tnn static int
356 1.1 tnn ssdfb_smbus_transfer_rect(void *cookie, uint8_t fromcol, uint8_t tocol,
357 1.1 tnn uint8_t frompage, uint8_t topage, uint8_t *p, size_t stride, bool usepoll)
358 1.1 tnn {
359 1.1 tnn struct ssdfb_i2c_softc *sc = (struct ssdfb_i2c_softc *)cookie;
360 1.1 tnn int flags = usepoll ? I2C_F_POLL : 0;
361 1.1 tnn uint8_t cb = SSDFB_I2C_CTRL_BYTE_DATA_MASK;
362 1.1 tnn uint8_t cc = 0;
363 1.3 tnn size_t len = tocol + 1 - fromcol;
364 1.1 tnn uint8_t cmd_higher_col =
365 1.1 tnn SSDFB_CMD_SET_HIGHER_COLUMN_START_ADDRESS_BASE + (fromcol >> 4);
366 1.1 tnn uint8_t cmd_lower_col =
367 1.1 tnn SSDFB_CMD_SET_LOWER_COLUMN_START_ADDRESS_BASE + (fromcol & 0xf);
368 1.1 tnn uint8_t cmd_page;
369 1.1 tnn uint8_t data[2];
370 1.1 tnn uint8_t *colp;
371 1.1 tnn uint8_t *endp;
372 1.1 tnn int error;
373 1.1 tnn
374 1.1 tnn error = iic_acquire_bus(sc->sc_i2c_tag, flags);
375 1.1 tnn if (error)
376 1.1 tnn return error;
377 1.1 tnn while (frompage <= topage) {
378 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
379 1.1 tnn sc->sc_i2c_addr, &cc, sizeof(cc),
380 1.1 tnn &cmd_higher_col, sizeof(cmd_higher_col), flags);
381 1.1 tnn if (error)
382 1.1 tnn goto out;
383 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
384 1.1 tnn sc->sc_i2c_addr, &cc, sizeof(cc),
385 1.1 tnn &cmd_lower_col, sizeof(cmd_lower_col), flags);
386 1.1 tnn if (error)
387 1.1 tnn goto out;
388 1.1 tnn cmd_page = SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE + frompage;
389 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
390 1.1 tnn sc->sc_i2c_addr, &cc, sizeof(cc),
391 1.1 tnn &cmd_page, sizeof(cmd_page), flags);
392 1.1 tnn if (error)
393 1.1 tnn goto out;
394 1.1 tnn colp = p;
395 1.1 tnn endp = colp + len;
396 1.1 tnn if (len & 1) {
397 1.1 tnn data[0] = *colp++;
398 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
399 1.1 tnn sc->sc_i2c_addr, &cb, sizeof(cb), data, 1, flags);
400 1.1 tnn if (error)
401 1.1 tnn goto out;
402 1.1 tnn }
403 1.1 tnn while (colp < endp) {
404 1.1 tnn /*
405 1.1 tnn * Send two bytes at a time. We can't use colp directly
406 1.1 tnn * because i2c controllers sometimes have data alignment
407 1.1 tnn * requirements.
408 1.1 tnn */
409 1.1 tnn data[0] = *colp++;
410 1.1 tnn data[1] = *colp++;
411 1.1 tnn error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
412 1.1 tnn sc->sc_i2c_addr, &cb, sizeof(cb), data, 2, flags);
413 1.1 tnn if (error)
414 1.1 tnn goto out;
415 1.1 tnn }
416 1.1 tnn frompage++;
417 1.1 tnn p += stride;
418 1.1 tnn }
419 1.1 tnn out:
420 1.1 tnn (void) iic_release_bus(sc->sc_i2c_tag, flags);
421 1.5 tnn
422 1.1 tnn return error;
423 1.1 tnn }
424